Edge termination strategies for a 4 kV 4H–SiC thyristor

Thyristors able to block 4 kV have been fabricated and characterised. The experimental forward current is 1.3 A @ V_AK = 10 V for a 9 mA gate current during 550 ns. The device active area is 2.3 mm². The devices and their edge terminations have been designed using numerical simulations. Two different edge terminations have been envisaged (mesa and a combination of mesa and JTE). A SiO₂ passivation layer also improves the forward blocking voltage depending on the sign and the magnitude of the effective charge density in the oxide. The mesa protection is not enough to allowing the thyristor to block 5 kV, due to the low etching rate in SiC. Thus, a mesa/JTE protection has been used. The influence of the etching depth, the JTE dose and length on the forward blocking voltage of the thyristor has been studied in details. Simulation results have allowed designing the devices, not far from the optimal structure. The best results of the forward blocking voltage are 4 kV for the mesa protected thyristor, while the mesa/JTE combination yields 3.6 kV. Furthermore, experimental results confirm the simulations concerning the influence of the oxide thickness on the forward blocking voltage. The better results for the mesa protected thyristor are due to a lower interface SiC/SiO₂ charge density provided by the different oxidation processes (at different foundries).In addition, the comparison between experiments and simulations allows estimate the effective charge density of the SiO₂ layer in 10¹²–5 × 10¹² cm⁻² range for the two fabricated thyristors. The improvement in the forward blocking voltage must pass through an improvement of the passivation layer. Passivation still remains a technological key step to obtain SiC high-voltage devices.     

Resistive switching properties of a thin SiO2 layer with CeOx buffer layer on n+ and p+ Si bottom electrodes

Resistive switching properties of a 2-nm-thick SiO₂ with a CeO_x buffer layer on p⁺ and n⁺ Si bottom electrodes were characterized. The distribution of set voltage (V_set) with the p⁺ Si bottom electrode devices reveals a Gaussian distribution centered in 4.5 V, which reflects a stochastic nature of the breakdown of the thin SiO₂. Capacitance–voltage (C–V) measurements indicate the trapping of electrons by positively shifting the C–V curve by 0.2 V during the first switching cycle. On the other hand, devices with the n⁺ Si bottom electrodes showed a broad distribution in V_set with a mean value higher than that of p⁺ Si bottom electrode devices by 0.9 V. Although no charge trapping was observed with n⁺ Si bottom electrode devices, a degradation in interface states was confirmed, causing a tail in the lower side of the V_set distribution. Based on the above measurements, the difference in the V_set can be understood by the work function difference and the contribution of electron trapping.     

Characterization of interfacial reaction and chemical bonding features of LaOx/HfO2 stack structure formed on thermally-grown SiO2/Si(1 0 0)

A stack structure consisting of ～1.5 nm-thick LaO_x and ～4.0 nm-thick HfO₂ was formed on thermally grown SiO₂ on Si(1 0 0) by MOCVD using dipivaloymethanato precursors, and the influence of N₂ annealing on interfacial reaction for this stack structure was examined by using X-ray photoelectron spectroscopy and Fourier transform infrared attenuated total reflection. We found that compositional mixing between LaO_x and HfO₂ becomes significant from 600 °C upwards and that interfacial reaction between HfLa_yO_z and SiO₂ proceeds consistently at 1000 °C in N₂ ambience.     

High thermal annealing effect on structural and optical properties of ZnO–SiO2 nanocomposite

The effect of annealing temperature on photoluminescence (PL) of ZnO–SiO₂ nanocomposite was investigated. The ZnO–SiO₂ nanocomposite was annealed at different temperatures from 600 °C to 1000 °C with a step of 100 °C. High Resolution Transmission Electron Microscope (HR-TEM) pictures showed ZnO nanoparticles of 5 nm are capped with amorphous SiO₂ matrix. Field Emission Scanning Electron Microscope (FE-SEM) pictures showed that samples exhibit spherical morphology up to 800 °C and dumbbell morphology above 800 °C. The absorption spectrum of ZnO–SiO₂ nanocomposite suffers a blue-shift from 369 nm to 365 nm with increase of temperature from 800 °C to 1000 °C. The PL spectrum of ZnO–SiO₂ nanocomposite exhibited an UV emission positioned at 396 nm. The UV emission intensity increased as the temperature increased from 600 °C to 700 °C and then decreased for samples annealed at and above 800^°C. The XRD results showed that formation of willemite phase starts at 800 °C and pure willemite phase formed at 1000 °C. The decrease of the intensity of 396 nm emission peak at 900 °C and 1000 °C is due to the collapse of the ZnO hexagonal structure. This is due to the dominant diffusion of Zn into SiO₂ at these temperatures. At 1000 °C, an emission peak at 388 nm is observed in addition to UV emission of ZnO at 396 nm and is believed to be originated from the willemite.     

A 5-GHz LC VCO with digital AAC and AFBS for 2.4 GHz ZigBee transceiver applications

A 5 GHz LC VCO (voltage-controlled oscillator) with automatic amplitude control (AAC) and automatic frequency-band selection (AFBS) for 2.4 GHz ZigBee transceivers is presented. Instead of continuous feedback loop, an alternative amplitude calibration scheme is proposed in this paper to alleviate the deficiencies inherent in the conventional approach. It helps to keep the VCO at optimum amplitude to avoid saturation of the cross-coupled transistors and therefore stabilizes the phase noise performance over process, voltage and temperature variations. For the ZigBee application with 16 frequency channels, a coarse tuning loop is added in this work to implement the frequency-band selection using the AFBS mechanism. The VCO core and the digital AAC, AFBS modules have been fully integrated in a 2.4 GHz ZigBee transceiver which was fabricated in a 0.18 μm RF-CMOS technology. The current consumption is 4.7 mA at 4.85 GHz with 1.8 V power supply and a chip area of about 0.285 mm² is occupied. The VCO is capable of operating from 4.67 GHz to 5.18 GHz and the measured phase-noise level is –120 dBc/Hz at 1 MHz offset from a 4.85 GHz carrier. The tuning sensitivity K_VCO of the VCO is about 78 MHz/V with 0.9 V control voltage.     

Highly ordered C60 films on epitaxial Fe/MgO(0 0 1) surfaces for organic spintronics

Hybrid interfaces between ferromagnetic surfaces and carbon-based molecules play an important role in organic spintronics. The fabrication of devices with well defined interfaces remains challenging, however, hampering microscopic understanding of their operation mechanisms. We have studied the crystallinity and molecular ordering of C₆₀ films on epitaxial Fe/MgO(0 0 1) surfaces, using X-ray diffraction and scanning tunneling microscopy (STM). Both techniques confirm that fcc molecular C₆₀ films with a (1 1 1)-texture can be fabricated on epitaxial bcc-Fe(0 0 1) surfaces at elevated growth temperatures (100–130 °C). STM measurements show that C₆₀ monolayers deposited at 130 °C are highly ordered, exhibiting quasi-hexagonal arrangements on the Fe(0 0 1) surface oriented along the [1 0 0] and [0 1 0] directions. The mismatch between the surface lattice of the monolayer and the bulk fcc C₆₀ lattice prevents epitaxial overgrowth of multilayers.     

Effect of high-temperature annealing on lanthanum aluminate thin films grown by ALD on Si(1 0 0)

Amorphous lanthanum aluminate thin films were deposited by atomic layer deposition on Si(1 0 0) using La(ⁱPrCp)₃, Al(CH₃)₃ and O₃ species. The effects of post-deposition rapid thermal annealing on the physical and electrical properties of the films were investigated. High-temperature annealing at 900 °C in N₂ atmosphere leads to the formation of amorphous La-aluminosilicate due to Si diffusion from the substrate. The annealed oxide exhibits a uniform composition through the film thickness, a large band gap of 7.0 ± 0.1 eV, and relatively high dielectric constant (κ) of 18 ± 1.     

Reliability of 100 nm AlGaN/GaN HEMTs for mm-wave applications

The effect of gate metallization and gate shape on the reliability and RF performance of 100 nm AlGaN/GaN HEMTs on SiC substrate for mm-wave applications has been investigated under on-state DC-stress tests. By replacing the gate metallization from NiPtAu to PtAu the median time to failure at T_ch = 209 °C can be improved from 10 h to more than 1000 h. Replacing the PtAu T-gate by a spacer gate further reduces the degradation rate under on-state stress, but decreases the current-gain cut-off frequency from 75 GHz to 50 GHz. Physical failure analysis using electroluminescence and TEM cross-section revealed pit and Ni void formation at the gate foot as the main degradation mechanisms of devices with NiPtAu T-gate. High resolution EDX mapping of stressed devices indicates that the formation of pits is caused by a local aluminium oxidation process. Simulation of the stress induced changes of the input characteristics of devices with NiPtAu gate further proves the formation of pits and Ni voids.     

High fluence 1.8 MeV proton irradiation effects on n-type MOS capacitors

MOS capacitors with 7 nm SiO₂ dielectrics and n-doped Si substrate were irradiated by 1.8 MeV protons with fluences ranging from 10¹² to 5 × 10¹³ cm^?2 which correspond to the typical LHC fluence range. No significant increase in gate oxide leakage current was detected. A decrease of the capacitance was observed in the accumulation regime. This effect is explained by an increase of the substrate resistivity caused by displacement damage.     

Performance assessment of (1 1 0) p-FET high-κ/MG: is it mobility or series resistance limited?

In this article the impact of Si-substrate orientation on mobility performance is studied for p-MOSFET’s with both HfSiON and SiON based dielectrics. Consistent with previous studies, the I_on at fixed I_off is 100% larger for Si(1 1 0) larger than for standard Si(1 0 0). A thorough analysis of the factors influencing I_on (EOT, mobility and R_series) for short channel devices (until L_met = 80 nm) indicates that a 200% increase of the mobility at high V_g is the source of this performance enhancement. The lower I_on increase (only 100%) compared to what is expected from the mobility is only explained by a larger impact of the R_series (70% of the total resistance) for short channel devices. As a result additional room for I_on improvement can be reached by device and R_series optimization.     

DC and microwave characteristics of Lg 50 nm T-gate InAlN/AlN/GaN HEMT for future high power RF applications

The DC and microwave characteristics of L_g = 50 nm T-gate InAlN/AlN/GaN High Electron Mobility Transistor (HEMT) on SiC substrate with heavily doped n+ GaN source and drain regions have demonstrated using Synopsys TCAD tool. The proposed device features an AlN spacer layer, AlGaN back-barrier and SiN surface passivation. The proposed HEMT exhibits a maximum drain current density of 1.8 A/mm, peak transconductance (g_m) of 650 mS/mm and ft/fmax of 118/210 GHz. At room temperature, the measured carrier mobility, sheet charge carrier density (n_s) and breakdown voltage are 1195 cm²/Vs, 1.6 × 10¹³ cm⁻² and 18 V respectively. The superlatives of the proposed HEMTs are bewitching competitor for future monolithic microwave integrated circuits (MMIC) applications particularly in W-band (75–110 GHz) high power RF applications.     

105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers

We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105 nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart Cut^TM process to fabricate 200 mm GeOI wafers with Ge thickness down to 60–80 nm. A full Si MOS compatible pMOSFET process was implemented with HfO₂/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (I_ON, I_OFF, transconductance, low field mobility, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties (μ_h ～ 250 cm²/V/s, I_ON = 436 μA/μm for L_G = 105 nm), and OFF current densities comparable or better than those reported in the literature.     

A 24 W Ku band GaN based power amplifier with 9.1 dB linear gain

A Ku-band power amplifier is successfully developed with a single chip 4.8 mm AlGaN/GaN high electron mobility transistors (HEMTs). The AlGaN/GaN HEMTs device, achieved by E-beam lithography г-gate process, exhibited a gate-drain reverse breakdown voltage of larger than 100 V, a cutoff frequency of f_T=30 GHz and a maximum available gain of 13 dB at 14 GHz. The pulsed condition (100 μs pulse period and 10% duty cycle) was used to test the power characteristic of the power amplifier. At the frequency of 13.9 GHz, the developed GaN HEMTs power amplifier delivers a 43.8 dBm (24 W) saturated output power with 9.1 dB linear gain and 34.6% maximum power-added efficiency (PAE) with a drain voltage of 30 V. To our best knowledge, it is the state-of-the-art result ever reported for internal-matched 4.8 mm single chip GaN HEMTs power amplifier at Ku-band.     

A 1 V, 69–73 GHz CMOS power amplifier based on improved Wilkinson power combiner

A 1 V, 69–73 GHz CMOS power amplifier based on improved Wilkinson power combiner is presented. Compared with the traditional one, the proposed Wilkinson power combiner could lower down the insertion loss and reduce the die area by eliminating the quarter-wavelength transmission lines while preserving the characteristics of Wilkinson power combining and good port isolation. The presented power amplifier has been implemented in 65 nm CMOS process and achieves a measured saturated output power of 10.61 dBm and a peak power added efficiency of 8.13% at 73 GHz with only 1 V power supply. The die area including pads is 1.23×0.45 mm², while the power combiner only occupies 200×80 μm².     

Comparative study of low-frequency noise in 0.18 μm and 0.35 μm gate-length nMOSFETs with gate area of 1.1 μm2

We analyzed the noise characteristics of 0.18 μm and 0.35 μm nMOSFETs with a gate area of 1.1 μm² in the frequency range of 1 Hz to 100 kHz. Both two- and four-finger devices were investigated and analyzed. The experimental results show that the noise of 0.35 μm gate-length nMOSFET possesses lower 1/f component than the 0.18 μm one, whereas the four-finger devices reveal less 1/f noise than those of with two-finger ones. Furthermore, we used time domain measurement of drain current and also the statistical analysis of wafer level on the random telegraph signals (RTS) tests, and the results showed that RTS noise is higher in devices with a 0.35 μm gate-length, and devices with a smaller gate finger width produce more RTS noise than devices with a larger gate finger width.     

Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET

Now a days, high-k dielectrics have been investigated as an alternative to Silicon dioxide (SiO₂) based gate dielectric for nanoscale semiconductor devices. This paper is an attempt to characterize the analog and RF performance of the high-k metal gate (HKMG) double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) in nanoscale through 2-D device simulation. The results demonstrates the impact of high-k oxide layer as single and gate stack (GS). The key idea behind this investigation is to provide a physical explanation for the improved analog and RF performance exhibited by the device. The major figures of merit (FOMs) studied in this paper are transconductance (g_m), output conductance (g_d), transconductance generation factor (g_m/I_D), early voltage (V_EA), intrinsic gain (A_V), cut off frequency (f_T), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP). The effects of downscaling of channel length (L) on analog performance of the proposed devices have also been presented. It has been observed that the performance enhancement of GS configurations (k=7.5 i.e device D5 in the study) is encouraging as far as the nanoscale DG-MOSFET is concerned. Also it significantly reduces the short channel effects (SCEs). Parameters like DC gain of (91.257 dB, 43.436 dB), nearly ideal values (39.765 V⁻¹, 39.589 V⁻¹) of TGF, an early voltage of (2.73 V, 16.897 V), cutoff frequency (294 GHz, 515.5 GHz) and GTFP of (5.14×10⁵ GHz/V, 1.72×10⁵ GHz/V) for two different values of V_DS=0.1 V and 0.5 V respectively are found to be close to ideal values. Analysis shows an opportunity for realizing high performance analog and RF circuits with the device proposed in this paper i.e. device D5.     

Common-base multi-finger submicron InGaAs/InP double heterojunction bipolar transistor with fmax of 305 GHz

A layout of a common-base four-finger InGaAs/InP double heterostructure bipolar transistor (DHBT) has been designed and the corresponding DHBT has been fabricated successfully by using planarization technology. The area of each emitter finger was 1 × 15 μm². The breakdown voltage was more than 7 V, the current could be more than 100 mA. The maximum output power can be more than 80 mW derived from the DC characteristics. The maximum oscillation frequency was as high as 305 GHz at I_C = 50 mA and V_CB = 1.5 V. The DHBT is thus promising for the medium power amplifier and voltage controlled oscillator (VCO) applications at W band and higher frequencies.     

The effect of oxide layer thickness on the quantification of 1.5 MeV γ–radiation induced interface traps in the Ag/SiO2/Si MOS devices

This work presents the effect of varied thickness of oxide layer and radiation dose on electrical characteristics of Ag/SiO₂/Si MOS devices irradiated by 1.5 MeV γ–radiations of varied doses. SiO₂ layers of 50, 100, 150 and 200 nm thickness were grown on Si substrates using dry oxidation and exposed to radiation doses of 1, 10 and 100 kGy. The exposure to radiation resulted in generation of fixed charge centers and interface traps in the SiO₂ and at the Si/SiO₂ interface. Capacitance-conductance-voltage (C-G-V) and capacitance-conductance-frequency (C-G-f) measurements were performed at room temperature for all MOS devices to quantify the active traps and their lifetimes. It is shown that accumulation and minimum capacitances decreased as the thickness of SiO₂ layer increased. For the unexposed MOS devices, the flat band voltage V_FB decreased at a rate of −0.12 V/nm, density of active traps increased by 4.5 times and depletion capacitance C_DP, increased by 2.5 times with the increase of oxide layer thickness from 50 to 200 nm. The density of active traps showed strong dependence on the frequency of the applied signal and the thickness of the oxide layer. The MOS device with 200 nm thick oxide layer irradiated with 100 kGy showed density of active interface traps was high at 50 kHz and was 3.6×10¹⁰ eV⁻¹ cm⁻². The relaxation time of the interface traps also increased with the exposure of γ–radiation and reached to 9.8 µs at 32 kHz in 200 nm thick oxide MOS device exposed with a dose of 100 kGy. It was inferred that this was due to formation of continuum energy states within the band gap and activation of these defects depended on the thickness of oxide layer, applied reverse bias and the working frequency. The present study highlighted the role of thickness of oxide layer in radiation hard environments and that only at high frequency, radiation induced traps remain passivated due to long relaxation times.     

Growth temperature dependence of epitaxial Gd2O3 films on Si(1 1 1)

This article reports on the epitaxy of crystalline high κ oxide Gd₂O₃ layers on Si(1 1 1) for CMOS gate application. Epitaxial Gd₂O₃ thin films have been grown by Molecular Beam Epitaxy (MBE) on Si(1 1 1) substrates between 650 and 750 °C. The structural and electrical properties were investigated depending on the growth temperature. The C–V measurements reveal that equivalent oxide thickness (EOT) equals 0.7 nm for the sample deposited at the optimal temperature of 700 °C with a relatively low leakage current of 3.6 × 10^?2 A/cm² at |V_g ? V_FB| = 1 V.     

Epitaxial lateral overgrowth of InP/GaAs (1 0 0) heterostructures by metalorganic chemical vapor deposition

Epitaxial lateral overgrowth (ELOG) was used to grow InP on GaAs(1 0 0) substrates by metalorganic chemical vapor deposition (MOCVD). The selectivity of InP by ELOG is excellent and the regrowth InP epilayers have good morphology without polycrystalline on SiO₂ mask. The [$0\overline{1}1$] directional mask stripes and high V/III ratio are benefit to InP lateral growth. Compared to conventional direct growth, ELOG is effective in reducing the dislocation density, relaxing compressing strain in epilayers. In addition, the full width at half maximum (FWHM) of X-ray diffraction (XRD) ω scans and room temperature (RT) photoluminescence (PL) for a 3 μm thick epilayer by ELOG are 198 arcsec and 44 meV, respectively.