A low voltage SANOS nonvolatile semiconductor memory (NVSM) device

In this paper, we present a new Polysilicon–Aluminum Oxide–Nitride–Oxide–Silicon (SANOS) device structure suitable for future nonvolatile semiconductor memories. Replacing SiO₂ with a high-K material, Al₂O₃ (K_f = 9) as the top blocking layer of the conventional SONOS device increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer with its dielectric constant during write and erase operations. Therefore, this new device can achieve lower programming voltages and faster programming speed than the conventional SONOS device. We have fabricated SANOS capacitors with 2 nm tunnel oxide, 5 nm silicon nitride and 8 nm aluminum oxide and studied the programming speed and charge retention characteristics of the new devices. These new SANOS devices achieve a 2 V reduction in the programming voltages with 2.1 V initial memory window.     

Enhanced charge storage characteristics by ZrO2 nanocrystallites precipitated from amorphous (ZrO2)0.8(SiO2)0.2 charge trapping layer

Charge trapping memory capacitors using (ZrO₂)_0.8(SiO₂)_0.2 film as charge trapping layer and amorphous Al₂O₃ as the tunneling layer and blocking layer were fabricated for nonvolatile semiconductor memory application. The ZrO₂ nanocrystallites with a size of 3–5 nm precipitated from amorphous (ZrO₂)_0.8(SiO₂)_0.2 during rapid thermal annealing at 800 °C can serve as the storage nodes, with which a large hysteresis memory window of 7.5 V at a sweeping gate voltage of 8 V has been achieved. At 150 °C bake temperature, the memory capacitor exhibited an excellent endurance up to 10⁵ write/erase cycles, after which a small charge loss of about 12% was achieved.     

Memory characteristics of Al2O3/La2O3/Al2O3 multi-layer films with various blocking and tunnel oxide thicknesses

In order to investigate charge trap characteristics with various thicknesses of blocking and tunnel oxide for application to non-volatile memory devices, we fabricated 5 and 15 nm Al₂O₃/5 nm La₂O₃/5 nm Al₂O₃ and 15 nm Al₂O₃/5 nm La₂O₃/5, 7.5, and 10 nm Al₂O₃ multi-stack films, respectively. The optimized structure was 15 nm Al₂O₃ blocking oxide/5 nm La₂O₃ trap layer/5 nm Al₂O₃ tunnel oxide film. The maximum memory window of this film of about 1.12 V was observed at 11 V for 10 ms in program mode and at ?13 V for 100 ms in erase mode. At these program/erase conditions, the threshold voltage of the 15 nm Al₂O₃/5 nm La₂O₃/5 nm Al₂O₃ film did not change for up to about 10⁴ cycles. Although the value of the memory window in this structure was not large, it is thought that a memory window of 1.12 V is acceptable in the flash memory devices due to a recently improved sense amplifier.     

Improvement of memory properties for MANOS-type nonvolatile memory devices with high-pressure wet vapor annealing

Effects of high-pressure wet vapor annealing (HPWA) on the memory properties of Metal/Alumina/Nitride/Oxide/Silicon (MANOS)-type flash memory devices are studied. The Oxide/Nitride/Alumina (ONA) stacks were annealed in a high-pressure wet vapor ambient (N₂:D₂O = 10 atm:2 atm) at 250 °C for 5 min. It is found that HPWA can effectively passivate the intrinsic defects of the Al₂O₃ film by oxygen species, leading to the improvement of blocking efficiency. The HPWA significantly improved the electrical and reliability characteristics of ONA stacks, such as leakage current density, saturation level of erase, charge loss rate through the blocking oxide, and memory window after the program and erase cycles. HPWA shows promise for future MANOS-type flash memory devices.     

Performance and reliability of HfAlOx-based interpoly dielectrics for floating-gate Flash memory

This paper discusses the performance and reliability of aggressively scaled HfAlO_x-based interpoly dielectric stacks in combination with high-workfunction metal gates for sub-45 nm non-volatile memory technologies. It is shown that a less than 5 nm EOT IPD stack can provide a large program/erase (P/E) window, while operating at moderate voltages and has very good retention, with an extrapolated 10-year retention window of about 3 V at 150 °C. The impact of the process sequence and metal gate material is discussed. The viability of the material is considered in view of the demands of various Flash memory technologies and direction for further improvements are discussed.     

Polymer composite of poly(vinyl phenol)-reduced graphene oxide reduced by vitamin C in low energy consuming write-once–read-many times memory devices

We report the application of reduced graphene oxide, using vitamin C as reducing agent, to make a composite with poly(vinyl phenol) as the active layer of write-once–read-many times memory devices. These devices present a high ON/OFF current ratio of 10⁵ when read at 1 V, retain the information for a long time maintaining the ON/OFF current ratio constant, and require low energy for performing at 5 V the memory write (less than 10^?8 J cm^?2 device active area) and read operations.     

Multilevel characteristics and operating mechanisms of nonvolatile memory devices based on a floating gate of graphene oxide sheets sandwiched between two polystyrene layers

Nonvolatile organic memory devices were fabricated utilizing a graphene oxide (GO) layer embedded between two polystyrene (PS) layers. Scanning electron microscope images of GO sheets sandwiched between two PS layers showed that the GO sheets were clearly embedded in the PS layers. Capacitance–voltage (C–V) curves of the Al/PS/GO/PS/n-type Si devices clearly showed hysteresis behaviors with multilevel characteristics. The window margin of the nonvolatile memory devices increased from 1 to 7 V with increasing applied sweep voltages from 6 to 32 V. The cycling retention of the ON/OFF switching for the devices was measured by applying voltages between +15 and −15 V. While the capacitance of the memory devices at an ON state have retained as 230 pF up to 10⁴ cycles, that at an OFF state maintained as 16 pF during three times of repeated measurements. The extrapolation of the retention data for the devices maintained up to 10⁶ cycles. The operating mechanisms of the nonvolatile organic memory devices with a floating gate were described by the C–V results and the energy band diagrams.     

Potentiality of trap charge effects and SiON induced interface defects in a-Si3N4/SiON based MIS structure for resistive NVM device

Potential application of amorphous silicon nitride (a-Si₃N₄)/silicon oxy-nitride (SiON) film has been demonstrated as resistive non-volatile memory (NVM) device by studying the Al/Si₃N₄/SiON/p-Si metal–insulator–semiconductor (MIS) structure. The existence of several deep trap states was revealed by the photoluminescence characterizations. The bipolar resistive switching operation of this device was investigated by current–voltage measurements whereas the trap charge effect was studied in detail by hysteresis behavior of frequency dependent capacitance–voltage characteristics. A memory window of 4.6 V was found with the interface trap density being 6.4 × 10¹¹ cm⁻² eV⁻¹. Excellent charge retention characteristics have been observed for the said MIS structure enabling it to be used as a reliable non-volatile resistive memory device.     

Characterization of TiOxNy nanoparticles embedded in HfOxNy as charge trapping nodes for nonvolatile memory device applications

Silicon-oxide–nitride-oxide–silicon devices with nanoparticles (NPs) as charge trapping nodes (CTNs) are important to provide enhanced performance for nonvolatile memory devices. To study these topics, the TiO_xN_y metal oxide NPs embedded in the HfO_xN_y high-k dielectric as CTNs of the nonvolatile memory devices were investigated via the thermal synthesis using Ti thin-film oxidized in the mixed O₂/N₂ ambient. Well-isolated TiO_xN_y NPs with a diameter of 5–20 nm, a surface density of ～3 × 10¹¹ cm^?2, and a charge trap density of around 2.33 × 10¹² cm^?2 were demonstrated. The writing characteristic measurements illustrate that the memory effect is mainly due to the hole trapping.     

Characterization of CoxNiyO hybrid metal oxide nanoparticles as charge trapping nodes in nonvolatile memory devices

The Co_xNi_yO hybrid metal oxide nanoparticles (HMONs) embedded in the HfO_xN_y high-k dielectric as charge trapping nodes of the nonvolatile memory devices have been formed via the chemical vapor deposition using the Co/Ni acetate calcined and reduced in the Ar/NH₃ ambient. A charge trap density of 8.96 × 10¹¹ cm^?2 and a flatband voltage shift of 500 mV were estimated by the appearance of the hysteresis in the capacitance–voltage (C–V) measurements during the ±5 V sweep. Scanning electron microscopy image displays that the Co_xNi_yO HMONs with a diameter of ～10–20 nm and a surface density of ～1 × 10¹⁰ cm^?2 were obtained. The mechanism related to the writing characteristics are mainly resulted from the holes trapping. Compared with those devices with the Co_xNi_yO HMONs formed by the dip-coated technique, memory devices with the Co_xNi_yO HMONs fabricated by the drop-coated technique show improved surface properties between the Co_xNi_yO HMONs and the HfON as well as electrical characteristics.     

Hydrophilic self-assembly monolayers for pentacene-based thin-film transistors

A series of hydrophilic alkanethiols, HS(CH₂)_nOH with n = 3, 4, 6, 8, 9 and 11, have been self-assembled on gold electrodes of pentacene-based thin-film transistors. The multi-parametric and ultra-sensitive response of these devices allows us to characterize both charge–injection and electrical stability moving from vacuum to air. The decay exponent β of charge injection is found to be 0.7–1.1 Å^?1 in agreement with earlier measurements of charge tunneling done by electrochemistry and large-area molecular junctions. We find that the intermediate chain lengths (n = 4 and 6) yield an optimum response as they represent the best compromise in terms of decrease of the contact-resistance and bias stress.     

A new erase method for scaled NAND flash memory device

A suitable bird-beak thickness is crucial to the cell reliability. However, the process control for bird-beak thickness in the edge region is very difficult. A new erase method is proposed in this work to modulate the electron tunneling region of 40 nm floating gate NAND flash memory device. The erasing electron can move to gate center from gate edge under back bias at 0.3 V/− 0.8 V. The Fowler-Nordheim (FN) current of erase operation distributes on the whole channel region, not located at the gate edge region. Results show that the proposed method can improve cell reliability about 33%. TCAD analysis is employed to explain and prove the mechanism. This new erase method is promising for scaled NAND flash memory.     

Use of Al2O3 as inter-poly dielectric in a production proven 130 nm embedded Flash technology

We have successfully integrated 2 Mb arrays with SiO₂/Al₂O₃ stacks as inter-poly dielectric (IPD) fabricated in a proven 130 nm embedded Flash technology. Gate stack write/erase high voltages (HV) can be reduced by 3 V. Write/erase distributions show evidence of bit pinning which can be explained by barrier lowering along Al₂O₃ grain boundaries. Reliability assessment of the 2 Mb array reveals promising data retention and cycle endurance, indicating the absence of charge trapping in the high-k IPD. Despite several integration issues, these results demonstrate the high potential of Al₂O₃ IPDs in embedded Flash technologies.     

Hybrid organic–inorganic materials for molecular proton memory devices

Molecular storage elements consisting of a stack of a proton conducting layer (PCL) and a proton trapping layer (PTL) are investigated in view of their perspective application to non-volatile proton memories. Experimental studies are conducted on PCL and PTL materials made of poly(methyl methacrylate) (PMMA) with embedded molecules of 12-tungstophosphoric acid (HPW) and 2-aminoanthracene (AA), respectively. Particular emphasis is placed on the thermal processing parameters (temperature and duration) used in material preparation and their optimization for circumventing undesirable phenomena, for the device stability and performance, like reactions between HPW and PMMA and inter-mixing of the PCL and PTL. Transient current measurements performed on metal–insulator–semiconductor devices containing an HPW/PMMA layer allowed the determination of both the concentration and mobility of the protons within this layer. Comparison of the extracted proton concentration (ca. 3.8 × 10¹⁷ protons/cm³) under full polarization conditions with the HPW concentration determined by UV spectroscopy indicates that only 2 protons per ～1000 HPW molecules are mobile and contribute to the current. Finally, the material features of a generic PCL/PTL stacked structure affecting the operation of a molecular proton memory device are examined from a theoretical point of view. Results indicate that the write characteristics of this type of memory such as the magnitude of the memory window and the write speed depend on the thickness, the proton mobility and the proton concentration of the PCL, while the write voltage is mainly determined by the thickness of the PTL. In light of these analyses, it appears that memory windows as large as 2.8 V might be obtained for a 1 ms/3 V write operation regime even in the case of PCL and PTL thicknesses as high as 175 nm. These observations suggest that a PTL/PCL storage element may be well suited in future low-cost, low-power, and non-volatile single-organic transistor memory applications.     

Electrical characterization of MFeOS gate stacks for ferroelectric FETs

We investigated the electrical characterization of metal–ferroelectric–oxide semiconductor (MFeOS) structures for nonvolatile memory applications. Al/PZT/Si and Al/PZT/SiO₂/Si capacitors were fabricated using lead zirconate titanate (PZT; 35:65) as the ferroelectric layer. The maximum C–V memory window was 6 V for metal–ferroelectric semiconductor (MFeS) structures and 2.95 and 6.25 V for MFeOS capacitors with a buffer layer of 2.5 and 5 nm, respectively. Comparative data reveal a higher dielectric strength and lower leakage characteristic for an MFeOS structure with a 5-nm SiO₂ buffer layer compared to an MFeS structure. We also observed that the leakage characteristic was influenced by the annealing conditions.     

Carrier transport mechanisms of multilevel nonvolatile memory devices with a floating gate consisting of hybrid organic/inorganic nanocomposites

Nonvolatile memory devices based on a poly(4-vinylphenol) (PVP) layer containing Cu₂ZnSnS₄ (CZTS) nanoparticles were fabricated by using a simple spin-coating method. An energy dispersive spectrum revealed that the CZTS nanoparticles were Cu poor and Zn rich. Transmission electron microscopy images showed that the CZTS nanoparticles were randomly distributed in the PVP layer. Capacitance–voltage (C–V) curves for Al/CZTS nanoparticles embedded in PVP layer/p-Si devices at 1 MHz showed a hysteresis with flat-band voltage (V_fb) shifts, which resulted from the existence of CZTS nanoparticles acting as trap sites in the memory devices. The magnitudes of the V_fb corresponding to the memory window shifts between 1.0 and 2.5 V, as determined from the C–V data at 1 MHz, were dependent on the voltages applied to the memory device, indicative of multilevel characteristics for the memory effect. The operating mechanisms of the writing and the erasing processes for Al/CZTS nanoparticles embedded in PVP layer/p-Si devices are described on the basis of the C–V results and the energy-band diagrams.     

Data retention characteristics of MANOS-type flash memory device with different metal gates at various levels of charge injection

We investigated the impact of charge injection and metal gates (Al and Pt) on the data retention characteristics of metal–alumina–nitride–oxide–silicon (MANOS) devices for NAND flash memory application. Through the theoretical and experimental results, the highly injected charge (ΔV_TH) could cause the band bending of Al₂O₃, which reduced the tunneling distance across Al₂O₃. Thus, the dominant charge loss path is not only toward SiO₂ but also toward Al₂O₃ direction. Compared to low-metal work function (Ф_M), ONA stack with high-Ф_M showed better data retention characteristics, even if ΔV_TH is high. This could be explained by Fermi level alignment for different Ф_M, which results in the reduction of electric field across the Al₂O₃ compensated by the ΔФ_M (Ф_Pt ? Ф_Al).     

Scaling of multidielectric nonvolatile SONOS memory structures

Present-day low-power, portable lap-top computers and consumer products require non-volatile semiconductor memory (NVSM) operating at 5 V with a trend towards reducing this level to 3.3 V. The SONOS technology, an acronym for the polySilicon-blocking Oxide-Nitride-tunnel Oxide-Silicon structure used in capacitors and transistors, shows promise as a technology for present and future low voltage NVSM applications. The nitride layer in the dielectric sandwich permits the storage of charge resulting in adjustable threshold voltages. This paper examines the physics and characterization of scaled SONOS NVSM transistors in relation to reducing the programming voltage. We develop a model for the transient characteristics of the SONOS NVSM transistor with: (1) a simple closed-form solution valid for short programming times; and (2) a numerical solution covering the entire range of programming times. The simple closed-form solution clearly illustrates the dependence of the turn-on time and erase/white slope on the dielectric thicknesses, initial stored charge in the nitride, and programming voltage. In particular, we have examined: (1) decreasing the tunnel oxide thickness; and (2) scaling the blocking oxide thickness. By properly scaling the dielectric films (11 Å tunnel oxide, 50 Å nitride, 40 Å blocking oxide), a ±8 V programmable SONOS device has been obtained with a 50 μs write time and a 100 μs erase time for a 3 V memory window, and a ±5 V programmable device with a 100 ms erase and write time for a 1.5 V memory window.     

Electrical characterization of metal-ferroelectric (Mn-substituted BiFeO3)-insulator (HfO2)-semiconductor capacitors for nonvolatile memory applications

Metal-ferroelectric (Mn-substituted BiFeO₃)-insulator (HfO₂)-semiconductor has been fabricated by co-sputtering technique. X-ray diffraction (XRD) patterns have proven the existence of a substitution phase. The shift in binding energy of Fe ions and the change in atom ratio of Mn to Fe were analyzed by X-ray photoelectron spectra (XPS). The memory windows as functions of insulator film thickness and annealing temperature were compared. The maximum memory window is 3 V at the sweep voltage of 8 V with thicker (60 nm) HfO₂. The leakage current and the charge injection effect can be reduced with increasing the amount of substituting Mn for Fe-site.     

Unipolar nonvolatile memory devices with composites of poly(9-vinylcarbazole) and titanium dioxide nanoparticles

Organic-based devices with an 8 × 8 array structure using titanium dioxide nanoparticles (TiO₂ NPs) embedded in poly(9-vinylcarbazole) (PVK) film exhibited bistable resistance states and a unipolar nonvolatile memory effect. TiO₂ NPs were a key factor for realizing the bistability and the concentration of TiO₂ NPs influenced ON/OFF ratio. From electrical measurements, switching mechanism of PVK:TiO₂ NPs devices was closely associated with filamentary conduction model and it was found that the OFF state was dominated by thermally activated transport while the ON state followed tunneling transport. PVK:TiO₂ NPs memory devices in 8 × 8 array structure showed a uniform cell-to-cell switching, stable switching endurance, and a high retention time longer than 10⁴ s.