Quasi-damascene metal gate/high-k CMOS using oxygenation through gate electrodes

We present a novel metal gate/high-k complementary metal–oxide–semiconductor (CMOS) integration scheme with symmetric and low threshold voltage (V_th) for both n-channel (nMOSFET) and p-channel (pMOSFET) metal–oxide–semiconductor field-effect transistors. The workfunction of pMOSFET is modulated by oxygen in-diffusion (‘oxygenation’) through the titanium nitride metal gate without equivalent oxide thickness (EOT) degradation. A significant V_th improvement by 420 mV and an aggressively scaled capacitance equivalent thickness under channel inversion (T_inv) of 1.3 nm is achieved for the pFET by using a replacement process in conjunction with optimized oxygenation process. Immunity of nMOSFET against oxygenation process is demonstrated.     

HCS degradation of 5 nm oxide high-voltage PLDMOS

Hot carrier (HC) injection, inducing drain and gate leakage current increase in 5 nm oxide p-channel LDMOS transistors, is investigated. Devices with two different drain implants are studied. At low gate voltage (V_GS) and high drain voltage (V_DS), reduction of the ON-resistance (R_ON) is observed. At stress times at which R_ON almost reaches its constant level, an increase of the drain leakage in OFF state (V_DS = −60 V, V_GS = 0 V) is observed. Longer stress time leads to increased gate leakage and in some cases oxide breakdown. In contrast to what was reported for devices with 25 nm gate oxide thickness, the threshold voltage of 5 nm gate oxide PLDMOS transistors does not drift. The experimental data can be fully explained by hot carrier injection and the oxide damage can be explained by two different and competing degradation mechanisms. By combining experimental data and TCAD simulations we are further capable to locate the hot spot of maximum oxide damage in the accumulation (Acc) region of the PLDMOS.     

Gain improvement and microwave operation of 4H–SiC MESFET with a new recessed metal ring structure

A new multi-recessed 4H-SiC MESFET with recessed metal ring for RF embedded circuits is proposed (MR2-MESFET). The key idea in the proposed structure is based on the elimination of the spaces adjacent to gate and stopped the depletion region extending towards drain and source and the reduction of the channel thickness between gate and drain to increase breakdown voltage (V_BR); meanwhile the elimination of the gate depletion layer extension to source/drain to decrease gate-source capacitance (C_gs). The influence of multi-recessed drift region and recessed metal ring structures on the characteristics of the MR2-MESFET is studied by numerical simulation. The optimized results show that the V_BR of the MR2-MESFET is 119% larger than that of the conventional 4H–SiC MESFET (C-MESFET); meanwhile maintain 85% higher saturation drain current. Therefore, the maximum output power density of the MR2-MESFET is 23.1 W/mm compared to 5.5 W/mm of the C-MESFET. Also, the cut-off frequency (f_T) and the maximum oscillation frequency (f_max) of 24.9 and 91.7 GHz are obtained for the MR2-MESFET compared to 11 and 40 GHz of the C-MESFET structure, respectively. The proposed MR2-MESFET shows a maximum stable gain (MSG) exceeding 23.6 dB at 3.1 GHz which is the highest gain yet reported for SiC MESFETs, showing the potential of this device for high power RF applications.     

Drivability improvement in Schottky barrier source/drain MOSFETs with strained-Si channel by Schottky barrier height reduction

Due to an extra barrier between source and channel, the drivability of Schottky barrier source/drain MOSFETs (SBMOSFETs) is smaller than that of conventional transistors. To reach the drivability comparable to the conventional MOSFET, the Schottky barrier height (SBH) should be lower than a critical value. It is expected that SBH can be effectively reduced by a bi-axially strain on Si. In this letter, p-channel MOSFETs with PtSi Schottky barrier source/drain, HfAlO gate dielectric, HfN/TaN metal gate and strained-Si channel are demonstrated for the first time using a simplified low temperature process. Devices with the channel length of 4 μm have the drain current of 9.5 μA/μm and the transconductance of 14 μS/μm at V_gs − V_th = V_ds = −1 V. Compared to the cubic Si counterpart, the drain current and the transconductance are improved up to 2.7 and 3.1 times respectively. The improvement is believed to arising from the reduced barrier height of the PtSi/strained-Si contact and the enhanced hole mobility in the strained-Si channel.     

Source/drain metallization effects on the specific contact resistance of indium tin zinc oxide thin film transistors

We report on the specific contact resistance of interfaces between thin amorphous semiconductor Indium Tin Zinc Oxide (ITZO) channel layers and different source/drain (S/D) electrodes (Al, ITO, and Ni) in amorphous oxide thin film transistors (TFTs) at different channel lengths using a transmission line model. All the contacts showed linear current–voltage characteristics. The effects of different channel lengths (200–800 μm, step 200 μm) and the contact resistance on the performance of TFT devices are discussed in this work. The Al/ITZO TFT samples with the channel length of 200 μm showed metallic behavior with a linear drain current-gate voltage (I_D–V_G) curve due to the formation of a conducting channel layer. The specific contact resistance (ρ_C) at the source or drain contact decreases as the gate voltage is increased from 0 to 10 V. The devices fabricated with Ni S/D electrodes show the best TFT characteristics such as highest field effect mobility (16.09 cm²/V·s), ON/OFF current ratio (3.27×10⁶), lowest sub-threshold slope (0.10 V/dec) and specific contact resistance (8.62 Ω·cm² at V_G=0 V). This is found that the interfacial reaction between Al and a-ITZO semiconducting layer lead to the negative shift of threshold voltage. There is a trend that the specific contact resistance decreases with increasing the work function of S/D electrode. This result can be partially ascribed to better band alignment in the Ni/ITZO interface due to the work function of Ni (5.04–5.35 eV) and ITZO (5.00–6.10 eV) being somewhat similar.     

Degradation of pMOSFETs due to hot electron induced punchthrough

This paper proposes a method which can separate the parasitic effect from the drain current I_d vs. gate voltage V_g curves of MOSFETs, then uses this method to analyze degradation of experimental pMOSFETs due to hot-electron-induced punchthrough (HEIP). An I_d vs. V_g curve of the parasitic MOSFET formed by a shallow trench isolation (STI) is obtained by extrapolating the line of I_d vs. channel width W at each V_g to W = 0 μm. The I_d vs. V_g curves of the parasitic MOSFET indicate that HEIP caused electron trapping at the interface between SiN and the sidewall oxide of STI, but the curves of the main MOSFET indicate that HEIP caused negative oxide charges and positive interface traps in the channel region. These charges and traps decreased the threshold voltage V_th of the parasitic MOSFET but increased V_th of the main MOSFET. These two opposite behaviors of V_th resulted in little HEIP-induced shift of V_th at W = 2.5 μm. | V_d | to secure ten-year HEIP lifetime of 10% shift of V_th was ≤ 2.2 V at W = 0.3 μm, ≤ 3.5 V at W = 1.0 μm, and ≤ 3.6 V at W = 10 μm; these changes indicate that degradation of parasitic MOSFET influences the HEIP lifetime of narrow pMOSFET significantly.     

Reduced contact resistance and highly stable operation in polymer thin-film transistor with aqueous MoOx solution contact treatment

We report on a newly developed solution process using MoO₃ for reducing source and drain (S/D) electrodes in organic thin-film transistor (TFT). By taking advantage of the difference in surface wettability between the gate dielectric layer and the S/D electrodes, the electrode treatment using the MoO_x solution was applied to polymer TFT with short channel lengths less than 10 μm. The contact resistance was noticeably reduced at the interface of the S/D electrodes in a polymer TFT using a pBTTT-C16. Furthermore, the field effect mobility for this TFT was enhanced from 0.03 to 0.1 cm²/V s. Most notably, the threshold voltage (V_th) shift under gated bias stress was less than 0.2 V after 10⁵ s, which is comparable to that of conventional poly crystalline Si TFT.     

Realizing high breakdown voltage for a novel interface charges islands structure based on partial-SOI substrate

A novel interface charge islands partial-SOI (ICI PSOI) high voltage device with a silicon window under the source and its mechanism are studied in this paper. ICI PSOI is characterized by a series of equidistant high concentration n⁺-regions on the bottom interface of top silicon layer. On the condition of high-voltage blocking state, inversion holes located in the spacing of two n⁺-regions effectively enhance the electric field of the buried oxide layer (E_I) and reduce the electric field of the silicon layer (E_S), resulting in a high breakdown voltage (V_B). It is shown by the simulations that the enhanced field ΔE_I and reduced field ΔE_S by the accumulated holes reach to 449 V/μm and 24 V/μm, respectively, which makes V_B of ICI PSOI increase to 663 V from 266 V of the conventional PSOI on 5 μm silicon layer and 1 μm buried oxide layer with the same silicon window length. On-resistance of ICI PSOI is lower than that of the conventional PSOI. Moreover, self-heating-effect is alleviated by the silicon window in comparison with the conventional SOI at the same power of 1 mW/μm.     

Effects of channel thickness variation on bias stress instability of InGaZnO thin-film transistors

Here, we report on the effects of channel (or active) layer thickness on the bias stress instability of InGaZnO (IGZO) thin-film transistors (TFTs). The investigation on variations of TFT characteristics under the electrical bias stress is very crucial for commercial applications. In this work, the initial electrical characteristics of the tested TFTs with different channel layer thicknesses (40, 50, and 60 nm) are performed. Various gate bias (V_GS) stresses (10, 20, and 30 V) are then applied to the tested TFTs. For all V_GS stresses with different channel layer thickness, the experimentally measured threshold voltage shift (ΔV_th) as a function of stress time is precisely modeled with stretched-exponential function. It is indicated that the ΔV_th is generated by carrier trapping but not defect creation. It is also observed that the ΔV_th shows incremental behavior as the channel layer thickness increases. Thus, it is verified that the increase of total trap states (N_T) and free carriers resulted in the increase of ΔV_th as the channel layer thickness increases.     

Investigations on electrical characteristics and reliability properties of MOS capacitors using HfAlOx on n-GaAs substrates

Radio frequency sputtering system is employed to fabricate metal oxide semiconductor (MOS) capacitors using an ultra-thin layer of HfAlO_x dielectric deposited on n-GaAs substrates with and without a Si interface control layer incorporated in between the dielectric and the semiconductor. Measurements are performed to obtain capacitance voltage (C–V) and current voltage (I–V) characteristics for GaAs/Si/HfAlO_x and GaAs/HfAlO_x capacitors under different constant voltage and constant current stress conditions. The variation of different electrical parameters such as change in interface trap density, hysteresis voltage with various values of constant voltage stress and the dependence of flat band voltage, fractional change in gate leakage current density, etc. with stress time are extracted from the C–V and I–V data for capacitors with and without a Si interlayer. Further the trap charge density and the movement of trap centroid are investigated for various injected influences. The dielectric breakdown and reliability properties of the dielectric films are studied using constant voltage stressing. A high time-dependent dielectric breakdown (TDDB, t_bd ? 1350 s) is observed for HfAlO_x gate dielectric with a silicon inter-layer under the high constant voltage stress at 8 V. Compared to capacitors without a Si interlayer, MOS capacitors with a Si interlayer exhibit improved electrical and breakdown characteristics, and excellent interface and reliability properties.     

Self-aligned inversion n-channel In0.2Ga0.8As/GaAs metal–oxide–semiconductor field-effect-transistors with TiN gate and Ga2O3(Gd2O3) dielectric

A self-aligned process for fabricating inversion n-channel metal–oxide–semiconductor field-effect-transistors (MOSFET’s) of strained In_0.2Ga_0.8As on GaAs using TiN as gate metal and Ga₂O₃(Gd₂O₃) as high κ gate dielectric has been developed. A MOSFET with a 4 μm gate length and a 100 μm gate width exhibits a drain current of 1.5 mA/mm at V_g = 4 V and V_d = 2 V, a low gate leakage of <10^?7 A/cm² at 1 MV/cm, an extrinsic transconductance of 1.7 mS/mm at V_g = 3 V, V_d = 2 V, and an on/off ratio of ～10⁵ in drain current. For comparison, a TiN/Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As MOS diode after rapid thermal annealing (RTA) to high temperatures of 750 °C exhibits excellent electrical and structural performances: a low leakage current density of 10^?8–10^?9 A/cm², well-behaved capacitance–voltage (C–V) characteristics giving a high dielectric constant of ～16 and a low interfacial density of state of ～(2～6) × 10¹¹ cm^?2 eV^?1, and an atomically sharp smooth Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As interface.     

Improved reliability of large-sized a-Si thin-film-transistor by back channel treatment in H2

A hydrogen plasma treatment on the back-channel region of large-sized amorphous silicon thin film transistor (a-Si TFT) with high RF power and optimal process time of 20 s is proposed in this work to effectively reduce off current (I_off) and threshold voltage (V_th) shift under high and low electrical-field stresses. The channel width (W) of large-sized a-Si TFT is ranged from 1000 to 10,000 μm, which are comparable to the realistic TFTs used in the gate driver on array (GOA) of display. It is experimentally found that the mechanism of V_th shift (ΔV_th) after high electrical stress is dominated by the defect generation in a-Si layer rather than charge trapping in the gate insulator (GI) layer, which is different from the observation in previous literatures. It could be due to the effects of back-channel treatment (BCT). In addition, after low electrical stresses, the mechanism of ΔV_th is dominated by defect generation in a-Si layer, which is consistent with previous reports.     

Similarities of lag phenomena and current collapse in field-plate AlGaN/GaN HEMTs with different types of buffer layers

We make a two-dimensional transient analysis of field-plate AlGaN/GaN high electron mobility transistors (HEMTs) with a Fe-doped semi-insulating buffer layer, which is modeled that as deep levels, only a deep acceptor located above the midgap is included (E_C − E_DA = 0.5 eV, E_C: energy level at the bottom of conduction band, E_DA: deep acceptor's energy level). And the results are compared with a case having an undoped semi-insulating buffer layer in which a deep donor above the midgap (E_C − E_DD = 0.5 eV. E_DD: the deep donor's energy level) is considered to compensate a deep acceptor below the midgap (E_DA − E_V = 0.6 eV, E_V: energy level at the top of valence band). It is shown that the drain-current responses when the drain voltage is lowered abruptly are reproduced quite similarly between the two cases with different types of buffer layers, although the time region where the slow current transients occur is a little different. The lags and current collapse are reduced by introducing a field plate. This reduction in lags and current collapse occurs because the deep acceptor's electron trapping is reduced under the gate region in the buffer layer. The dependence of drain lag, gate lag and current collapse on the field-plate length and the SiN layer thickness is also studied, indicating that the rates of drain lag, gate lag and current collapse are quantitatively quite similar between the two cases with different types of buffer layers when the deep-acceptor densities are the same.     

Novel organic inverters with dual-gate pentacene thin-film transistor

We report on the fabrication and characterization of dual-gate pentacene organic thin-film transistors (OTFTs) with plasma-enhanced atomic-layer-deposited (PEALD) 150 nm thick Al₂O₃ as a bottom-gate dielectric and PEALD 200 nm thick Al₂O₃ as a top-gate dielectric. The V_th of dual-gate OTFT has changed systematically with the application of voltage bias to top-gate electrode. When voltage bias from −10 V to 10 V is applied to top gate, V_th changes from 1.95 V to −9.8 V. Two novel types of the zero drive load logic inverter with dual-gate structure have been proposed and fabricated using PEALD Al₂O₃ gate dielectrics. Because the variation of V_th due to chemical degradation and the spatial variation of V_th are inherent in OTFTs, the compensation technology by dual-gate structure can be essential to OTFT applications.     

Analysis of slow traps centres in submicron MOSFETs by random telegraph signal technique

In this paper, we present a comprehensive study of slow single traps, situated inside the gate oxide of small area (W×L=0.5×0.1 μm²) metal–oxide–semiconductor (MOS) transistors. The gate oxide of the analyzed transistors, which have been used for memory-cell applications, is composed of two SiO₂ layers—a deposited high-temperature oxide (HTO) and the thermal oxide. The interface between the two gate oxides is shown to play a significant role in the channel conduction: we observed that the presence of individual traps situated inside the gate oxide, at some angstroms from the interface with the channel, is inducing discrete variations in the drain current. Using random telegraph signal (RTS) analysis, for various temperatures and gate bias, we have determined the characteristics of these single traps: the energy position within the silicon bandgap, capture cross section and the position within the gate oxide.     

Effect of Halo structure variations on the threshold voltage of a 22 nm gate length NMOS transistor

This paper reports on the effects of the Halo structure variations on threshold voltage (V_th) in a 22 nm gate length high-k/metal gate planar NMOS transistor. Since the V_th is one of the important physical parameter for determining the functionality of complementary metal-oxide–semiconductor device, this experiment will focus on finding the best combination on process parameter to achieve the best value of V_th. The Halo structure variable process parameters are the Halo implantation dose, the Halo implantation tilting angle, the Source/Drain implantation dose and the compensation implantation dose. The design of the planar device consists of a combination of high permittivity material (high-k) and a metal gate. Titanium dioxide was used as the high-k material instead of the traditional SiO₂ dielectric and tungsten silicide was used as the metal gate. The optimization process was executed using Taguchi's L₉ array to obtain a robust design. Taguchi's Nominal-the-Best signal-to-noise ratio was used in an effort to minimize the variance of V_th. The results show that the V_th values have least variance and the mean value can be adjusted to 0.289 V±12.7% which is in line with projections made by the International Technology Roadmap for Semiconductors.     

High performance organic thin film transistors using chemically modified bottom contacts and dielectric surfaces

A compatible process of orthogonal self-assembled monolayers (SAMs) is applied to intentionally modify the bottom contacts and gate dielectric surfaces of organic thin film transistors (OTFTs). This efficient interface modification is first achieved by 4-fluorothiophenol (4-FTP) SAM to chemically treat the silver source–drain (S/D) contacts while the silicon oxide (SiO₂) dielectric interface is further primed by either hexamethyldisilazane (HMDS) or octyltrichlorosilane (OTS-C8). Results show that the field effect mobilities of the bottom-gate bottom-contact PTDPPTFT4 transistors were significantly improved to 0.91 cm² V⁻¹ s⁻¹.     

To observe bidirectional negative differential resistance at room temperature by narrowing transport channels for charge carriers in vertical organic light-emitting transistor

Bidirectional negative differential resistance (NDR) at room temperature with high peak-to-valley current ratio (PVCR) of ～10 are observed from vertical organic light-emitting transistor indium-tin oxide (ITO)/N,N′-di(naphthalene-1-yl)-N,N′-diphenyl-benzidine) (α-NPD)(60 nm)/Al(30 nm)/α-NPD(60 nm)/tris-(8-hydroxyquinoline) aluminium (Alq₃)(50 nm)/Al by narrowing the transport channels for charge carriers with a thick-enough middle Al gate electrode layer to block charge carriers transporting from source electrode to drain electrode. When the transport channel for charge carriers gets large enough, the controllability of gate bias on the drain–source current gets weaker and the device almost works as an organic light-emitting diode only. Therefore, it provides a very simple way to produce NDR device with dominant bidirectional NDR and high PVCR (～10) at room temperature by narrowing transport channels for charge carriers in optoelectronics.     

An optimization technique for parameter extraction of ultra-deep submicron LDD MOSFET’s

An optimization technique to determine the threshold voltages V_th is proposed for meaningful parameter extractions of ultra-deep submicron LDD MOSFETs. The novel technique, coupled with some traditional V_th determination techniques, are implemented in several existing extraction methods to extract the parasitic series resistance R_ds, the effective channel length L_eff , and the effective mobility μ_eff of ultra-thin gate oxide LDD MOSFETs on 90 nm CMOS technology. A comparison among these extractions demonstrates that the technique of V_th optimization maintains the accuracy of extractions, avoids the intentional choice of the gate voltage range, and eliminates the impact of close interdependence among these parameters on the meaningful extraction, especially at high gate voltage range. Furthermore, the novel technique can reduce the extraction variance of different extraction methods, hence, suitable for application in device compact model.     

Performance of commercial foundry-level AlGaN/GaN HEMTs after hot electron stressing

The performance degradation of commercial foundry level GaN HEMTs placed under a constant-power drain voltage step-stress test has been studied. By utilizing electroluminescence measurement techniques to optimize hot electron stress testing conditions (Meneghini, 2012), no significant permanent changes in saturation current (I_dss), transconductance (Gm), and threshold voltage (V_th) can be seen after stress testing of drain voltages from 30 V up to 200 V. We observe little permanent degradation due to hot electron effects in GaN HEMTs at these extreme operating conditions and it is inferred that other considerations, such as key dimensions in channel or peak electric field (Chynoweth, 1958; Zhang and Singh, 2001) [2,3], are more relevant to physics of failure than drain bias alone.