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1.
InAlN films of different thicknesses (150 nm, 250 nm, 380 nm, 750 nm and 1050 nm) were grown on Si (111) by means of reactive co-sputtering at 300 °C. Surface morphology results indicated an increase in the grains size and their spacing with increase of the film thickness. The surface of InAlN remained smooth with a slight variation in its RMS roughness from 1.29 nm to 6.62 nm by varying the film thickness. X-ray diffraction patterns exhibited InAlN diffraction peaks with preferred orientation along (002) plane in the thickness range 250 nm to 750 nm, however, the preferred orientation of the film was changed towards (101) plane at 1050 nm. An improvement in the crystallinity of InAlN was observed with increase of the film thickness. Electrical characterization revealed a decrease in the film's resistivity by increasing its thickness to 750 nm, however, the resistivity was found to increase at 1050 nm. The electron concentration indicated an increasing trend whereas changes in the electron mobility were found to be inconsistent with increase of the film thickness.  相似文献   

2.
The manufacturing of state-of-the-art electronic devices involves an increasing demand for the accurate determination of ultra-shallow electrical carrier profiles related to the need to monitor the activation of the dopants with reduced thermal budgets. For sub-micron structures (down to 100 nm) a qualified conventional spreading resistance probe system is an attractive tool for the reliable measurement of the resistivity (and carrier) depth variations in silicon due to its high geometrical resolution (nm) and high dynamic range (nine orders of magnitude). The spreading resistance (SR) roadmap for future process development (sub-50 nm profiles), however, shows that there is a need for a significant reduction of the involved contact size and tip separation, a higher depth resolution (sub-nm) and an improved quantification. The recently introduced scanning spreading resistance microscopy technique resolves some of the involved issues such as the smaller contact size (20–50 nm) and the higher geometrical depth resolution (sub-nm) when applied on a bevelled surface. Further developments are, however, needed in the fields of tip configuration, surface preparation and contact modelling to achieve timely all the needs of the SR roadmap. This is expected to lead to a new instrument, the NanoProfiler™, using two small (20–50 nm contact size), closely spaced (250 nm), conductive tips mounted on an atomic force microscope-based system. The NanoProfilerTM setup can easily achieve Angstrom depth resolution and therefore makes the profiling of sub-10 nm structures feasible.  相似文献   

3.
MOS capacitors with 7 nm SiO2 dielectrics and n-doped Si substrate were irradiated by 1.8 MeV protons with fluences ranging from 1012 to 5 × 1013 cm?2 which correspond to the typical LHC fluence range. No significant increase in gate oxide leakage current was detected. A decrease of the capacitance was observed in the accumulation regime. This effect is explained by an increase of the substrate resistivity caused by displacement damage.  相似文献   

4.
Copper indium sulfide (CISu) films were deposited by the pulse galvanostatic deposition technique at different duty cycles. The films are polycrystalline with peaks corresponding to the chalcopyrite phase of CISu. The grain size and surface roughness increased from 10 to 25 nm and 0.85 to 2.50 nm respectively with increase of duty cycle. Optical band gap in the range of 1.30–1.51 eV was observed for the films deposited at different duty cycles. Room temperature resistivity of the films is in the range of 0.1–3.67 Ω cm. Photoconductivity measurements were made at room temperature. Photocurrent spectra exhibited maximum corresponding to the band gap of copper indium sulphide. CdS/CuInS2 fabricated with CISu films deposited at 50% duty cycle have exhibited a Voc of 0.62 V, Jsc of 16.30 mA cm?2, FF of 0.71 and efficiency of 7.16%.  相似文献   

5.
Copper Indium Telluride films were deposited for the first time by the pulse electrodeposition technique at different duty cycles in the range of 6–50% at room temperature and at a constant potential of −0.66 V(SCE). The films exhibited single phase copper indium telluride. The grain size increased with increase of duty cycle. Optical band gap of the films varied in the range of 0.98–1.02 eV. Atomic force microscopy studies indicated that the grain size and surface roughness vary from 15 nm to 30 nm and 1.0 nm to 1.5 nm, respectively with increase of duty cycle. Capacitance voltage measurements indicated the films to exhibit n-type behavior. The flat band potential was −0.76 V(SCE) and carrier density was in the range of 1016 cm−3.  相似文献   

6.
Silver telluride thin films of thickness 50 nm have been deposited at different deposition rates on glass substrates at room temperature and at a pressure of 2×10−5 mbar. The electrical resistivity was measured in the temperature range 300–430 K. The temperature dependence of the electrical resistance of Ag2Te thin films shows structural phase transition and coexistence of low temperature monoclinic phase and high temperature cubic phase. The effect of deposition rate on the phase transition and the electrical resistivity of silver telluride thin films in relation to carrier concentration and mobility are discussed.  相似文献   

7.
We have investigated the contact resistivity of GeCu2Te3 (GCT) phase change material to a W electrode using the circular transfer length method (CTLM). The contact resistivity ρc of as-deposited amorphous GCT to W was 3.9×10−2 Ω cm2. The value of ρc drastically decreased upon crystallization and crystalline GCT that annealed at 300 °C showed a ρc of 4.8×10−6 Ω cm2. The ρc contrast between amorphous (as-deposited) and crystalline (annealed at 300 °C) states was larger in GCT than in conventional Ge2Sb2Te5 (GST). Consequently, it was suggested from a calculation based on a simple vertical structure memory cell model that a GCT memory cell shows a four times larger resistance contrast than a GST memory cell.  相似文献   

8.
We have deposited very low resistant Co films on SiO2-coated Si substrates using UV pulsed laser pyrolytic decomposition of Co2(CO)8 with 355 nm laser radiation at atmospheric pressure. Facile decomposition of the precursors and the use of Ar curtain enable the deposition of relatively pure Co (with O less than 7% and negligible C) at the power of 1.11–3.33 W, and of pure Co at 6.67 W. The resistivity decreases from 58 to 19 µΩ-cm as the power increases from 2.22 to 3.33 W, showing inverse-linear dependence on grain size. In addition, further increase of the power to 6.67 W decreases the resistivity to 9 µΩ-cm, due to both the growth of large grains with negligible contaminants, and the adverse effect of surface roughness. The effects of oxygen contaminants on the resistivity can be minimal, because of its presence in the form of oxide. These low resistant fine metal lines deposited by a direct-writing laser chemical vapor deposition technique at atmospheric pressure have been reported for the first time.  相似文献   

9.
《Microelectronic Engineering》2007,84(5-8):1096-1099
The behaviour of a new epoxy based resist (mr-EBL 6000.1 XP) as a negative resist for e-beam lithography is presented. We demonstrate that it is possible to define sub-100 nm patterns when irradiating thin (120 nm) layers of resist with a 10 keV electron beam. The dependence of resolution and remaining thickness on electron dose, electron energy and photo acid generator (PAG) content is determined. After the electron beam lithography process, the resist is used as a mask for reactive ion etching. It presents a good etch resistance, that allows transfer of patterns to the substrate with resolution below 100 nm.  相似文献   

10.
The next generation packaging materials are expected to possess high heat dissipation capability. Understanding the needs for betterment in the field of thermal management, the present study aims at investigating the package level analysis on a high power LED. In this study, commercially available thermal paste was heavily filled with ceramic particles of aluminium nitride (AlN) and boron nitride (BN) in order to enhance the heat dissipation of the device. Different particle sizes of AlN and BN fillers were incorporated homogenously into the thermal paste and applied as a thermal interface material (TIM) for an effective system level analysis employing thermal transient measurement. It was found that AlN TIM achieve less LED junction temperature by a difference of 2.20 °C compared to BN filled TIM. Furthermore, among D50 = 1170 nm, 813 nm and 758 nm, the AlN at D50 = 1170 nm was found to exhibit the lowest junction temperature of 38.49 °C and the lowest total thermal resistance of 11.33 K/W compared to the other two fillers.  相似文献   

11.
Copper indium sulpho selenide films of different composition were deposited by the pulse plating technique at 50% duty cycle (15 s ON and 15 s OFF). X-ray diffraction studies indicated the formation of single phase chalcopyrite copper indium sulpho selenide films. Transmission Electron Microscope studies indicated that the grain size increased from 10 nm–40 nm as the selenium content increased. The band gap of the films was in the range of 0.95 eV–1.44 eV. Room temperature resistivity of the films is in the range of 16.0 Ω cm–33.0 Ω cm. Films of different composition used in photoelectrochemical cells have exhibited photo output. Films of composition, CuInS0.9Se0.1 have exhibited maximum output, a VOC of 0.74 V, JSC of 18.50 mA cm?2, ff of 0.75 and efficiency of 11.40% for 60 mW cm?2 illumination.  相似文献   

12.
The barrier properties and failure mechanism of sputtered Hf, HfN and multilayered HfN/HfN thin films were studied for the application as a Cu diffusion barrier in metallization schemes. The barrier capability and thermal stability of Hf, HfN and HfN/HfN films were determined using X-ray diffraction (XRD), leakage current density, sheet resistance (Rs) and cross-sectional transmission electron microscopy (XTEM). The thin multi-amorphous-like HfN thin film (10 nm) possesses the best barrier capability than Hf (50 nm) and amorphous-like HfN (50 nm). Nitrogen incorporated Hf films possess better barrier performance than sputtered Hf films. The Cu/Hf/n+–p junction diodes with the Hf barrier of 50 nm thickness were able to sustain a 30-min thermal annealing at temperature up to 500 °C. Copper silicide forms after annealing. The Hf barrier fails due to the reaction of Cu and the Hf barrier, in which Cu atoms penetrate into the Si substrate after annealing at high temperature. The thermal stabilities of Cu/Hf/n+–p junction diodes are enhanced by nitrogen incorporation. Nitrogen incorporated Hf (HfN, 50 nm) diffusion barriers retained the integrity of junction diodes up to 550 °C with lower leakage current densities. Multilayered amorphous-like HfN (10 nm) barriers also retained the integrity of junction diodes up to 550 °C even if the thickness is thin. No copper–hafnium and copper silicide compounds are found. Nitrogen incorporated hafnium diffusion barrier can suppress the formation of copper–hafnium compounds and copper penetration, and thus improve the thermal stability of barrier layer. Diffusion resistance of nitrogen-incorporated Hf barrier is more effective. In all characterization techniques, nitrogen in the film, inducing the microstructure variation appears to play an important role in thermal stability and resistance against Cu diffusion. Amorphousization effects of nitrogen variation are believed to be capable of lengthening grain structures to alleviate Cu diffusion effectively. In addition, a thin multilayered amorphous-like HfN film not only has lengthening grain structures to alleviate Cu diffusion, but block and discontinue fast diffusion paths as well. Hence, a thin multilayered amorphous-like HfN/HfN barrier shows the excellent barrier property to suppress the formation of high resistance η′-(Cu,Si) compound phase to 700 °C.  相似文献   

13.
《Organic Electronics》2014,15(8):1836-1842
A copper oxide (CuO) nanoparticle ink was inkjet printed and photosintered in order to optimize electrical performance as a function of pattern dimension. For a given photosintering condition, electrical conductance varied strongly with line widths, ranging from 100 to 300 μm, illustrating the implications of printing and sintering complex circuit designs with varying feature sizes. By tuning the time delay between printing and sintering, exposure wavelength, radiant energy, pulse width and the distance between the light-source and substrate, photosintering conditions were optimized so that variations in sheet resistance for different line widths were minimized. Using optimized photosintering conditions, a sheet resistance value as low as 150 mΩ/□ (resistivity of 9 μΩ cm) and current carrying capacity of 280 mA for a 300 μm wide trace was achieved.  相似文献   

14.
《Microelectronic Engineering》2007,84(5-8):793-796
This paper demonstrates significant improvements in the stitching performance of an electron beam lithography tool by correcting for wafer tilt. This is achieved with no significant increase in writing time. Wafer tilt gives rise to keystone errors in the writing field and even for modest tilts the stitching error can increase significantly. By applying suitable corrections to the main field the maximum stitching error was reduced from 34 to 12 nm for a wafer tilt of 2 mrad.  相似文献   

15.
As an emerging material, graphene has attracted vast interest in solid-state physics, materials science, nanoelectronics and bioscience. Graphene has zero bandgap with its valence and conduction bands are cone-shaped and meet at the K points of the Brillouin zone. Due to its high intrinsic carrier mobility, large saturation velocity, and high on state current density, graphene is also considered as a promising candidate for high-frequency devices. To improve the reliability of graphene FETs, which include shifting the Dirac point voltage toward zero, increasing the channel mobility and decreasing the source/drain contact resistance, we optimized the device fabrication process. For CVD grown graphene, the film transfer and the device fabrication processes may produce interfacial states between graphene and the substrate and make graphene p or n-type, which shift the fermi level far away from the Dirac point. We have found that after graphene film transfer, an annealing process at 400 °C under N2 ambient will shift Dirac point toward zero gate voltage. Ti/Au, Ni, and Ti/Pd/Au source/drain structures have been studied to minimize the contact resistance. According to the measured data, Ti/Pd/Au structure gives the lowest contact resistance (~500 ohm μm). By controlling the process of graphene growth, transfer and device fabrication, we have achieved graphene FETs with a field effective mobility of 16,000 cm2/V s after subtraction of contact resistance. The contact resistivity was estimated in the range of 1.1 × 10?6 Ω cm2 to 8.8 × 10?6 Ω cm2, which is close to state of the art III–V technology. The maximum transconductance was found to be 280 mS/mm at VD = 0.5 V, which is the highest value among CVD graphene FETs published to date.  相似文献   

16.
This study focusses on the investigation of RF power variations (100–300 W) effects on structural, morphological and optical properties of CaCu3Ti4O12 thin film deposited on ITO/glass substrate in a non-reactive atmosphere (Ar). The increase of RF power from 100 W to 300 W led to evolution of (112), (022), (033), and (224) of CCTO XRD peaks. The results indicated that all the films were polycrystalline nature with cubic structure. The crystallite size increased from 20 nm to 25 nm with increasing RF power. FESEM revealed that the films deposited were uniform, porous with granular form, while the grain size increased from 30 to 50 nm. AFM analysis confirmed the increment in surface roughness from 1.6 to 2.3 nm with increasing film grain size. Besides, optical transmittance values decreased to minimum 70% with increasing RF power while optical energy bandgap increased from 3.20 eV to 3.44 eV. Therefore, favorable CCTO thin film properties can be possibly obtained for certain application by controlling RF magnetron sputtering power.  相似文献   

17.
We have investigated Ag(200 nm)/AgAl(100 nm) ohmic contacts to p-type GaN for near-UV (405 nm) flip-chip light-emitting diodes (LEDs). It is shown that the use of an AgAl alloy capping layer (with 8 at% Al) results in better electrical and optical properties as compared to single Ag contacts when annealed at 430 °C. For example, Ag/AgAl (8 at% Al) contacts give specific contact resistance of 4.6×10–4 Ω cm2 and reflectance of 90% at a wavelength of 405 nm. However, use of an AgAl (with 50 at% Al) layer is not effective. LEDs fabricated with the Ag/AgAl (8 at% Al) reflectors produce higher light output as compared with the ones with single Ag reflectors. Ohmic mechanisms of the Ag/AgAl (8 at% Al) contacts are described and discussed.  相似文献   

18.
The effect of varying sintering temperature in the range 1270–1430 °C on the resistivity–temperature characteristics of semiconducting BaTiO3 based positive temperature coefficient of resistance thermistors containing a donor-dopant, but without acceptor doping, was investigated by impedance spectroscopy. As the sintering temperature was increased the specimen resistivity around the Curie temperature decreased, while the peak resistivity, obtained above the Curie temperature, remained approximately constant. The change in PTC behaviour with increasing sintering temperature is inconsistent with the standard double Schottky barrier model, but is explained in terms of grain size variations coupled with a, sintering temperature independent, grain boundary barrier layer thickness of 0.50±0.04 μm.  相似文献   

19.
Several scanning probe microscopy (SPM) modes exist for the electrical characterization of semiconductor materials and devices with nm-scale resolution. The most important electrical SPM modes are: scanning capacitance microscopy (SCM), scanning spreading resistance microscopy (SSRM), and tunneling-AFM (TUNA). SCM and SSRM are primarily used for 2-D carrier profiling and resistivity mapping on cross-sectioned devices. The spatial resolution is on the order of 20 nm, while the dynamic range goes from 1015 to 1020 atoms/cm3. Imaging examples are shown for sub-quarter micron MOSFETs, ferro-electric material, and compound semiconductor structures. The TUNA method allows one to perform thickness mapping and defect imaging of thin dielectric films using a tunneling current flowing between the SPM tip and the sample. Spatial resolution is on the nm-scale, while the current range is from 50 fA to 120 pA. Examples are shown of gate oxide breakdown and defect localization in thin gate oxides.  相似文献   

20.
Phase Change Memory (PCM) operation relies on the reversible transition between two stable states (amorphous and crystalline) of a chalcogenide material, mainly of composition Ge2Sb2Te5 (GST). In Wall type PCM cells, cycling endurance induces a gradual change of the cell electrical parameters caused by variations in the chemical composition of the active volume. The region closer to the GST-heater contact area, becomes more Sb rich and Ge depleted. The new alloy has usually different thermal characteristics for the phase transitions that influence the electrical behavior of the cell. In this study we analyze the morphological, structural and electrical properties of two Sb-rich non-stoichiometric alloys: Ge14Sb35Te51 and Ge14Sb49Te37, at their amorphous and crystalline phase. Experiments have been performed in non-patterned blanket films and, to simulate the device size, in amorphous regions of 20 nm, 50 nm and 100 nm diameter respectively. The amorphous Ge14Sb35Te51 film crystallizes in the meta-stable face centered cubic structure at 150 °C and in the rhombohedral phase at 175 °C, behavior characteristic of the Ge1Sb2Te4 composition. The average grain size is of about 100 nm after an annealing at 400 °C. The Ge14Sb49Te37 film crystallizes only in the hexagonal phase, with an average grain size of about 60 nm after annealing at 400 °C. The X-ray fluorescence analysis shows a non uniform distribution of the constituent atoms and in particular a Ge signal decrement and a Sb enrichment at grain boundaries. The in situ annealing of amorphous nano-areas (RESET state under a thermal stress) indicates a fast re-crystallization speed for Ge14Sb35Te51, 80 pm/s at 90 °C, and a lower speed for Ge14Sb49Te37, at 130 °C a grain growth velocity of 50 pm/s has been measured. The different behavior of the two alloys is discussed in terms of structural vacancies filling by the Sb atoms in excess and by their segregation at grain boundaries. The influence of the obtained results on the device characteristics is discussed.  相似文献   

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