Comparative study of low-frequency noise in 0.18 μm and 0.35 μm gate-length nMOSFETs with gate area of 1.1 μm2

We analyzed the noise characteristics of 0.18 μm and 0.35 μm nMOSFETs with a gate area of 1.1 μm² in the frequency range of 1 Hz to 100 kHz. Both two- and four-finger devices were investigated and analyzed. The experimental results show that the noise of 0.35 μm gate-length nMOSFET possesses lower 1/f component than the 0.18 μm one, whereas the four-finger devices reveal less 1/f noise than those of with two-finger ones. Furthermore, we used time domain measurement of drain current and also the statistical analysis of wafer level on the random telegraph signals (RTS) tests, and the results showed that RTS noise is higher in devices with a 0.35 μm gate-length, and devices with a smaller gate finger width produce more RTS noise than devices with a larger gate finger width.     

STI-to-gate distance effects on flicker noise characteristics in 0.13 μm CMOS

The geometry effect on the flicker noise characteristics and the variations in 0.13 μm CMOS transistors were studied. By symmetrically extending the distance between the shallow-trench-isolation (STI) to the gate, both NMOS and PMOS presented obvious improvement on the noise characteristics. As the distance increased from 0.6 μm to 10 μm, the average noise level reduced by more than one order of magnitude (NMOS) and the standard deviations σ_dB improved from 5.95 dB to 1.79 dB for NMOS and from 3.93 dB to 2.17 dB for PMOS, respectively. To further identify the noise mechanism, the devices with asymmetrical STI-to-gate distances were also investigated. It was found that the distance in the source side (SA) has a much higher impact on the observed noise characteristics. The results suggested that the noise characteristics were dominated by the STI stress induced traps for both NMOS and PMOS studied here. In addition, the carrier number fluctuation model with the correlated mobility scattering could be more suitable to describe the noise characteristics in these devices.     

Silicon-on-insulator power integrated circuits

A power integrated circuit process has been developed, based on silicon-on-insulator, which allows intelligent CMOS control circuitry to be placed alongside integrated high-voltage power devices. A breakdown voltage of 335 V has been obtained by using a silicon layer of 4 μm thickness together with a buried oxide layer of 3 μm thickness. The respective LDMOS specific on-resistance and LIGBT on-state voltage for this breakdown voltage were 148 mΩ cm² and 3.9 V, respectively.     

Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K

The linearity of triple gate nanowire transistors (NWs) implemented on a Silicon-On-Insulator (SOI) substrate is investigated in this work considering temperature (T) influence. The analysis is performed in long channel nanowire MOSFETs with different fin width (W_FIN), from quasi-planar structures (W_FIN = 10 μm) to narrow devices (9.5 nm), operating as single-transistor amplifiers from room temperature down to 100 K. The total, second and third order harmonic distortions (THD, HD2 and HD3, respectively) are extracted using the Integral Function Method (IFM). The analysis is divided in two parts. First, a fixed input signal is applied at the gate of the single-transistor amplifiers and, then, the output signal is fixed. Transport parameters such as effective mobility (μ_eff), mobility degradation coefficient (θ) and series resistance (R_S) have been extracted down to 100 K and correlated to the distortion to explain linearity peaks behavior with temperature and fin width. Narrow transistors have shown improved linearity mainly due to higher intrinsic voltage gain (A_V) considering the entire temperature range. Low temperature operation has shown to degrade the linearity characteristics of both wide and narrow NW MOSFETs.     

Long-wave (10 μm) infrared light emitting diode device performance

Electroluminescence in the range of 6–12 μm is observed from an Sb-based type-II interband quantum cascade structure. The LED structure has 30 active/injection periods. We have studied both top-emitting and flip-chip mount bottom emitting LED devices. For room temperature operation, an increase, saturation and decrease in light output occur at successively higher injection currents. An increase of about 10 times in light output occurs when device is operated at 77 K compared to room temperature operation. This increase is attributed to reduced Auger non-radiative recombination at lower temperatures. The peak-emission wavelengths at room temperature and 80 K operation are 7 and 10 μm, respectively. These devices can be used for high-temperature simulation in an infrared scene generation experiment.     

Responsivity and lifetime of resonant-cavity-enhanced HgCdTe detectors

Resonant-cavity-enhanced HgCdTe structures have been grown by molecular beam epitaxy, and photoconductors have been modelled and fabricated based on these structures. Responsivity has been measured and shows a peak responsivity of 8 × 10⁴ V/W for a 50 × 50 μm² photoconductor at a temperature of 200 K. The measured responsivity shows some agreement with the modelled responsivity across the mid-wave infrared window (3–5 μm). The measured responsivity is limited by surface recombination, which limits the effective lifetime to ≈15 ns. The optical cut-off of the detector varies with temperature as modelled from 5.1 μm at 80 K to 4.4 μm at 250 K. There is strong agreement between modelled peak responsivity and measured peak responsivity with varying temperature from 80 to 300 K.     

Study of the breakdown failure mechanisms for power AlGaN/GaN HEMTs implemented using a RF compatible process

The breakdown failure mechanisms for a family of power AlGaN/GaN HEMTs were studied. These devices were fabricated using a commercially available MMIC/RF technology with a semi-insulating SiC substrate. After a 10 min thermal annealing at 425 K, the transistors were subjected to temperature dependent electrical characteristics measurement. Breakdown degradation with a negative temperature coefficient of ?0.113 V/K for the devices without field plate was found. The breakdown voltage is also found to be a decreasing function of the gate length. Gate current increases simultaneously with the drain current during the drain-voltage stress test. This suggests that the probability of a direct leakage current path from gate to the 2-DEG region. The leakage current is attributed by a combination of native and generated traps/defects dominated gate tunneling, and hot electrons injected from the gate to channel. Devices with field plate show an improvement in breakdown voltage from ～40 V (with no field plate) to 138 V and with lower negative temperature coefficient. A temperature coefficient of ?0.065 V/K was observed for devices with a field plate length of 1.6 μm.     

Positive bias temperature instabilities on sub-nanometer EOT FinFETs

PBTI degradation on FinFETs with HfO₂/TiN gate stack (EOT < 1 nm) is studied. Thinner TiN layer decreases interfacial oxide thickness, and reduces PBTI lifetime. This behavior is consistent with the results in planar devices. Corner rounding effect on PBTI is also analyzed. Finally, charge pumping measurements on devices with several fin widths devices apparently show a higher density of defects in the top-wall high-κ oxide than in the sidewall of the fin. This could explain more severe PBTI degradation.     

Microwave effects of UV light exposure of a GaN HEMT: Measurements and model extraction

This paper presents an experimental investigation on the microwave performance of a GaN HEMT subject to UV light exposure. The device, having 0.25 μm gate length and 100 μm gate width, has been characterized by measuring its DC performance, linear scattering parameters, noise parameters in the 2–26 GHz frequency range, either in dark condition and under CW light exposure at 375 nm. Clear variations of the GaN HEMT performance related to the charge generation and the relevant threshold voltage shift within the semiconductor layers are recognizable in the reported results. The scattering parameters and the noise parameters are affected in a similar way as it occurs in GaAs HEMT's under optical irradiation in the visible range. A circuit model extraction has then been performed to analyze more deeply the effects of the UV exposure. The observed changes of the noise parameters might be ascribed to the effects of the increased gate conduction under illumination and have been efficiently modeled by an additional resistor between the internal gate and source terminals with an assigned noise temperature of 3053 °C.     

Microwave performance of field-plate 0.13-μm MOS transistors with varying field-plate extension

Si-based field-plate 0.13 μm gate length metal-oxide-semiconductor field effect transistor (Si MOSFET) with field-plate (FP) lengths of 0.1 μm, 0.2 μm, and 0.3 μm have been fabricated and investigated. The field-plate metals were connected to gate electrode in this study to improve device gate resistance (R_g) resulting in the better microwave performance. By increasing the length of field-plate metal extension (L_FPE), the off-state drain-to-source surface leakage current can be suppressed. Besides, low surface traps in FP NMOS also leads to a higher drain-to-source current (I_ds) especially at high current regime compared to standard device. The power added efficiency (PAE) was 56.3% for L_FPE of 0.3 μm device, and these values where 54.7% and 53.8% for L_FPE of 0.2 μm and 0.1 μm devices, respectively. Wider field-plate metal extension exhibits highly potential for low noise amplifier and high efficiency power amplifier applications.     

MEMS based low cost piezoresistive microcantilever force sensor and sensor module

In the present work, we report fabrication and characterization of a low-cost MEMS based piezoresistive micro-force sensor with SU-8 tip using laboratory made silicon-on-insulator (SOI) substrate. To prepare SOI wafer, silicon film (0.8 µm thick) was deposited on an oxidized silicon wafer using RF magnetron sputtering technique. The films were deposited in argon (Ar) ambient without external substrate heating. The material characteristics of the sputtered deposited silicon film and silicon film annealed at different temperatures (400–1050 °C) were studied using atomic force microscopy (AFM) and X-ray diffraction (XRD) techniques. The residual stress of the films was measured as a function of annealing temperature. The stress of the as-deposited films was observed to be compressive and annealing the film above 1050 °C resulted in a tensile stress. The stress of the film decreased gradually with increase in annealing temperature. The fabricated cantilevers were 130 μm in length, 40 μm wide and 1.0 μm thick. A series of force–displacement curves were obtained using fabricated microcantilever with commercial AFM setup and the data were analyzed to get the spring constant and the sensitivity of the fabricated microcantilever. The measured spring constant and sensitivity of the sensor was 0.1488 N/m and 2.7 mV/N. The microcantilever force sensor was integrated with an electronic module that detects the change in resistance of the sensor with respect to the applied force and displays it on the computer screen.     

Channel height dependent protein nucleation and crystal growth in microfluidic devices

We report on results of a study of protein crystallization in microfluidic devices with different channel heights. Multilayer soft lithography has been used for the fabrication of devices with integrated micro-valves and crystallization channels of height in the range from 15 μm to 180 μm. To demonstrate the channel height dependent nucleation and crystal growth, a standard batch crystallization solution composed of 60 mg/ml lysozyme, 100 mM acetate buffer pH 4.6 and 1.5 M NaCl was used with minimized sample quantity. Our results show that deep channels favorite the nucleation whereas shallow ones favorite the crystal growth. When the channel height is less than 50 μm the number of lysozyme crystals is dramatically reduced whereas their mean size is increased. Furthermore, our results also show the feasibility of decoupling nucleation and crystal growth in a stair-like channel which should facilitate the appearance of single crystals suitable for X-ray diffraction.     

Spin-coated PMMA films

Polymethylmethacrylate (PMMA) spin-coated thin films are commonly used as resist films in micro/nanofabrication processes. By using atomic force microscopy (AFM) imaging, scratching lithography and force–distance curves spectroscopy, the spin coating and post-processing conditions were determined, for obtaining films whose surface morphology appears featureless or is dominated by pinholes and other surface defects. Featureless appear the surfaces of films spin coated at 8 krpm from a 1.25% solution on silicon substrates and postbaked at 200 °C for 2 min on a hot plate, while surface defects in the form of large circular pits with diameters between 10 and 20 μm and depth of ∼2 nm dominate the surface morphologies of films spin coated at 7 krpm on glass substrates from a 2% solution and postbaked either at 200 °C for 2 min on a hot plate or at 170 °C for 30 min in an oven. Surface defects in the form of pinholes appear on the surfaces of films spin coated at 8 krpm on silicon substrates from a 1.25% solution (thickness of ∼8 nm) and postbaked at 170 °C for 60 min in an oven or left in a low vacuum chamber for a few days. The implication of the different film properties—depending on the preparation parameters—in lithographic techniques is explained and discussed in the paper.     

Defect-controlled synthesis of graphene based nano-size electronic devices using in situ thermal treatment

Defect-controllable reduction approach of graphene is demonstrated. By in situ thermal reduction from graphene oxide on silicon wafer (300 nm SiO₂), large size (∼15 μm) of single and few-layer graphene with highly improved electrical properties has been prepared. The effects of increasing annealing temperature on reducing the defect, restoring the lattice and enhancing the field-effect performance of graphene are proved. The characteristics of the sample were analyzed using optical microscope (OM), atomic force microscope (AFM), X-ray photoelectron spectra (XPS), Raman laser, semiconductor parameter analyzer and a micromanipulator. The devices based on the obtained few-layer graphene exhibit relatively high p-type transistor characteristics (6.2 cm²/V s) in the atmospheric environment.     

Enhancement in electrical performance of indium gallium zinc oxide-based thin film transistors by low temperature thermal annealing

We have studied the characteristics of transparent bottom-gate thin film transistors (TFTs) using In–Ga–Zn–O (IGZO) as an active channel material. IGZO films were deposited on SiO₂/Si substrates by DC sputtering techniques. Thereafter, the bottom-gate TFT devices were fabricated by depositing Ti/Au metal pads on IGZO films, where the channel length and width were defined to be 200 and 1000 μm, respectively. Post-metallization thermal annealing of the devices was carried out at 260, 280 and 300 °C in nitrogen ambient for 1 h. The devices annealed at 280 °C have shown better characteristics with enhanced field-effect mobility and high on–off current ratio. The compositional variation of IGZO films was also observed with different annealing temperatures.     

Realizing high breakdown voltage for a novel interface charges islands structure based on partial-SOI substrate

A novel interface charge islands partial-SOI (ICI PSOI) high voltage device with a silicon window under the source and its mechanism are studied in this paper. ICI PSOI is characterized by a series of equidistant high concentration n⁺-regions on the bottom interface of top silicon layer. On the condition of high-voltage blocking state, inversion holes located in the spacing of two n⁺-regions effectively enhance the electric field of the buried oxide layer (E_I) and reduce the electric field of the silicon layer (E_S), resulting in a high breakdown voltage (V_B). It is shown by the simulations that the enhanced field ΔE_I and reduced field ΔE_S by the accumulated holes reach to 449 V/μm and 24 V/μm, respectively, which makes V_B of ICI PSOI increase to 663 V from 266 V of the conventional PSOI on 5 μm silicon layer and 1 μm buried oxide layer with the same silicon window length. On-resistance of ICI PSOI is lower than that of the conventional PSOI. Moreover, self-heating-effect is alleviated by the silicon window in comparison with the conventional SOI at the same power of 1 mW/μm.     

Direct imprint of Al foil for metallization of high-aspect ratio Al lines in nano/micro patterned SiO2/Si

Patterning techniques of Al micro/nano-structures become more and more critical as optical components and microelectronic devices continue to be scaled down. In this work, we fabricated gap-filled Al lines in SiO₂/Si masters by using the direct thermal imprint of molten Al. As a result, gap-filled Al lines with width ranging from 0.25 to 20 μm and depth ranging from 6 to 127 μm could be achieved without any further processing step such as CVD and PVD. The process studied here has shown the possibility to extend trench filling capability to 0.25 μm structures with 24:1 aspect ratio, which are difficult to be obtained by other conventional Al metallization methods.     

High-mobility tetrathiafulvalene organic field-effect transistors from solution processing

We report on mobilities up to 3.6 cm²/V s in organic field-effect transistors (OFETs) with solution-processed dithiophene- and dibenzo-tetrathiafulvalene (DT- and DB-TTF) single crystals as active materials. In the devices, the channel length varies from 100 μm down to sub 100 nm, and the SiO₂ thickness is either 100 nm, 50 nm, or 20 nm. The devices exhibit excellent operation characteristics with an on/off-ratio exceeding 10⁶. Temperature dependent measurements between 50 and 400 K reveal a thermally activated transport with increased activation above 200 K. The mobility exhibits exponential activation with two distinct exponents.     

New insight on negative bias temperature instability degradation with drain bias of 28 nm High-K Metal Gate p-MOSFET devices

The degradation of negative bias temperature instability (NBTI) on 28 nm High-K Metal Gate (HKMG) p-MOSFET devices under non-uniform stress condition has been systematically studied. We found the asymmetry between forward and reverse Idsat shift under non-uniform stress condition is significant for long channel devices even under low drain bias stress (e.g., Vds = −0.1 V and gate channel length L = 1 μm), and seems to be dominated by a minimally required critical length (L = 0.2 μm derived from the experimental data). To the authors’ best knowledge, these are new phenomena reported. We attribute these anomalous NBTI characteristics with drain bias to the local self-heating (LSH) activated NBTI degradation mechanism. One semi-empirical analytical model, which fits well with our experimental data, is then proposed in this paper.     

Invited paper: Short pulse generation in mid-IR fiber lasers

Mode-locked fiber lasers emitting short pulses of light at wavelengths of 2 μm and longer are reviewed. Rare-earth doped silica and fluoride fiber lasers operating in the mode-locked regime in the mid-IR (2–5 μm) have attracted attention due to their usefulness to spectroscopy, nonlinear optics, laser surgery, remote sensing and ranging to name a few. While silica fiber lasers are fundamentally limited to emission wavelengths below 2.2 μm, fluoride fiber lasers can reach to nearly 4 μm. The relative infancy of fluoride fibers as compared to silica fibers means the field has work to do to translate the mode-locking techniques to systems beyond 2 μm. However, with the recent demonstration of a stable, mode-locked 3 μm fiber laser, the possibility of achieving high performance 3 μm class mode-locked fiber lasers looks promising.