ALD of LaHfOx nano-laminates for high-κ gate dielectric applications

Electrical properties and thermal stability of LaHfO_x nano-laminate films deposited on Si substrates by atomic layer deposition (ALD) have been investigated for future high-κ gate dielectric applications. A novel La precursor, tris(N,N′-diisopropylformamidinato) lanthanum [La(ⁱPrfAMD)₃], was employed in conjunction with conventional tetrakis-(ethylmethyl)amido Hf (TEMA Hf) and water (H₂O). The capacitance-voltage curves of the metal oxide semiconductor capacitors (MOSCAPs) showed negligible hysteresis and frequency dispersion, indicating minimal deterioration of the interface and bulk properties. A systematic shift in the flat-band voltage (V_fb) was observed with respect to the change in structure of nano-laminate stacks as well as La₂O₃ to HfO₂ content in the films. The EOTs obtained were in the range of ∼1.23-1.5 nm with leakage current densities of ∼1.3 × 10⁻⁸ A/cm² to 1.3 × 10⁻⁵ A/cm² at V_fb − 1 V. In addition, the films with a higher content of La₂O₃ remained amorphous up to 950 °C indicating very good thermal stability, whereas the HfO₂ rich films crystallized at lower temperatures.     

Tuning the dipole at the High-κ/SiO2 interface in advanced metal gate stacks

Combining two different electrical characterisation methods on the same MOS capacitors, we demonstrate that the flat band voltage of High-κ metal gate stack is determined by a dipole at the High-κ/SiO₂ interface. Meanwhile, roll-off of flat band voltage, occurring for thin SiO₂ inter layer, is also associated to a dipole variation at this same interface. We have measured its value and we show that this dipole is highly influenced by the High-κ material in contact with the SiO₂. Moreover, we also demonstrate its strong dependence on the process conditions. Finally, for a same metal gate and depending on the High-κ in contact with SiO₂, we show that this dipole can induce up to 1.7 eV variation in the gate effective work function. However, controlling the dipole magnitude remains a strong issue especially for the thinnest EOT.     

Improved electrical characteristics and reliability of amorphous InGaZnO metal-insulator-semiconductor capacitor with high κ HfOxNy gate dielectric

High κ HfO_xN_y film was deposited on amorphous InGaZnO (a-IGZO) by radio-frequency reactive sputtering using an HfO₂ target in nitrogen plus argon ambience, the electrical characteristics and reliability of a-IGZO metal-insulator-semiconductor (MIS) capacitors were investigated. Experimental results indicate that the nitrogen incorporation into HfO₂ can produce a strong nitride interfacial barrier layer, thus lead to reducing the interface state density, suppressing the hysteresis voltage, and decreasing the gate-leakage current. Improved performance has been achieved for HfO_xN_y gate dielectric a-IGZO MIS capacitors, with a interface state density of 5.1 × 10¹¹ eV⁻¹ cm⁻², a gate-leakage current density of 3.9 × 10⁻⁵ A/cm² at V_fb + 1 V, an equivalent permittivity of 24, and a hysteresis voltage of 105 mV. Moreover, the enhanced reliability of Al/HfO_xN_y/a-IGZO MIS capacitor is observed with a small degradation of electrical characteristics after a high field stressing at 10 MV/cm for 3600 s.     

Electrical characteristics and TDDB breakdown mechanism of N2-RTA-treated Hf-based high-κ gate dielectrics

This study investigates the effects of rapid thermal annealing (RTA) in nitrogen ambient on HfO₂ and HfSiO_x gate dielectrics, including their electrical characteristics, film properties, TDDB reliability and breakdown mechanism. The optimal temperature for N₂ RTA treatment is also investigated. The positive oxide trap charges (oxygen vacancies) in HfO₂ and HfSiO_x dielectric films can be reduced by the thermal annealing, but as the annealing temperature increased, many positive oxide trap charges (oxygen vacancies) with shallow or deep trap energy level will be formed in the grain boundaries, degrading the electrical characteristics, and changing the breakdown mechanism. We believe that variation in the number of positive oxide trap charges (oxygen vacancies) with shallow or deep trap energy levels is the main cause of the CV shift and difference in the breakdown behaviors between HfO₂ and HfSiO_x dielectrics. With respect to CV characteristics and TDDB reliability, the optimal temperature for N₂ RTA treatment is in the range 500-600 °C and 800-900 °C, respectively.     

Preparation of a new gate dielectric material HfTiON film

A new gate dielectric material HfTiON is deposited by reactive co-sputtering of Hf and Ti targets in N2/O2 ambient, followed by annealing in N2 at 600 ℃ and 800 ℃ respectively for 2 min. Capacitance-voltage and gate-leakage properties are characterized and compared for different anneal conditions. The results indicate that the sample annealed at 800 ℃ exhibits lower interface-state and oxide-charge densities, and better device reliability. This is attributed to the fact that the rapid thermal annealing at the higher temperature of 800 ℃ can effectively remove the damage-induced precipitation, forming a hardened dielectric/Si interface with high reliability.     

A novel p-n junction polycrystalline silicon gate MOSFET†

A segmented multiple gate MOSFET utilizing a single level of polysilicon gate layer was fabricated and characterized. Data presented for both p- and n-channel devices in which the polysilicon gate layer is segmented into three separate lateral gates by alternate p- and n-typo doping. It was found that current conduction takes place from the source to the drain by applying appropriate potentials to the end gates oven though the central gate was left floating. The harrier potential of the diodes formed within the polysilicon gate layer was measured together with their threshold voltage which was found to be substantially different under the p- and n-type gates..It is concluded that this difference is only partially duo to the difference in work function of the two types of gates ; the rest is due to a difference in the effective surface state density Qss which was, as expected, always found to be positive. It was also found that for both p- and n-channel devices, the Qss was larger for n⁺ gate in comparison with the pH gate. Transfer characteristics of the device were also measured and modelled satisfactorily by applying the standard MOSFET theory suitably modified to account for the different threshold voltage of the p⁺ and n⁺ polygate. Based on this DC characterization, it is proposed that the device would be suitable for CCD or logic gates in which the single polysilicon gate layer could afford higher packing density and yield.     

Atomistic origin of high-quality “novel SiON gate dielectrics”

We have investigated the effect of the oxygen incorporation into SiN films by the first principles calculations. The calculated results show that the oxygen incorporation tends to generate defect states in SiN band gap by forming dangling bonds and floating bonds of Si. Based on the calculated results, it is also indicated that the high quality SiON film can be fabricated by suppressing the incorporation of O atoms into the SiN film, reproducing the reported experiments.     

Nanosized metal grains induced electrical characteristic fluctuation in 16-nm-gate high-κ/metal gate bulk FinFET devices

In this work, the work function fluctuation (WKF) induced variability in 16-nm-gate bulk N-FinFET is for the first time explored by an experimentally calibrated 3D device simulation. Random nanosized grains of TiN gate are statistically positioned in the gate region to examine the associated carriers’ transport, concurrently capturing “grain number variation” and “grain position fluctuation.” The newly developed localized WKF simulation method enables us to estimate the threshold voltage fluctuation of devices with respect to the aspect ratio (AR = fin height/fin width) which accounts for the random grain’s size, number and position effects simultaneously.     

Interplay of plasma etch, strip and wet clean in patterning La2O3/HfO2-containing high-κ/metal gate stacks

The removal process of the La₂O₃/HfO₂ dielectric and of the residues after metal gate etch are discussed. The challenges are presented and related to the specific physico-chemical properties of La-containing compounds. Solutions based on optimization of plasma etch, strip and wet clean are demonstrated for both an integrated and delayed etch-clean process. Both processes meet the stringent requirements of complete removal of the high-κ layers and metal-containing sidewall residues without inducing silicon recess or undercut.     

Physical analysis of breakdown in high-κ/metal gate stacks using TEM/EELS and STM for reliability enhancement (invited)

In this invited paper, we demonstrate how physical analysis techniques that are commonly used in integrated circuits failure analysis can be applied to detect the failure defects associated with ultrathin gate dielectric wear-out and breakdown in high-κ materials and investigate the associated failure mechanism(s) based on the defect chemistry. The key contributions of this work are perhaps focused on two areas: (1) how to correlate the failure mechanisms in high-κ/metal gate technology during wear-out and breakdown to device processing and materials and (2) how the understanding of these new failure mechanisms can be used in proposing “design for reliability” (DFR) initiatives for complex and expensive future CMOS nanoelectronic technology nodes of 22 nm and 15 nm. Hf-based high-κ materials in conjunction with various gate electrode technologies will be used as main examples while other potential high-κ gate materials such as cerium oxide (CeO₂) will also be demonstrated to further illustrate the concept of DFR.     

320 Gb/s all-optical XOR gate using semiconductor optical amplifier-Mach–Zehnder interferometer and delayed interferometer

Photonic Network Communications - All-optical exclusive OR (XOR) gate with semiconductor optical amplifier (SOA)-Mach–Zehnder interferometer (MZI) and delayed interferometer (DI) is...     

Study of stress-induced leakage current (SILC) in HfO2/Dy2O3 high-κ gate stacks on germanium

In the present work we study reliability issues of Pt/HfO₂/Dy₂O₃/n-Ge MOS structures under various stress conditions. The electrical characteristics of the micro-capacitors are very good probably due to the presence of a rare earth oxide as interfacial layer. It is shown that the injected charge (Q_inj) at high constant voltage stress (CVS) conditions induces stress-induced leakage current (SILC) that obeys a power-law. We also observe a correlation between the trapped oxide charge and SILC, which is, at low stress field, charge build-up and no SILC, while at high stress field SILC but few trapped charges. Results show that the present bilayer oxides combination can lead to Ge based MOS devices that show acceptable degradation of electrical properties of MOS structures and improved reliability characteristics.     

Technology innovations and process integrations for sub-100nm gate patterning

I.　Introduction Several　new　factors　are　rendering　gate　pattern－ing　increasingly　challenging　as　the　industry　movestoward　the　sub－100nm　technology　node.　These　areextremely　tight　CD　control　requirements　(e.g.，　＜　3nm3σ　within　wafer　and　＜　2nm　wafer　to　wafer　for　90nmnode)，　complications　induced　by　193nm　resist，　anultra－thin　gate　dielectric　layer　(approximately10－15A， οand　multiple　film　stacks　involving　different　etchchemistries　over　…     

Bias optimization of 2.4 GHz double gate MOSFET RF mixer

The optimum biasing points and structural design parameters for novel nano-scale double gate MOSFET (DG-MOSFET) radio frequency mixers are investigated at 2.4 GHz. Our objective is to analyze and identify the correlation of the conversion gain of the mixer circuit with the signal amplitude of the local oscillator (LO) as well as different device parameters, such as the gate length (L _gate ), doping concentration (N _A ) and body thickness (t _Si ), thus minimizing signal loss and power consumption and increasing stability. The most important figure of merit is found to be the LO DC bias that determines the level of non-linearity in the transconductance response. Furthermore, we observe that in properly designed DG-MOSFETs $(\hbox{L}_{gate} \ge 3t_{Si}),\; \hbox{L}_{gate}$ and N _A have limited impact on the conversion gain of the mixer, while t _Si has a more significant role to play. Although the mixing performance of DG-MOSFETs is ultimately limited by the short channel effects perpetrated by any given structural constraint, an optimum body thickness t _Si exists in each case to maximize the conversion gain. Thus, we illustrate how 2D and quantum-corrected simulations can identify the optimum body thickness and optimum bias conditions in such compact nano-scale mixers.     

Technology innovations and process integrations for sub-100nm gate patterning

This paper presents a brief overview of the Applied Centura(R)DPS(R)system,configured with silicon etch DPS Ⅱ chamber, with emphasis on discussing tuning capability for CD uniformity control. It also presents the studies of etch process chemistry and film integration impact for an overall successful gate patterning development. Discussions will focus on resolutions to key issues, such as CD uniformity, line-edge roughness, and multilayer film etching integration.     

Critical current–gate voltage characteristics in short- and long-gated Josephson junctions

We studied the gate controllability of the critical current and the normal resistance in superconductor–semiconductor–superconductor junctions. The junctions used a two-dimensional electron gas (2DEG) in the InAs-inserted InAlAs/InGaAs heterostructure. It is shown that the interface barrier between the superconductor and the 2DEG affects the controllability in a short-gated junction. In a split-gated junction, the critical current–normal resistance product is almost constant against gate voltage. This is due to quantization of both the critical current and the conductance in a narrow and short semiconductor channel. The long-gated junction in the quasi-ballistic transport regime shows rapid suppression of the critical current by gate voltage.