Improved independent gate N-type FinFET fabrication and characterization

N-type independent gate FinFETs (IGFinFETs) have been fabricated and characterized. Previous published results for this structure highlighted processing deficiencies. Several process enhancements have improved device results beyond those previously reported. These process improvements are presented, and the resulting device is demonstrated. Device results for 2 micron channel length devices are shown. Six decades of drain current suppression and low gate leakage currents are achieved. Subthreshold slope of 200 mV/dec and a threshold voltage tuning range of 1.7 V are demonstrated. This device combines the behavioral characteristics of independent-double-gate MOSFETs with the processing advantages and integration of FinFETs.     

Improved self-gain in deep submicrometer strained silicon-germanium pMOSFETs with HfSiOx/TiSiN gate stacks

The self-gain of surface channel compressively strained SiGe pMOSFETs with HfSiO_x/TiSiN gate stacks is investigated for a range of gate lengths down to 55 nm. There is 125% and 700% enhancement in the self-gain of SiGe pMOSFETs compared with the Si control at 100 nm and 55 nm lithographic gate lengths, respectively. This improvement in the self-gain of the SiGe devices is due to 80% hole mobility enhancement compared with the Si control and improved electrostatic integrity in the SiGe devices due to less boron diffusion into the channel. At 55 nm gate length, the SiGe pMOSFETs show 50% less drain induced barrier lowering compared with the Si control devices. Electrical measurements show that the SiGe devices have larger effective channel lengths. It is shown that the enhancement in the self-gain of the SiGe devices compared with the Si control increases as the gate length is reduced thereby making SiGe pMOSFETs with HfSiO_x/TiSiN gate stacks an excellent candidate for analog/mixed-signal applications.     

Influence of the sidewall crystal orientation, HfSiO nitridation and TiN metal gate thickness on n-MuGFETs under analog operation

This work characterizes the analog performance of SOI n-MuGFETs with HfSiO gate dielectric and TiN metal gate with respect to the influence of the high-k post-nitridation, TiN thickness and device rotation. A thinner TiN metal gate is found favorable for improved analog characteristics showing an increase in intrinsic voltage gain. The devices where the high-k material is subjected to a nitridation step indicated a degradation of the Early voltage (V_EA) values which resulted in a lower voltage gain. The 45° rotated devices have a smaller V_EA than the standard ones when a HfSiO dielectric is used. However, the higher transconductance of these devices, due to the increased mobility in the (1 0 0) sidewall orientation, compensates this V_EA degradation of the voltage gain, keeping it nearly equal to the voltage gain values of the standard devices.     

High mobility strained Si0.5Ge0.5/SSOI short channel field effect transistors with TiN/GdScO3 gate stack

Short channel p-type metal-oxide-semiconductor field effect transistors (MOSFETs) with GdScO₃ gate dielectric were fabricated on a quantum well strained Si/strained Si_0.5Ge_0.5/strained Si heterostructure on insulator. Amorphous GdScO₃ layers with a dielectric constant of 24 show small hysteresis and low density of interface states. All devices show good performance with a threshold voltage of 0.585 V, commonly used for the present technology nodes, and high I_on/I_off current ratios. We confirm experimentally the theoretical predictions that the drive current and the transconductance of the biaxially strained (1 0 0) devices are weakly dependent on the channel orientation. The transistor’s hole mobility, extracted using split C-V method on long channel devices, indicates an enhancement of 90% (compared to SiO₂/SOI transistors) at low effective field, with a peak value of 265 cm²/V s. The enhancement is however, only 40% at high electrical fields. We demonstrate that the combination of GdScO₃ dielectric and strained SiGe layer is a promising solution for gate-first high mobility short channel p-MOSFETs.     

New opportunities for SiGe and Ge channel p-FETs

A thin body (fully depleted) strained SGOI device structure (FDSGOI), and a strained SiGe channel layer on SOI, were fabricated using scaled high-κ gate dielectrics and metal gate technology. The uniaxial strain effect and corresponding drive current enhancement reported by Irisawa et al. [1] for narrow-width devices was investigated on these structures. Although the strained FDSGOI device structure exhibited reduced off-state leakage compared to thicker body devices, and long-channel drive current enhancement under uniaxial strain, the loss of drive current enhancement at short channel length led to uncompetitive I_ON-I_OFF characteristics. The SiGe on SOI structure showed the highest long-channel drive current enhancement (nearly 3×) in the narrowest devices, and also showed a significant reduction in off-state current. This trend was maintained down to the shortest channel lengths studied here and resulted in I_ON-I_OFF characteristics that were competitive with contemporary uniaxial strained Si channel devices.     

An analytic method to compute the stress dependence on the dimensions and its influence in the characteristics of triple gate devices

Triple-gate devices are considered a promising solution for sub-20 nm era. Strain engineering has also been recognized as an alternative due to the increase in the carriers mobility it propitiates. The simulation of strained devices has the major drawback of the stress non-uniformity, which cannot be easily considered in a device TCAD simulation without the coupled process simulation that is time consuming and cumbersome task. However, it is mandatory to have accurate device simulation, with good correlation with experimental results of strained devices, allowing for in-depth physical insight as well as prediction on the stress impact on the device electrical characteristics. This work proposes the use of an analytic function, based on the literature, to describe accurately the strain dependence on both channel length and fin width in order to simulate adequately strained triple-gate devices. The maximum transconductance and the threshold voltage are used as the key parameters to compare simulated and experimental data. The results show the agreement of the proposed analytic function with the experimental results. Also, an analysis on the threshold voltage variation is carried out, showing that the stress affects the dependence of the threshold voltage on the temperature.     

Harmonic distortion of 2-MOS structures for MOSFET-C filters implemented with n-type unstrained and strained FINFETS

This work investigates the harmonic distortion (HD) in 2-MOS balanced structures composed of triple gate FinFETs. HD has been evaluated through the determination of the third-order harmonic distortion (HD3), since this represents the major non-linearity source in balanced structures. The 2-MOS structures with devices of different channel lengths (L) and fin widths (W_fin) have been studied operating in the linear region as tunable resistors. The analysis was performed as a function of the gate voltage, aiming to verify the correlation between operation bias and HD3. The physical origins of the non-linearities have been investigated and are pointed out. Being a resistive circuit, the 2-MOS structure is generally projected for a targeted on-resistance, which has also been evaluated in terms of HD3. The impact of the application of biaxial strain has been studied for FinFETs of different dimensions. It has been noted that HD3 reduces with the increase of the gate bias for all the devices and this reduction is more pronounced both in narrower and in longer devices. Also, the presence of strain slightly diminishes the non-linearity at a similar bias. However, a drawback associated with the use of strain engineering consists in a significant reduction of the on-resistance with respect to unstrained devices.     

Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic

Double gate FinFETs are shown to be better candidates for subthreshold logic design than equivalent bulk devices. However it is not so clear which configuration of DG FinFETs will be more optimal for subthreshold logic. In this paper, we compare the different device and circuit level performance metrics of DG FinFETs with symmetric, asymmetric, tied and independent gate options for subthreshold logic. We observe that energy delay product (EDP) shows a better subthreshold performance metric than power delay product (PDP) and it is observed that the tied gate symmetric option has ≈78% lower EDP value than that of independent gate option for subthreshold logic. The asymmetry in back gate oxide thickness adds to further reduction in EDP for tied gate and has no significant effect on independent gate option. The robustness (measured in terms of % variation in device/circuit performance metrics for a ±10% variation in design parameters) of DG FinFETs with various options has also been investigated in presence of different design parameter variations such as silicon body thickness, channel length, threshold voltage, supply voltage and temperature, etc. Independent gate option has been seen to be more robust (≈40% less) than that of tied gate option for subthreshold logic. Comparison of logic families for subthreshold regime with DG FinFET options shows that for tied gate option, sub-CMOS, sub-Domino and sub-DCVSL have almost similar and better energy consumption and robustness characteristics with respect to PVT variations than other families.     

High-performance GaAs MESFETs with advanced LDD structure fordigital, analog, and microwave applications

GaAs MESFETs with advanced LDD structure have been developed by using a single resist-layered dummy gate (SRD) process. The advanced LDD structure suppresses the short channel effects, and reduces source resistance, while maintaining a moderate breakdown voltage. The 0.3-μm enhancement-mode devices exhibit a transconductance of 420 mS/mm, while the breakdown voltage of the depletion-mode device (V_th=-500 mV) is larger than 6 V. The standard deviation of the threshold voltage for 0.3-μm devices is less than 30 mV across a 3-in wafer. The 0.3-μm devices exhibit an average cutoff frequency of 47.2 GHz with a standard deviation of 1.3 GHz across a 3-in wafer. The cutoff frequency of a 0.15-μm device is as high as 72 GHz. D-type flip-flop circuits for digital IC applications and preamplifier for analog IC applications fabricated with 0.3-μm gate length devices operate above 10 Gb/s. In addition, the 0.3-μm devices also show good noise performance with a noise figure of 1.1 dB with associated gain of 6.5 dB at 18 GHz. These results demonstrate that GaAs MESFETs with an advanced LDD structure are quite suitable for digital, analog, microwave, and hybrid IC applications     

Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation

In this paper, the influence of proton irradiation is experimentally studied in triple-gate Bulk FinFETs with and without Dynamic Threshold MOS configuration (DTMOS). The drain current, transconductance, Drain Induced Barrier Lowering (DIBL) and the important figures of merit for the analog performance such as transconductance-over-drain current, output conductance and intrinsic voltage gain will be compared. Furthermore, the Low-Frequency (LF) noise will be also analyzed in the DT mode and the standard biasing configuration. The results indicate that the better electrical characteristics and analog performance of DTMOS FinFETs make them very competitive candidates for low-noise RF analog applications in a radiation environment.     

VMOS—A new MOS integrated circuit technology

A new V-groove MOS integrated circuit technology (VMOS) is described. It makes use of preferential etching of silicon to define the channels of the MOS transistors. The fabrication involves either a three or four mask process and is capable of producing either silicon gate or standard metal gate transistors. The technology results in very short channel length devices using non-critical alignment tolerances. Despite the short channel length, the VMOS transistor exhibits lower output conductance and higher breakdown voltage than a standard MOS transistor.A first order theory is presented for the VMOS transistor along with measurements made on test devices of various channel lengths. Some integrated circuit applications of the technology are also presented, including an R-S fiip-flop and a 27-stage bucket brigade shift register. The advantages of the VMOS technology in such applications are discussed.     

Temperature dependences of threshold voltage and drain-induced barrier lowering in 60 nm gate length MOS transistors

The temperature dependence of threshold voltage (V_T) and drain-induced barrier lowering (DIBL) characteristics for MOS transistors fabricated with three different threshold voltage technologies are studied. We found that the technique employed to adjust the V_T value make the devices to be not well-scaled for short-channel effects for ultra-short devices at low temperatures. For devices with a short gate length (L<90 nm) and being fabricated using the low threshold voltage (low-V_T) technology, both the temperature dependencies of threshold voltage and DIBL are different to the standard-V_T and high-V_T ones. Abnormally large values of DIBL were found for low V_T-devices because of the significant encroachment of drain depletion region on the channel region. On the other hand, the high substrate doping in high-V_T process makes the devices to have a larger junction depth than that used in the standard process. It causes a poorer DIBL for short-channel devices. Hence the best scaling or design of the devices at room temperature does not imply that they should also be good at low temperatures, especially for L = 60 nm fabricated using the low-V_T process. Different device design and process optimization are required for devices to be operated at temperatures beyond the nominal range.     

Improved analog hot-carrier immunity for CMOS mixed-signalapplications with LATID technology

This paper reports the results of an investigation of hot-carrier effects on analog performance in LATID (Large-Angle-Tilt-Implanted-Drain) and conventional LDD submicron CMOS technology. The investigation focuses on hot-carrier induced degradation of voltage gain, degradation of drain output resistance, and drift of offset voltage of differential pairs. Results illustrate that LATID technology significantly out-performs LDD technology in regard to hot-carrier immunity of key analog parameters in short channel length devices as well as in relatively long channel length devices. The improvement of analog hot-carrier immunity with LATID is attributed to the mechanisms of reduction and departure of high electrical field from the drain area. Results suggest that LATID technology is a promising candidate for mixed-signal ULSI applications     

Analysis of leakage reduction technique on FinFET based 7T and 8T SRAM cells

We propose a FinFET based 7T and 8T Static Random Access Memory (SRAM) cells. FinFETs also promise to improve challenging performance versus power tradeoffs. Designers can run the transistors more rapidly and use the similar amount of power, compared to the planar CMOS, or run them at the similar performance using less power. The aim of this paper is to reduce the leakage current and leakage power of FinFET based SRAM cells using Self-controllable Voltage Level (SVL) circuit Techniques in 45nm Technology. SVL circuit allows supply voltage for a maximum DC voltage to be applied on active load or can reduce the supplied DC voltage to a load in standby mode. This SVL circuit can reduce standby leakage power of SRAM cell with minimum problem in terms of chip area and speed. High leakage currents in submicron regimes are primary contributors to total power dissipation of bulk CMOS circuits as the threshold voltage V _th, channel length L and gate oxide thickness t _ox are scaled down. The leakage current in the SRAM cell increases due to reduction in channel length of the MOSFET. Two methods are used; one method in which the supply voltage is reduced and other method in which the ground potential is increased. The Proposed FinFET based 7T and 8T SRAM cells have been designed using Cadence Virtuoso Tool, all the simulation results has been generated by Cadence SPECTRE simulator at 45nm technology.     

应变SiGe沟道PMOSFET阈值电压模型

首先建立了应变SiGe沟道PMOSFET的一维阈值电压模型,在此基础上,通过考虑沟道横向电场的影响,将其扩展到适用于短沟道的准二维阈值电压模型,与二维数值模拟结果呈现出好的符合。利用此模型,模拟分析了各结构参数对器件阈值电压的影响,并简要讨论了无Sicap层器件的阈值电压。     

基于SiGe虚拟衬底的低场迁移率提升140%的应变Si沟道NMOS器件 Cui Wei(崔伟)1,2,Tang Zhaohuan(唐昭焕)2, Tan Kaizhou(谭开洲)2, Zhang Jing(张静)2,

本文研究了一种应变SiGe沟道的NMOS器件,通过调整硅帽层、SiGe缓冲层,沟道掺杂和Ge组分变化,并采用变能量硼注入形成P阱的方式,成功完成了应变NMOS器件的制作。测试结果表明应变的NMOS器件在低场(Vgs=3.5V, Vds=0.5V)条件下,迁移率极值提升了140%,而PMOS器件性能保持不变。文中对硅基应变增强机理进行了分析。并利用此NMOS器件研制了一款CMOS倒向器,倒向器特性良好, 没有漏电,高低电平转换正常。     

Thermal stress probing the channel-length modulation effect of nano n-type FinFETs

The 3D FinFETs deed provide the impressive gate controllability, especially in drive speed of transistors. However, this advantage relatively brings some drawbacks in channel length modulation (CLM) causing the difficulty in device model establishment. In this work, besides the study of n-type FinFETs in CLM effect, the previous study in 2D HK/MG nMOSFETs at room temperature is also referred and discussed with 3D FinFETs. The influence to the CLM effect at low gate bias is more apparent, speculating the quality of surface channel contributing the depletion width near drain site. The depletion width is usually influenced by raised temperature. And the CLM effect is gradually moved from the low-field dominated to the mid-field as the temperature increased at short-channel device no matter what the V_T implant energy is, but not suitable to the others.     

Fabrication and analysis of deep submicron strained-Si n-MOSFET's

Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si_0.8Ge_0.2 heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 μm) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects     

Gate-edge charges related effects and performance degradation in advanced multiple-gate MOSFETs

This paper analyzes the influence of negative charges (NC) located at the gate edges on the advanced MOSFETs behavior, paying particular attention to the subthreshold slope, S, maximum transconductance, G_mmax, and analog figures of merit, such as transconductance over drain current ratio, G_m/I_D, output conductance, G_D, Early voltage, V_EA, and intrinsic gain. General trends obtained by two-dimensional numerical simulations on double-gate (DG) structures are whenever possible qualitatively correlated with experimental data obtained on FinFETs. We show that the presence of negative charges at the gate edges while degrading the subthreshold behavior and analog figures of merit (especially for long-channel devices) can result in apparent improved control of short-channel effects and higher G_mmax. The origin of such twofold impact of negative charges at the gate edges on the device behavior is also analyzed by 2-D device simulations and a simplified two-transistors model.     

一种新型高性能FinFET的设计与特性分析

针对CMOS器件随着技术节点的不断减小而产生的短沟道效应和漏电流较大等问题,设计了一种新型直肠形鳍式场效应晶体管(FinFET),并将该新型器件与传统的矩形结构和梯形结构的FinFET通过Sentaurus TCAD仿真软件进行对比。结果表明,当栅极长度控制在10 nm时,新型器件相比于另外两种传统的FinFET具有更小的鳍片尺寸,且鳍片高度不低于抑制短沟道效应的临界值。仿真结果显示,这种新型的FinFET具有更好的开关特性和亚阈值特性。同时,该器件在射频方面的特性参数也显示出该器件具有较高性能,并有一定的实际应用价值。