Optimization and validation of thermal management for a RF front-end SiP based on rigid-flex substrate

This paper mainly presents a new 3D stacking RF System-in-Package (SiP) structure based on rigid-flex substrate for a micro base station, with 33 active chips integrated in a small package of 5cm × 5.5cm × 0.8cm. Total power consumption adds up to 20.1 Watt. To address thermal management and testability difficulties of this RF SiP, a thermal test package is designed with the same package structure and assembly flow, only replacing active chips with thermal test dies (TTDs). Optimization and validation of thermal management for the thermal test package is conducted. Effects of the structure, chip power distribution, and ambient temperature aspects on the thermal performance are studied. Thermal vias designed in the organic substrate provide a direct heat dissipation path from TTDs to the top heatsink, which minimizes junction temperature gap of the top substrate from 31.2 °C to 5.3 °C, and enables junction temperatures of all the chips on the face to face structure to be well below 82 °C. Chip power distribution optimization indicates placing high power RF parts on the top rigid substrate is a reasonable choice. The ambient temperature optimizes with forced air convection and cold-plate cooling method, both of which are effective methods to improve thermal performances especially for this micro base station application where environment temperature may reach more than 75 °C. The thermal management validation is performed with a thermal test vehicle. Junction temperatures are compared between finite-volume-method (FVM) simulation and thermal measurement under the natural convection condition. The accordance of simulation and measurement validates this thermal test method. Junction temperatures of typical RF chips are all below 80 °C, which shows the effectiveness of thermal management of this RF SiP.     

A 1.58 nW power consumption and 34.45 ppm/°C temperature coefficient bandgap reference (BGR) for subblocks of RFID tag

In this paper a bandgap reference (BGR) circuit irrespective of the temperature and the supply voltage variation with very low power consumption is proposed. The proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) generators of the proposed BGR, which has four cores cascaded with each other, are used in order to increase not only the output voltage, but also the output control ability for the temperature and the voltage insensitivity. To combine produced voltage from PTAT and CTAT generator, a weight combination circuit, which uses internal capacitors of transistors, is applied. Due to the fact that all of the transistors in such a topology are worked in sub-threshold region, the power consumption is significantly diminished to 1.58 nW. Also the variation of the temperature from −25 °C to 150 °C, leads to the temperature coefficient about 34.45 ppm/°C. The design simulation is done at 960 MHz frequency in TSMC 0.18 µm CMOS technology with the help of Cadence software. Also the post layout simulation result and the layout of the proposed circuit are presented. The output and the chip area of this BGR are 141.5 mV and 1387 µm² respectively.     

Microwave effects of UV light exposure of a GaN HEMT: Measurements and model extraction

This paper presents an experimental investigation on the microwave performance of a GaN HEMT subject to UV light exposure. The device, having 0.25 μm gate length and 100 μm gate width, has been characterized by measuring its DC performance, linear scattering parameters, noise parameters in the 2–26 GHz frequency range, either in dark condition and under CW light exposure at 375 nm. Clear variations of the GaN HEMT performance related to the charge generation and the relevant threshold voltage shift within the semiconductor layers are recognizable in the reported results. The scattering parameters and the noise parameters are affected in a similar way as it occurs in GaAs HEMT's under optical irradiation in the visible range. A circuit model extraction has then been performed to analyze more deeply the effects of the UV exposure. The observed changes of the noise parameters might be ascribed to the effects of the increased gate conduction under illumination and have been efficiently modeled by an additional resistor between the internal gate and source terminals with an assigned noise temperature of 3053 °C.     

Thermal stability of organic transistors with short channel length on ultrathin foils

We demonstrate an effective design for fabrication of short channel organic transistors (<3 μm channel length) on ultrathin 1 μm thick substrates that exhibit excellent thermal stability. For short channel transistors, we demonstrate durability up to 170 °C, with a theoretical cutoff frequency above 100 kHz, and stable performance in cyclic heating tests up to 120 °C. We fabricate inverter circuits to investigate their behavior upon heating and show that inverter gain can be improved by 150%. Device performance and topology changes were systematically analyzed after annealing steps to gain better understanding on the mechanism behind the performance change. This report on the thermal stability of short channel transistors on ultrathin films shows good durability at elevated temperatures and paves the way for high frequency imperceptible electronics.     

Polarity dependent structure and optical properties of freestanding GaN layers grown by hydride vapor phase epitaxy

GaN freestanding substrate was obtained by hydride vapor phase epitaxy directly on sapphire with porous network interlayer. The morphologies of Ga-face and N-face of freestanding GaN substrate were analyzed by a variety of characterization techniques before and after etching in boiled KOH for 1 min. The obtained characteristics of unetched GaN are strongly dependent on the growth polarity. The N-polar GaN layer has high free electron, impurity and point defect concentrations. In the layers grown on the (0 0 0 1) Ga-polar side, these concentrations are very low. After etching, the Ga-polar GaN has identical properties to those of the unetched Ga-polar GaN layer. But the etched N-polar GaN has significant difference with unetched N-polar GaN layer in structure and optical properties. The etched N-polar GaN has a smaller (0 0 0 2) DCXRD width (646″) than the unetched N-polar GaN (1351″). The optical quality of etched N-polar GaN is comparable with that of Ga-polar GaN, and the FWHMs of the D⁰X line of Ga-face and etched N-face are 9.3 and 12.8 meV, respectively. The LPP mode in the Raman spectra and FERB peak in PL spectra were used to analyze the free carrier concentration of two sides of etched and unetched freestanding GaN substrate.     

Reliability of Diode-Integrated SiC Power MOSFET(DioMOS)

Status of the reliability study on silicon carbide (SiC) power MOS transistors is presented. The SiC transistors studied are diode-integrated MOSFETs (DioMOS) in which a highly doped n-type epitaxial channel layer formed underneath the gate oxide acts as a reverse diode and thus an external Schottky barrier diode can be eliminated. The novel MOS device can reduce the total area of SiC leading to potentially lower cost as well as the size of the packaging. After summarizing the issues on reliability of conventional SiC MOS transistors, the improvements by the newly proposed DioMOS with blocking voltage of 1200 V are presented. The I–V characteristic of the integrated reverse diode is free from the degradation which is typically observed in conventional pn-junction-based body diode in SiC MOS transistors. The improved quality of the MOS gate in the DioMOS results in very stable threshold voltage within its variation less than 0.1 V even after 2000 h of serious gate voltage stresses of + 25 V and − 10 V at 150 °C. High temperature reverse bias test (HTRB) shows very stable off-state and gate leakage current up to 2000 h under the drain voltage of 1200 V at 150 °C. These results indicate that the presented DioMOS can be applied to practical switching systems free from the reliability issues.     

Study of the breakdown failure mechanisms for power AlGaN/GaN HEMTs implemented using a RF compatible process

The breakdown failure mechanisms for a family of power AlGaN/GaN HEMTs were studied. These devices were fabricated using a commercially available MMIC/RF technology with a semi-insulating SiC substrate. After a 10 min thermal annealing at 425 K, the transistors were subjected to temperature dependent electrical characteristics measurement. Breakdown degradation with a negative temperature coefficient of ?0.113 V/K for the devices without field plate was found. The breakdown voltage is also found to be a decreasing function of the gate length. Gate current increases simultaneously with the drain current during the drain-voltage stress test. This suggests that the probability of a direct leakage current path from gate to the 2-DEG region. The leakage current is attributed by a combination of native and generated traps/defects dominated gate tunneling, and hot electrons injected from the gate to channel. Devices with field plate show an improvement in breakdown voltage from ～40 V (with no field plate) to 138 V and with lower negative temperature coefficient. A temperature coefficient of ?0.065 V/K was observed for devices with a field plate length of 1.6 μm.     

Epitaxial growth of nonpolar GaN films on r-plane sapphire substrates by pulsed laser deposition

Single-crystalline nonpolar GaN epitaxial films have been successfully grown on r-plane sapphire (Al₂O₃) substrates by pulsed laser deposition (PLD) with an in-plane epitaxial relationship of GaN[1-100]//Al₂O₃[11-20]. The properties of the ~500 nm-thick nonpolar GaN epitaxial films grown at temperatures ranging from 450 to 880 °C are studied in detail. It is revealed that the surface morphology, the crystalline quality, and the interfacial property of as-grown ~500 nm-thick nonpolar GaN epitaxial films are firstly improved and then decreased with the growth temperature changing from 450 to 880 °C. It shows an optimized result at the growth temperature of 850 °C, and the ~500 nm-thick nonpolar GaN epitaxial films grown at 850 °C show very smooth surface with a root-mean-square surface roughness of 5.5 nm and the best crystalline quality with the full-width at half-maximum values of X-ray rocking curves for GaN(11-20) and GaN(10-11) of 0.8° and 0.9°, respectively. Additionally, there is a 1.7 nm-thick interfacial layer existing between GaN epitaxial films and r-plane sapphire substrates. This work offers an effective approach for achieving single-crystalline nonpolar GaN epitaxial films for the fabrication of nonpolar GaN-based devices.     

The excellent spontaneous ultraviolet emission of GaN nanostructures grown on silicon substrates by thermal vapor deposition

In this study, GaN nanostructures were grown on p-Si (111) substrate by thermal chemical vapor deposition (TCVD). Ga vapor directly reacted with NH₃ solution in N₂ carrier gas flow of 2 L/min at different temperatures (950–1050 °C). The influence of NH₃ solution and growth temperature on the morphology, structure, optical and photoresponse properties of GaN nanostructures was investigated. Scanning electron microscopy images showed that the densities of the NWs varied with increasing temperature. The use of NH₃ solution and increased growth temperature improved the crystalline quality of GaN nanostructures. The photoluminescence (PL) spectra of nanostructures displayed a near band-edge (NBE) emission at around 363–367 nm. Higher growth temperature (1050 °C) resulted in a strong NBE emission with no yellow emission peak. With +5 V applied bias, the NWs metal–semiconductor–metal UV photodetector exhibited a high photocurrent of 1.6×10⁻³ A. The photocurrent to dark current contrast ratio was 120.     

Reliability of 100 nm AlGaN/GaN HEMTs for mm-wave applications

The effect of gate metallization and gate shape on the reliability and RF performance of 100 nm AlGaN/GaN HEMTs on SiC substrate for mm-wave applications has been investigated under on-state DC-stress tests. By replacing the gate metallization from NiPtAu to PtAu the median time to failure at T_ch = 209 °C can be improved from 10 h to more than 1000 h. Replacing the PtAu T-gate by a spacer gate further reduces the degradation rate under on-state stress, but decreases the current-gain cut-off frequency from 75 GHz to 50 GHz. Physical failure analysis using electroluminescence and TEM cross-section revealed pit and Ni void formation at the gate foot as the main degradation mechanisms of devices with NiPtAu T-gate. High resolution EDX mapping of stressed devices indicates that the formation of pits is caused by a local aluminium oxidation process. Simulation of the stress induced changes of the input characteristics of devices with NiPtAu gate further proves the formation of pits and Ni voids.     

Effects of substrate temperature on the degradation of RF sputtered NiO properties

Nickel oxide (NiO) film was grown on Si (100) substrate through RF sputtering of NiO target in Ar plasma at various temperatures ranging from room temperature (RT) to 300 °C. The structural study revealed (200) oriented NiO diffraction peak at RT and at 100 °C, however, by increasing the substrate temperature to 200 °C, intensity of (200) NiO diffraction peak was decreased. At higher temperature (300 °C), crystalline quality of NiO was significantly degraded and the film was decomposed into Ni. The EDS results confirmed an increase of Ni atomic percentage with increase of the substrate temperature. The surface morphology of NiO film at RT and at 100 °C displayed cubical like grains that were changed into elongated grains with further increase of the substrate temperature. The UV–vis reflectance measurements of NiO revealed a small decrease in its band gap by increasing the substrate temperature to 200 °C.     

Effect of RF power and substrate temperature on the properties of boron and gallium co-doped ZnO films

Boron and gallium co-doped ZnO (BGZO) films were prepared by radio-frequency (RF) magnetron sputtering under different RF powers (50–250 W) at room temperature and 200 °C, respectively. The influence of sputtering power and substrate temperature on the structural, morphological, electrical and optical properties of BGZO films was investigated. The results indicated that all the films showed preferentially c-axis orientation and structure of hexagonal wurtzite. The grain size decreased at higher sputtering power above 150 W. The carrier concentration and optical band gap (E_g) increased with the increasing of RF sputtering power. At RF power of 150 W, the films showed higher mobility and lower resistivity. Average optical transmittance of all the BGZO films is greater than 85% in the visible wavelength and did not change obviously with the sputtering power or substrate temperature.     

Development and characterization of the thermal behavior of packaged cascode GaN HEMTs

This study investigates the heat generation behavior of packaged normally-on multi-finger AlGaN/GaN high electron mobility transistors (HEMTs) that are cascoded with a low-voltage MOSFET (LVMOS) and a SiC Schottky barrier diode (SBD). By foremost carrying out electro-thermal simulation and related thermal measurements with infrared thermography and Raman spectroscopy for basic 5 mm GaN HEMTs, the location of hot spot in operating device can be obtained. Based on the outcome, further packaged cascode GaN HEMT is analyzed. A hybrid integration of the GaN-HEMT, LVMOS, and SiC SBD are assembled on a directly bonded copper (DBC) substrate in the four-pin metal case TO-257 package. The metal plate is used as both the source terminal and heat sink. The analytical results of thermal investigation are confirmed by comparing them with the infrared thermographic measurements and numerical results obtained from a simulation using Ansys Icepak. For a power dissipation of less than 11.8 W, the peak temperature of the GaN HEMTs is 118.7 °C, obtained from thermal measurements.     

Single-grain Si thin-film transistors SPICE model,analog and RF circuit applications

Single-grain thin-film transistors (SG-TFTs) fabricated inside location-controlled using μ-Czochralski process exhibit SOI-FETs like performance despite processing temperatures remaining below 350 °C. Thus, the SG-TFT is a potential technology for large-area highly-integrated electronic system and system-in-package, taking advantage of the system-on-flexible substrate and low manufacturing cost capabalities. The SG-TFT is modeled based on the BSIMSOI SPICE model where the mobility parameter is modified to fit the SG-TFT behavior. Therefore, analog and RF circuits can be designed and benchmarked. A two-stage telescopic cascode operational amplifier fabricated in a prototype 1.5 μm SG-TFT technology demonstrates DC gain of 55 dB and unity-gain bandwidth of 6.3 MHz. A prototype CMOS voltage reference demonstrates a power supply rejection ratio (PSRR) of 50 dB. With unity-gain frequency, f_T, in the GHz range, the SG-TFT can also enable RF circuits for wireless applications. A 12 dB gain RF cascode amplifier with integrated on-chip inductors operating in the 433 MHz ISM band is demonstrated.     

Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K

The linearity of triple gate nanowire transistors (NWs) implemented on a Silicon-On-Insulator (SOI) substrate is investigated in this work considering temperature (T) influence. The analysis is performed in long channel nanowire MOSFETs with different fin width (W_FIN), from quasi-planar structures (W_FIN = 10 μm) to narrow devices (9.5 nm), operating as single-transistor amplifiers from room temperature down to 100 K. The total, second and third order harmonic distortions (THD, HD2 and HD3, respectively) are extracted using the Integral Function Method (IFM). The analysis is divided in two parts. First, a fixed input signal is applied at the gate of the single-transistor amplifiers and, then, the output signal is fixed. Transport parameters such as effective mobility (μ_eff), mobility degradation coefficient (θ) and series resistance (R_S) have been extracted down to 100 K and correlated to the distortion to explain linearity peaks behavior with temperature and fin width. Narrow transistors have shown improved linearity mainly due to higher intrinsic voltage gain (A_V) considering the entire temperature range. Low temperature operation has shown to degrade the linearity characteristics of both wide and narrow NW MOSFETs.     

A 24 W Ku band GaN based power amplifier with 9.1 dB linear gain

A Ku-band power amplifier is successfully developed with a single chip 4.8 mm AlGaN/GaN high electron mobility transistors (HEMTs). The AlGaN/GaN HEMTs device, achieved by E-beam lithography г-gate process, exhibited a gate-drain reverse breakdown voltage of larger than 100 V, a cutoff frequency of f_T=30 GHz and a maximum available gain of 13 dB at 14 GHz. The pulsed condition (100 μs pulse period and 10% duty cycle) was used to test the power characteristic of the power amplifier. At the frequency of 13.9 GHz, the developed GaN HEMTs power amplifier delivers a 43.8 dBm (24 W) saturated output power with 9.1 dB linear gain and 34.6% maximum power-added efficiency (PAE) with a drain voltage of 30 V. To our best knowledge, it is the state-of-the-art result ever reported for internal-matched 4.8 mm single chip GaN HEMTs power amplifier at Ku-band.     

Sub-1 V,pico-watt subthreshold CMOS voltage reference circuit with dual temperature compensation

A pico-watt CMOS voltage reference is developed using an SK Hynix 0.18 µm CMOS process. The proposed architecture is resistorless and consists of MOSFET circuits operated in the subthreshold region. A dual temperature compensation technique is utilized to produce a near-zero temperature coefficient reference output voltage. Experimental results demonstrate an average reference voltage of 250.7 mV, with a temperature coefficient as low as 3.2 ppm/°C for 0 to 125 °C range, while the power consumption is 545 pW under a 420 mV power supply at 27 °C. The power supply rejection ratio and output noise without any filtering capacitor at 100 Hz are −54.5 dB and 2.88 µV/Hz^1/2, respectively. The active area of the fabricated chip is 0.00332 mm².     

Influence of processing and annealing steps on electrical properties of InAlN/GaN high electron mobility transistor with Al2O3 gate insulation and passivation

We report on preparation and electrical characterization of InAlN/AlN/GaN metal–oxide–semiconductor high electron mobility transistors (MOS HEMTs) with Al₂O₃ gate insulation and surface passivation. About 12 nm thin high-κ dielectric film was deposited by MOCVD. Before and after the dielectric deposition, the samples were treated by different processing steps. We monitored and analyzed the steps by sequential device testing. It was found that both intentional (ex situ) and unintentional (in situ before Al₂O₃ growth) InAlN surface oxidation increases the channel sheet resistance and causes a current collapse. Post deposition annealing decreases the sheet resistance of the MOS HEMT devices and effectively suppresses the current collapse. Transistors dimensions were source-to-drain distance 8 μm and gate width 2 μm. A maximum transconductance of 110 mS/mm, a drain current of ～0.6 A/mm (V_GS = 1 V) and a gate leakage current reduction from 4 to 6 orders of magnitude compared to Schottky barrier (SB) HEMTs was achieved for MOS HEMT with 1 h annealing at 700 °C in forming gas ambient. Moreover, InAlN/GaN MOS HEMTs with deposited Al₂O₃ dielectric film were found highly thermally stable by resisting 5 h 700 °C annealing.     

DC and microwave characteristics of Lg 50 nm T-gate InAlN/AlN/GaN HEMT for future high power RF applications

The DC and microwave characteristics of L_g = 50 nm T-gate InAlN/AlN/GaN High Electron Mobility Transistor (HEMT) on SiC substrate with heavily doped n+ GaN source and drain regions have demonstrated using Synopsys TCAD tool. The proposed device features an AlN spacer layer, AlGaN back-barrier and SiN surface passivation. The proposed HEMT exhibits a maximum drain current density of 1.8 A/mm, peak transconductance (g_m) of 650 mS/mm and ft/fmax of 118/210 GHz. At room temperature, the measured carrier mobility, sheet charge carrier density (n_s) and breakdown voltage are 1195 cm²/Vs, 1.6 × 10¹³ cm⁻² and 18 V respectively. The superlatives of the proposed HEMTs are bewitching competitor for future monolithic microwave integrated circuits (MMIC) applications particularly in W-band (75–110 GHz) high power RF applications.     

Synthesis and characterization of gallium nitride nanoparticles by using solvothermal-soft-chemical methodology

GaN nanoparticles have been synthesized by solvothermal method. Gallium acetyl-acetonate and ammonium acetate were mixed in stoichiometry conditions. The reaction was induced in different solvents such as ethanol, ethylene glycol, propanol and benzene. The as-prepared materials were heat-treated from 240 to 950 °C. X-ray photoelectron spectroscopy (XPS) and X-ray diffraction (XRD) put in evidence that the resulting intrinsic-structure is highly linked with the solvent in turn and with temperature. It was found that wurzite phase is reached at 950 °C with benzene as a solvent; with surface area of 50 m² g⁻¹, measured by nitrogen physisorption. In addition, well-defined GaN-nanoparticles were determined using SEM–EDS and HRTEM for a diffraction-selected area (SAED). Moreover, optical properties obtained by using photoluminescence (PL) spectroscopy indicated a well crystal-definition from bands at 2.85 and 3.0 eV related with structural defects. GaN deposited onto an ITO substrate induced a more cathodic current corresponding to hydrogen evolution compared with ITO free of GaN in neutral conditions.