A novel topology for grounded-to-floating resistor conversion in CMOS technology

A new circuit topology to convert grounded resistors to an equivalent floating resistor is presented and discussed. The value of the resulting floating resistor equals the sum of the two grounded resistors. The new topology can be used to convert either passive, active grounded resistors or active grounded conductances. The new topology is used in the design of a current controlled very high value floating resistor in the range of GΩ. This was achieved by utilising the output conductance of two matched transistors operating in the subthreshold region and biased using a 500 nA current. The practicality of the new topology is demonstrated through the design of a very low frequency bandpass filter for artificial insect vision and pacemaker applications. Simulations results using Level 49 model parameters in HSPICE show an introduced total harmonic distortion of less than 0.25% for a 1 V_pp input signal in a 3.3 V 0.25 μm CMOS technology. Statistical modelling of the new topology is also presented and discussed.     

Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

In this paper, a multi-level wordline driver scheme is presented to improve 6T-SRAM read and write stability. The proposed wordline driver generates a shaped pulse during the read mode and a boosted wordline during the write mode. During read, the shaped pulse is tuned at nominal voltage for a short period of time, whereas for the remaining access time, the wordline voltage is reduced to save the power consumption of the cell. This shaped wordline pulse results in improved read noise margin without any degradation in access time for small wordline load. The improvement is explained by examining the dynamic and nonlinear behavior of the SRAM cell. Furthermore, during the hold mode, for a short time (depending on the size of boosting capacitance), wordline voltage becomes negative and charges up to zero after a specific time that results in a lower leakage current compared to conventional SRAM. The proposed technique results in at least 2× improvement in read noise margin while it improves write margin by 3× for lower supply voltages than 0.7 V. The leakage power for the proposed SRAM is reduced by 2% while the total power is improved by 3% in the worst case scenario for an SRAM array. The main advantage of the proposed wordline driver is the improvement of dynamic noise margin with less than 2.5% penalty in area. TSMC 65 nm technology models are used for simulations.     

SOI CMOS SRAM单元单粒子翻转效应的模拟

为简单快速模拟静态随机存储器(SRAM)的单粒子效应,在二维器件数值模拟的基础上,以经典的双指数模型为原型,通过数值拟合得到了单粒子效应瞬态电流脉冲的表达式,考虑晶体管偏压对瞬态电流的影响,得到修正的瞬态电流表达式,将其带入电路模拟软件HSPICE中进行SRAM存储单元单粒子翻转效应的电路模拟,通过与实际单粒子实验结果的对比,验证了这种模拟方法的实用性。     

Gate leakage current reduction in IP3 SRAM cells at 45 nm CMOS technology for multimedia applications

We have presented an analysis of the gate leakage current of the IP3 static random access memory (SRAM) cell structure when the cell is in idle mode (performs no data read/write operations) and active mode (performs data read/write operations), along with the requirements for the overall standby leakage power, active write and read powers. A comparison has been drawn with existing SRAM cell structures, the conventional 6T, PP, P4 and P3 cells. At the supply voltage, V_DD = 0.8 V, a reduction of 98%, 99%, 92% and 94% is observed in the gate leakage current in comparison with the 6T, PP, P4 and P3 SRAM cells, respectively, while at V_DD = 0.7 V, it is 97%, 98%, 87% and 84%. A significant reduction is also observed in the overall standby leakage power by 56%, the active write power by 44% and the active read power by 99%, compared with the conventional 6T SRAM cell at V_DD = 0.8 V, with no loss in cell stability and performance with a small area penalty. The simulation environment used for this work is 45 nm deep sub-micron complementary metal oxide semiconductor (CMOS) technology, t_ox = 2.4 nm, V_thn = 0.22 V, V_thp = 0.224 V, V_DD = 0.7 V and 0.8 V, at T = 300 K.     

SRAM devices and circuits optimization toward energy efficiency in multi-Vth CMOS

Minimum-energy-driven circuit design is highly required in numerous emerging applications such as mobile electronics, wireless sensor nodes, implantable biomedical devices, etc. Due to high computing capability requirements in such applications, SRAMs play a critical role in energy consumption. This paper presents SRAM energy analysis utilizing multi-threshold (multi-V_th) voltage devices and various circuit techniques for power reduction and performance improvement, and suggests optimal device combinations for energy efficiency improvement. In general, higher-V_th devices are preferred in the cross-coupled latches and the write access transistors for reducing leakage current while lower-V_th devices are desired in the read port for implementing higher performance. However, excessively raised V_th in the write paths, i.e. the cross-coupled latches and the write access transistors, leads to slower write speed than read, quickly nullifying improved energy efficiency. In this work, the energy efficiency improvement of 6.24× is achieved only through an optimal device combination in a commercial 65 nm CMOS technology. Employing power reduction and performance boosting techniques together with the optimal device combination enhances the energy efficiency further up to 33×.     

SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction

A 70-Mb SRAM is designed and fabricated on a 65-nm CMOS technology. It features a 0.57-/spl mu/m/sup 2/ 6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with dynamically controlled sleep transistor. SRAM virtual ground in standby is controlled by programmable bias transistors to achieve good voltage control with fine granularity under process skew. It also has a built-in programmable defect "screen" circuit for high volume manufacturing. The measurements showed that the SRAM leakage can be reduced by 3-5/spl times/ while maintaining the integrity of stored data.     

A boosted negative bit-line SRAM with write-assisted cell in 45 nm CMOS technology

A new 11 T SRAM cell with write-assist is proposed to improve operation at low supply voltage.In this technique,a negative bit-line voltage is applied to one of the write bit-lines,while a boosted voltage is applied to the other write bit-line where transmission gate access is used in proposed 11 T cell.Supply voltage to one of the inverters is interrupted to weaken the feedback.Improved write feature is attributed to strengthened write access devices and weakened feedback loop of cell at the same time.Amount of boosting required for write performance improvement is also reduced due to feedback weakening,solving the persistent problem of half-selected cells and reliability reduction of access devices with the other suggested boosted and negative bit-line techniques.The proposed design improves write time by 79％,63％ and slower by 52％ with respect to LP 10 T,WRE 8 T and 6 Tcells respectively.It is found that write margin for the proposed cell is improved by about 4×,2.4× and 5.37× compared to WRE8 T,LP10 T and 6 T respectively.The proposed cell with boosted negative bit line (BNBL) provides 47％,31％,and 68.4％ improvement in write margin with respect to no write-assist,negative bit line (NBL) and boosted bit line (BBL) write-assist respectively.Also,new sensing circuit with replica bit-line is proposed to give a more precise timing of applying boosted voltages for improved results.All simulations are done on TSMC 45 nm CMOS technology.     

Static noise margin variation for sub-threshold SRAM in 65-nm CMOS

The increased importance of lowering power in memory design has produced a trend of operating memories at lower supply voltages. Recent explorations into sub-threshold operation for logic show that minimum energy operation is possible in this region. These two trends suggest a meeting point for energy-constrained applications in which SRAM operates at sub-threshold voltages compatible with the logic. Since sub-threshold voltages leave less room for large static noise margin (SNM), a thorough understanding of the impact of various design decisions and other parameters becomes critical. This paper analyzes SNM for sub-threshold bitcells in a 65-nm process for its dependency on sizing, V/sub DD/, temperature, and local and global threshold variation. The V/sub T/ variation has the greatest impact on SNM, so we provide a model that allows estimation of the SNM along the worst-case tail of the distribution.     

Design of a novel CMOS/MTJ-based multibit SRAM cell with low store energy for IoT applications

ABSTRACT

With rapid growth of Internet of Things, more and more devices are getting connected, which results in generation of large amount of data. To convert this collected raw data into useful information, it needs to be processed. However, during processing a significant amount of energy is spent in bringing data from off-chip non-volatile memory to on-chip memory. In addition, these devices are generally operated in ‘Normally OFF’ mode, which requires energy intensive boot process for waking up. Addressing these issues, Magnetic Tunnel Junction offers features like non-volatility and high integration density, which allows storage of data and instruction closer to the core. Therefore, this work proposes a hybrid multibit SRAM cell, which integrates MTJ with conventional 6T SRAM cell. The proposed SRAM cell supports multiple bit storage within a single cell. However, one of the critical issues with the MTJ is high-energy consumption while storing data. Hence, we also propose a store assist circuit for multibit SRAM cell, which asynchronously terminates the store operation after its completion to reduce the power consumption. Our simulation results show that the store assist circuit results in reduction of store energy by 35% and 72% when compared with existing multibit non-volatile SRAM.     

New configuration memory cells for FPGA in nano-scaled CMOS technology

In nano-scaled CMOS technology, the reduction of soft error rate and leakage current are the most important challenges in designing Field Programmable Gate Arrays (FPGA). To overcome these challenges, based on the observations that most configuration bit-streams of FPGA are zeros across different designs and that configuration memory cells are not directly involved with signal propagation delays in FPGA, this paper presents three new low-leakage and hardened configuration memory cells for nano-scaled CMOS technology. These cells are completely hardened when zeros are stored in the cells and cannot flip from particle strikes at the sensitive cell nodes. These cells retain their data with leakage currents and positive feedback without a refresh cycle. Simulation results show that the proposed cells are working correctly during their configuration and idle cycles and that our cells have a lower soft error rate and leakage current in 22-nm as well as in 65-nm technologies.     

A scaled, high-performance (4.5 fJ) bipolar device in a 0.35 μmhigh-density BiCMOS SRAM technology

We present the performance improvements obtained both by scaling the Selectively Compensated Collector (SCC) BJT and by using a modified Current-Mode Logic (CML) gate configuration. Scaling the perimeter parameter by using the (tighter) bitcell design rules results in a ~30% reduction in parasitic capacitances, and a 23% lower power-delay product; reducing it from 48 fJ to 37 fJ. The greatest return comes from using a modified CML gate, which has an n-MOS current source. At a supply voltage of 1.1 V, and at 40 μA switching current, the minimum power-delay product of this CML gate is a silicon-substrate bipolar record 4.5 fJ     

A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply

Column-based dynamic power supply has been integrated into a high-frequency 70-Mb SRAM design that is fabricated on a high-performance 65-nm CMOS technology. The fully synchronized design achieves a 3-GHz operating frequency at 1.1-V power supply. The power supply at SRAM cell array is dynamically switched between two different voltage levels during READ and WRITE operations. Silicon measurement has proven this method to be effective in achieving both good cell READ and WRITE margins, while lowering the overall SRAM leakage power consumption.     

High-speed reduced-leakage SRAM memory cell design techniques for low-power 65 nm FD-SOI/SON CMOS technology

The paper presents a detailed study on the sub-1 V high speed operation with reduced leakage design techniques for conventional 6T Static Random Access Memory (SRAM) on fully depleted Silicon-on Insulator (FD-SOI) and fully depleted Silicon-on-Nothing (FD-SON) technology. Performance of SON MOSFET is found to be significantly better both in terms of power and speed from its equivalent SOI device. Future devices with advanced technology are promising for low-power application. The most promising high-speed, low-power operation techniques are introduced, analyzed and compared into 65 nm low-power FD-SOI/SON technology. Hspice simulations conclude Drive Source Line (DSL) architecture as the best option for high speed operation in sub 100 nm technology without affecting the Static Noise Margin (SNM) of the cells.     

Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS

In nanoscaled technologies, increased inter-die and intra-die variations in process parameters can result in large number of parametric failures in an SRAM array, thereby, degrading yield. In this paper, we propose a self-repairing SRAM to reduce parametric failures in memory. In the proposed technique, on-chip monitoring of leakage current and/or delay of a ring oscillator is used to determine the inter-die process corner of an SRAM die. Depending on the inter-die Vt shift, the self-repair system selects the proper body bias to reduce parametric failures. Simulations using predictive 70-nm device show that the proposed self-repairing SRAM improves design yield by 5%-40%. A test-chip is designed and fabricated in IBM 0.13-mum CMOS technology to successfully demonstrate the operation of the self-repair system.     

Threshold voltage-minimum gate length trade-off in buried channelPMOS devices for scaled supply voltage CMOS technologies

The trade-off between threshold voltage (V_th) and the minimum gate length (L_min) is discussed for optimizing the performance of buried channel PMOS transistors for low voltage/low power high-speed digital CMOS circuits. In a low supply voltage CMOS technology it is desirable to scale V_th and L_min for improved circuit performance. However, these two parameters cannot be scaled independently due to the channel punch-through effect. Statistical process/device modeling, split lot experiments, circuit simulations, and measurements are performed to optimize the PMOS transistor current drive and CMOS circuit speed. We show that trading PMOS transistor V_th for a smaller L_min results in faster circuits for low supply voltage (3.3 to 1.8 V) n⁺-polysilicon gate CMOS technology, Circuit simulation and measurements are performed in this study. Approximate empirical expressions are given for the optimum buried channel PMOS transistor V _th for minimizing CMOS circuit speed for cases involving: (1) constant capacitive load and (2) load capacitance proportional to MOS gate capacitance. The results of the numerical exercise are applied to the centering of device parameters of a 0.5 μm 3.3 V CMOS technology that (a) matches the speed of our 0.5 μm 5 V CMOS technology, and (b) achieves good performance down to 1.8 V power supply. For this process the optimum PMOS transistor V_th (absolute value) is approximately 0.85-0.90 V     

Device to circuit reliability correlations for metal gate/high-k transistors in scaled CMOS technologies

Metal gate/high-k stacks are in CMOS manufacturing since the 45 nm technology node. To meet technology performance and yield targets, gate stack reliability is constantly being challenged. Assessing the associated reliability risk for CMOS products relies on a solid understanding of device to circuit reliability correlations. In this paper we summarize our findings on the correlation between device reliability and circuit degradation and highlight areas for future work to focus on.     

Interrelation of equivalent values for linear energy transfer of heavy charged particles and the energy of focused laser radiation

The estimations of equivalent values for linear energy transfer of heavy charged particles based on the results of experimental investigations of sensitivity of LSICs to local radiation effects with the use of the procedure of local laser irradiation are presented. The possibility of recalculation of the energy of laser radiation into equivalent values of linear energy transfer with the use of the measurements of the ionization reaction in the supply circuit of LSIC is substantiated. Uncertainties caused by the characteristics of the interaction of optical radiation with semiconductor structures are eliminated in the suggested procedure.     

A high-efficiency CMOS image sensor with air gap in situ MicroLens (AGML) fabricated by 0.18-/spl mu/m CMOS technology

The air gap in situ microlens (AGML) above-pixel sensor with 0.18-/spl mu/m CMOS image sensor technology has been successfully developed to dramatically improve the optical crosstalk and pixel sensitivity. We demonstrated excellent crosstalk diminution with the structure on small pixels. Compared with conventional 2.8 /spl mu/m square pixel, adopting the AGML can reduce the optical crosstalk up to 64%, and provide 21% in enhancement of photosensitivity at 0/spl deg/ incident angle. Furthermore, under 20/spl deg/ incident angle the optical crosstalk reduction and sensitivity enhancement are increased to 89% and 122%, respectively. Therefore, the AGML structure makes pixel size be further scaled down to less than 2.8 /spl mu/m square and maintain good performance.     

Low programming voltage floating gate analogue memory cells in standard VLSI CMOS technology

Floating gate MOSFET structures were fabricated in a standard 2 mu m double-polysilicon CMOS process which requires programming voltages of only 6.5-9 V. This considerable reduction in programming voltage is achieved by simultaneously exploiting tunnelling through the interpolysilicon oxide and capacitive geometries whose top poly-layers overlap the edges of the lower poly-layers.<>