A physical compact DC drain current model for long-channel undoped ultra-thin body (UTB) SOI and asymmetric double-gate (DG) MOSFETs with independent gate operation

In this paper, a new compact charge based DC model for the drain current of long channel fully depleted ultra-thin body SOI MOSFETs and asymmetric double-gate MOSFETs with independent gate operation (ADGMOSFETs) is presented. The model was validated by both TCAD simulations and electrical measurements with a good agreement. In particular, great care was taken during the derivation of the model in order to respect the physics of the device and to make the correct approximations. The obtained solutions can be viewed as a generalization of classical MOS theory to the case of undoped fully depleted ADGMOS. As a result, the model consists of relatively simple equations and is a promising approach for the compact modeling and parameter extraction of fully depleted SOI transistors.     

Analytical modelling of ultra-thin film depletion-mode SOI MOSFETs

Reliable analytical models for thin and ultra-thin film depletion-mode SOI MOSFETs have been developed. These models are based on the linearly varying potential (LVP) approximation in the Si film. They allow the understanding and optimization of electrical properties of these devices. In particular, the behaviour of the subthreshold swing and the transconductance is discussed and compared successfully with numerical simulation.     

Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors' model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors' analytical model is verified using two-dimensional device simulations.     

Elimination of parasitic bipolar-induced breakdown effects in ultra-thin SOI MOSFETs using narrow-bandgap-source (NBS) structure

In this paper, we introduce the Si-SiGe narrow bandgap-source (NBS) SOI device structure in order to improve the low drain-to-source breakdown voltage (V/sub BD/) in ultra-thin SOI devices. Reducing the potential barrier of valence band between source and body by applying the SiGe layer at the source region, we can improve the drain-to-source breakdown voltage by suppressing the hole accumulation in the body. As confirmed by 2D simulation results, NBS-SOI devices provide excellent performance compared to conventional SOI devices.<>     

Numerical and charge sheet models for thin-film SOI MOSFETs

Numerical charge sheet models applicable for all bias conditions are presented for the channel currents of long-channel SOI MOSFETs. From a comparison of the two models it is shown that the charge sheet analytic model accurately predicts the channel currents from weak to strong inversion regions. The results include analytic expressions for the drift and diffusion current components of individual channel currents, the front-gate and back-gate interaction parameter, and an analytic correlation between the surface potentials of the front and back channels when there is coupling between the two gates under nonthermal equilibrium conditions. The effect of SOI (silicon on insulator) film thickness on the drain current was investigated under different bias conditions for the back gate, and it was found that thin films are beneficial from the point of increased drain currents if the back channel is in depletion or inversion. It is also shown that, in addition to the charge coupling effects, dynamic interaction between the channels exists if the static current in one of the channels saturates     

Two-dimensional analytic modeling of very thin SOI MOSFETs

An analytic solution of the Poisson's equation for MOSFETs on very thin SOI (silicon on insulator) was developed using an infinite series method. The calculation region includes the thin SOI and the gate and buried oxides. The results of this model were found to agree well with a two-dimensional (PISCES) simulation in the subthreshold region and the linear region with small V_DS. This model is used to study the short-channel behavior of very small MOS transistors on thin SOI. It is found that with very thin SOI, short-channel effects are much reduced compared to bulk MOS transistors and depend on the bulk-substrate bias. The model also shows that it is possible to fabricate submicrometer transistors on very thin SOI even if the channel doping is nearly intrinsic     

On the gate capacitance limits of nanoscale DG and FD SOI MOSFETs

An analytical total gate capacitance C/sub G/ model for symmetric double-gate (DG) and fully depleted silicon-on-insulator (FD/SOI) MOSFETs of arbitrary Si film is developed and demonstrated. The model accounts for the effects of carrier-energy quantization and inversion-layer screening and is verified via self-consistent numerical solutions of the Poisson and Schro/spl uml/dinger equations. Results provide good physical insight regarding C/sub G/ degradation due to quantization and screening governed by device structure and/or transverse electric field for nanoscale DG and FD/SOI MOSFETs. Two limits of C/sub G/ at ON-state are then derived when the silicon film t/sub Si/ approaches zero and infinity. The effect of inversion-layer screening on C/sub G/, which is significant for ultrathin Si-film DG MOSFETs, is quantitatively defined for the first time. The insightful results show that the two-dimensional screening length for DG MOSFETs is independent of the doping density and much shorter than the bulk Debye length as a result of strong structural confinement.     

A Review of Core Compact Models for Undoped Double-Gate SOI MOSFETs

In this paper, we review the compact-modeling framework for undoped double-gate (DG) silicon-on-insulator (SOI) MOSFETs. The use of multiple gates has emerged as a new technology to possibly replace the conventional planar MOSFET when its feature size is scaled to the sub-50-nm regime. MOSFET technology has been the choice for mainstream digital circuits for very large scale integration as well as for other high-frequency applications in the low-gigahertz range. But the continuing scaling of MOSFET presents many challenges, and multiple-gate, particularly DG, SOI devices seem to be attractive alternatives as they can effectively reduce the short-channel effects and yield higher current drive. Core compact models, including the analysis for surface potential and drain-current, for both the symmetric and asymmetric DG SOI MOSFETs, are discussed and compared. Numerical simulations are also included in order to assess the validity of the models reviewed     

Measurement and modeling of the sidewall threshold voltage ofmesa-isolated SOI MOSFETs

Five-terminal silicon-on-insulator (SOI) MOSFETs have been characterized to determine the threshold voltage at the front, back, and sidewall as a function of the body bias. The threshold voltage shift with the body bias at the front and back interfaces can be explained by the standard bulk body effect equation. However, the threshold voltage shift at the sidewall is smaller than predicted by this equation and saturates at large body biases. This anomalous behavior is explained by two-dimensional charge sharing between the sidewall and the front and back interfaces. An analytical model that accounts for this charge sharing by a simple trapezoidal approximation of the depletion regions and correctly predicts the sidewall threshold voltage shift and its saturation is discussed. The model makes it possible to measure the sidewall threshold even when it is larger than the front threshold voltage     

Efficient thermal modeling of SOI MOSFETs for fast dynamic operation

An efficient dynamic thermal model has been developed for silicon-on-insulator (SOI) MOSFETs. The model is derived from the variational principle using a thermal functional, and is able to describe extremely fast dynamic thermal behavior in SOI devices subjected to sudden changes in power generation. The developed model is further converted into a thermal circuit with time-varying thermal resistances and capacitances. With the circuit implemented in a circuit simulator, these time-varying thermal resistances and capacitances are able to reasonably capture extremely fast temperature evolution in SOI devices without including a large number of nodes. The developed dynamic thermal model and circuit are verified with the rigorous device simulation including self-heating.     

Modeling of the subthreshold characteristics of SOI MOSFETs withfloating body

n-channel SOI MOSFETs with floating bodies show a threshold voltage shift and an improvement in subthreshold slope at high drain biases. The magnitude of this effect depends on the device parameters and the starting SOI substrate. A simple device model is presented that explains the observed characteristics to be due to MOS back-bias effects resulting from the positively charged floating body. The improvement in the subthreshold slope is the outcome of positive feedback between the body potential and the transistor channel current     

Compact modeling of quantum effects in symmetric double-gate MOSFETs

Quantum effects have been incorporated in the analytic potential model for double-gate MOSFETs. From extensive solutions to the coupled Schrodinger and Poisson equations, threshold voltage shift and inversion layer capacitance are extracted as closed form functions of silicon thickness and inversion charge density. With these modifications, the compact model is shown to reproduce C-V and I-V curves of double-gate MOSFETs consistent with those obtained from those measured from experimental FinFET hardware.     

History dependence of output characteristics ofsilicon-on-insulator (SOI) MOSFETs

It is demonstrated that the drain current overshoot in partially depleted SOI MOSFETs has a significant history dependence or memory effect, even in the absence of impact ionization under low drain biases. The measured output characteristics of partially depleted SOI MOSFETs are shown to be dynamically dependent on their switching history, frequency, and bias conditions, due to the finite time constants of carrier generation (thermal or impact ionization) and recombination in the floating body     

Reliability of the doping concentration in an ultra-thin body and buried oxide silicon on insulator (SOI) and comparison with a partially depleted SOI

This study compares the reliability of nMOSFETs with low- and high-doped ultra-thin body and buried oxide (UTBB) with fully depleted (FD) and partially depleted (PD) silicon on insulator (SOI). The high-doped devices display lower off-current leakage performance but more degradation in both hot-carrier stress (HCS) and positive bias temperature instability (PBTI) test at both room temperature and elevated temperature compared with the low-doped devices. The PBTI test indicates that the high-doped devices induce high tunneling leakage and that the degradation is highly associated with temperature. The degradation stabilizes with an increase in stress time. The thinner PD-SOI demonstrates low variation at the threshold voltage and low drive current under HCS. The FD-SOI has better drain leakage control than the PD-SOI.     

Compact Modeling Methodology of Strained-Si Channel-on-Insulator (SSOI) MOSFETs

Compact physical models for SSOI MOSFETs are presented. The models consider specific features for strained-Si devices including SSOI such as mobility enhancement, band offsets, junction capacitance, and self-heating effects. All of the floating-body current components in conventional SOI structure, which are generation/recombination current, reverse-bias (band-to-band and trap-assisted) junction tunneling currents, gate-induced drain leakage current, gatebody oxide tunneling current, and impact ionization current are applied to the SSOI device, and their effects are discussed. The model validity is confirmed by fabricated 70?nm bulk-Si (control) and strained-Si devices.     

Compact modeling of thermal resistance in bipolar transistors onbulk and SOI substrates

Analytical expressions for the thermal resistance of bipolar transistors on bulk and SOI substrates are presented. The models are derived on the basis of intuitive physical pictures and validated by comparison with experimental data and three-dimensional (3D) device simulation. The effect of bulk and SOI substrates, shallow- and deep-trench isolation, and multiple emitter fingers is accounted for. All models are suitable for both hand calculations and computer-aided design     

Modeling of drain current, capacitance and transconductance in thin film undoped symmetric DG MOSFETs including quantum effects

In this paper, we present a fast yet accurate semi-analytical model for the I-V and C-V characteristics of nanoscale undoped symmetric double gate (DG) MOSFETs. The model employs a parabolic potential approximation for the body potential in the coordinate normal to the interfaces in all regions of device operation. While carrier confinement phenomenon is taken into account, we calculate the surface electric field which is used to determine the inversion charge sheet density. The density is used in a compact classical model of the symmetric DG MOSFET as a core model. Some quantum effects which include the threshold voltage shift and effective oxide thickness increment are applied through some modifications to the core model. To assess the accuracy of the proposed model, the results of the model are compared to those of the numerical simulations. The comparison reveals the high accuracy of the proposed model.     

Compact modeling of a PD SOI MESFET for wide temperature designs

A compact model for the partially depleted (PD) silicon-on-insulator (SOI) metal semiconductor field effect transistor (MESFET) is presented. The absence of a gate-oxide makes the SOI MESFET extremely robust, able to withstand high voltages, and useful for extreme environment electronics. These devices have been fabricated using a standard SOI CMOS process. In contrast to SOI MOSFETs and GaAs MESFETs, the source-substrate voltage has a significant impact on the channel current. In this work a model has been developed that includes the effect of the buried oxide on the performance of the MESFET. The model has been verified for a wide temperature range of −180 to 150 °C. A behavioral model has been included to model the breakdown voltage. The core DC and RF models have been adapted from the commercially available Triquint's Own Model (TOM3) MESFET model. Building from the TOM3 model, a measurement-based approach is used to develop a four-terminal compact model using Verilog-A. The charge-based approach, using S-parameter measurements was used to develop the capacitance model. We also present a voltage reference circuit using two MESFET transistors to verify the model and explore wide temperature range circuit applications.     

The reaction characteristics of ultra-thin Ni films on undoped and doped Si (100)

Reaction characteristics of ultra-thin Ni films (5 nm and 10 nm) on undoped and highly doped (As-doped and B-doped) Si (100) substrates are investigated in this work. The sheet resistance (Rs) measurements confirm the existence of a NiSi salicidation process window with low Rs values within a certain annealing temperature range for all the samples except the one of Ni(5 nm) on P⁺-Si(100) substrate (abnormal sample). The experimental results also show that the transition reaction to low resistivity phase NiSi is retarded on highly doped Si substrates regardless of the initial Ni film thickness. Micro-Raman and x-ray diffraction (XRD) measurement show that NiSi forms in the process window and NiSi₂ forms in a higher temperature annealing process for all normal substrates. Auger electron spectroscopy (AES) results for the abnormal sample show that the high resistivity of the formation film is due to the formation of NiSi₂.     

Investigation of Thermal Noise in UTB GOI and SOI Devices

The thermal-noise performances of ultrathin-body silicon-on-insulator (SOI) and germanium-on-insulator (GOI) devices are investigated and compared through simulation in this paper. The figures-of-merit for noise characteristics are considered in terms of the minimum of noise figure (NF_min)and equivalent noise resistance (R_n). GOI devices exhibit better noise performance over SOI counterparts. The reduction in the supply voltage brings more distinct improvements of the noise performance of GOI devices. The dependence of noise parameters on the film thickness and spacer length is also analyzed. The results demonstrate that GOI devices are more suitable for RF and low-noise applications.