Ferroelectric transistor memory arrays on flexible foils

In this paper, we successfully fabricated and operated passive matrix P(VDF–TrFE) transistor arrays, i.e. memory arrays in which no pass-transistors or other additional electronic components are used. Because of the smaller cell, a higher integration density is possible. We demonstrate arrays up to a size of 16 × 16, processed on thin (25 μm) poly(ethylene naphthalate) substrates, using Indium–Gallium–Zinc–Oxide (IGZO) as the semiconductor and 200 nm-thick P(VDF–TrFE) as a ferroelectric gate dielectric. The memory transistors have remnant current modulations of ～10⁵ with a retention time of more than 12 days. They can be switched in less than 1 μs at operating voltages of 25 V. Switching speed is strongly decreased with decreasing voltage: at ～10 V the transistors do not switch within 10 s. This difference in switching speed of more than 4 orders in magnitude when changing the electric field by a factor of only 2.5 makes these memories robust towards disturb voltages, and forms the basis of integration of these transistors in passive matrix-addressable transistor arrays that contains only one (memory) transistor per cell. It is shown that with current technology and memory characteristics it is possible to scale up the array size in the future.     

Flexible high mobility pentacene transistor with high-k/low-k double polymer dielectric layer operating at −5 V

We report on the fabrication of pentacene-based thin-film transistors (TFTs) with a 230 nm-thick double polymer dielectric composed of 30 nm-thin low-k poly-4-vinyphenol (PVP) and 200 nm-thick high-k poly(vinylidene fluoride/trifluoroethylene) [P(VDF–TrFE)] dielectric on polyethersulfone (PES) films. Our 230 nm-thick double (high-k/low-k) polymer showed a good dielectric strength of ～2 MV/cm, a high capacitance of 26 nF/cm² with k = ～7. Based on this double polymer dielectric, our flexible pentacene TFT displayed a high saturation mobility of 1.22 cm²/V s, a threshold voltage of ?2.5 V, and on/off ratio of 10³, stably operating under ?5 V.     

Reconfigurable 1×4 InP-based optical switch

An integrated 1×4 InP-based optical switch is reported. The device is quite simple and full device operation is achieved by injecting electrical currents to two electrodes. Since the operation of the switch relies on current spreading, using the carrier-induced refractive index change in InGaAsP multiple quantum wells, an area-selective zinc in-diffusion process is used to regulate the current spreading and optimize device performance. As a result, the fabricated 1×4 switch exhibits a ?14 dB crosstalk between channels over a wavelength range of 30 nm, while maintaining low electrical power consumption and allowing the switch to be operated uncooled and under d.c. current conditions.     

105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers

We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105 nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart Cut^TM process to fabricate 200 mm GeOI wafers with Ge thickness down to 60–80 nm. A full Si MOS compatible pMOSFET process was implemented with HfO₂/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (I_ON, I_OFF, transconductance, low field mobility, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties (μ_h ～ 250 cm²/V/s, I_ON = 436 μA/μm for L_G = 105 nm), and OFF current densities comparable or better than those reported in the literature.     

Determination of the laterally homogeneous barrier height of palladium Schottky barrier diodes on n-Ge (1 1 1)

We have studied the experimental linear relationship between barrier heights and ideality factors for palladium (Pd) on bulk-grown (1 1 1) Sb-doped n-type germanium (Ge) metal-semiconductor structures with a doping density of about 2.5×10¹⁵ cm^?3. The Pd Schottky contacts were fabricated by vacuum resistive evaporation. The electrical analysis of the contacts was investigated by means of current–voltage (I–V) and capacitance–voltage (C–V) measurements at a temperature of 296 K. The effective barrier heights from I–V characteristics varied from 0.492 to 0.550 eV, the ideality factor n varied from 1.140 to 1.950, and from reverse bias capacitance–voltage (C^?2–V) characteristics the barrier height varied from 0.427 to 0.509 eV. The lateral homogenous barrier height value of 0.558 eV for the contacts was obtained from the linear relationship between experimental barrier heights and ideality factors. Furthermore the experimental barrier height distribution obtained from I–V and (C^?2?V) characteristics were fitted by Gaussian distribution function, and their mean values were found to be 0.529 and 0.463 eV, respectively.     

Organic field-effect transistors based on low-temperature processable transparent polymer dielectrics with low leakage current

A solution-based transparent polymer was investigated as the gate dielectric for organic field-effect transistors (OFETs). Organic thin films (400 nm) are readily fabricated by spin-coating a polyhydrazide solution under ambient conditions on the ITO substrates, followed by annealing at a low temperature (120 °C). The smooth transparent dielectrics exhibited excellent insulating properties with very low leakage current densities of ～10^?8 A/cm². High performance OFETs with evaporated pentacene as organic semiconductor function at a low operate voltage (?15 V). The mobility could reach as high as 0.7 cm²/Vs and on/off current ratio up to 10⁴. Solution-processed TIPS-pentacene OFETs also work well with this polymer dielectric.     

Edge termination strategies for a 4 kV 4H–SiC thyristor

Thyristors able to block 4 kV have been fabricated and characterised. The experimental forward current is 1.3 A @ V_AK = 10 V for a 9 mA gate current during 550 ns. The device active area is 2.3 mm². The devices and their edge terminations have been designed using numerical simulations. Two different edge terminations have been envisaged (mesa and a combination of mesa and JTE). A SiO₂ passivation layer also improves the forward blocking voltage depending on the sign and the magnitude of the effective charge density in the oxide. The mesa protection is not enough to allowing the thyristor to block 5 kV, due to the low etching rate in SiC. Thus, a mesa/JTE protection has been used. The influence of the etching depth, the JTE dose and length on the forward blocking voltage of the thyristor has been studied in details. Simulation results have allowed designing the devices, not far from the optimal structure. The best results of the forward blocking voltage are 4 kV for the mesa protected thyristor, while the mesa/JTE combination yields 3.6 kV. Furthermore, experimental results confirm the simulations concerning the influence of the oxide thickness on the forward blocking voltage. The better results for the mesa protected thyristor are due to a lower interface SiC/SiO₂ charge density provided by the different oxidation processes (at different foundries).In addition, the comparison between experiments and simulations allows estimate the effective charge density of the SiO₂ layer in 10¹²–5 × 10¹² cm⁻² range for the two fabricated thyristors. The improvement in the forward blocking voltage must pass through an improvement of the passivation layer. Passivation still remains a technological key step to obtain SiC high-voltage devices.     

A high Schottky barrier between Ni and S-passivated n-type Si(1 0 0) surface

By minimizing surface states with sulfur passivation, a record-high Schottky barrier is achieved with nickel on n-type Si(1 0 0) surface. Capacitance–voltage measurements yield a flat-band barrier height of 0.97 eV. Activation-energy and current–voltage measurements indicate ～0.2-eV lower barriers for the Ni/Si(1 0 0) junction. These results accompany a previously-reported record-high Schottky barrier of 1.1 eV between aluminum and S-passivated p-type Si(1 0 0) surface. The operation of these metal/Si(1 0 0) junctions changes from majority-carrier conduction, i.e., a Schottky junction, to minority-carrier conduction, i.e., a p–n junction, with the increase in barrier height from 0.97 eV to 1.1 eV. Temperature-dependent current–voltage measurements reveal that the Ni/S-passivated n-type Si(1 0 0) junction is stable up to 110 °C.     

Enhancement in electrical performance of indium gallium zinc oxide-based thin film transistors by low temperature thermal annealing

We have studied the characteristics of transparent bottom-gate thin film transistors (TFTs) using In–Ga–Zn–O (IGZO) as an active channel material. IGZO films were deposited on SiO₂/Si substrates by DC sputtering techniques. Thereafter, the bottom-gate TFT devices were fabricated by depositing Ti/Au metal pads on IGZO films, where the channel length and width were defined to be 200 and 1000 μm, respectively. Post-metallization thermal annealing of the devices was carried out at 260, 280 and 300 °C in nitrogen ambient for 1 h. The devices annealed at 280 °C have shown better characteristics with enhanced field-effect mobility and high on–off current ratio. The compositional variation of IGZO films was also observed with different annealing temperatures.     

Amorphous SiC as a structural layer in microbridge-based RF MEMS switches for use in software-defined radio

This paper reports an effort to develop amorphous silicon carbide (a-SiC) films for use in shunt capacitor RF MEMS microbridge-based switches. The films were deposited using methane and silane as the precursor gases. Switches were fabricated using 500 nm and 300 nm-thick a-SiC films to form the microbridges. Switches made from metallized 500 nm-thick SiC films exhibited favorable mechanical performance but poor RF performance. In contrast, switches made from metallized 300 nm-thick SiC films exhibited excellent RF performance but poor mechanical performance. Load-deflection testing of unmetallized and metallized bulk micromachined SiC membranes indicates that the metal layers have a small effect on the Young’s modulus of the 500 nm and 300 nm-thick SiC MEMS. As for residual stress, the metal layers have a modest effect on the 500 nm-thick structures, but a significant affect on the residual stress in the 300 nm-thick structures.     

Self-aligned inversion n-channel In0.2Ga0.8As/GaAs metal–oxide–semiconductor field-effect-transistors with TiN gate and Ga2O3(Gd2O3) dielectric

A self-aligned process for fabricating inversion n-channel metal–oxide–semiconductor field-effect-transistors (MOSFET’s) of strained In_0.2Ga_0.8As on GaAs using TiN as gate metal and Ga₂O₃(Gd₂O₃) as high κ gate dielectric has been developed. A MOSFET with a 4 μm gate length and a 100 μm gate width exhibits a drain current of 1.5 mA/mm at V_g = 4 V and V_d = 2 V, a low gate leakage of <10^?7 A/cm² at 1 MV/cm, an extrinsic transconductance of 1.7 mS/mm at V_g = 3 V, V_d = 2 V, and an on/off ratio of ～10⁵ in drain current. For comparison, a TiN/Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As MOS diode after rapid thermal annealing (RTA) to high temperatures of 750 °C exhibits excellent electrical and structural performances: a low leakage current density of 10^?8–10^?9 A/cm², well-behaved capacitance–voltage (C–V) characteristics giving a high dielectric constant of ～16 and a low interfacial density of state of ～(2～6) × 10¹¹ cm^?2 eV^?1, and an atomically sharp smooth Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As interface.     

Flexible nonvolatile organic ferroelectric memory transistors fabricated on polydimethylsiloxane elastomer

The flexible organic ferroelectric nonvolatile memory thin film transistors (OFMTs) were fabricated on polydimethylsiloxane (PDMS) elastomer substrates, in which an organic ferroelectric poly(vinylidene-trifluoroethylene) and an organic semiconducting poly(9,9-dioctylfluorene-co-bithiophene) layers were used as gate insulator and active channel, respectively. The carrier mobility, on/off ratio, and subthreshold swing of the OFMTs fabricated on PDMS showed 5 × 10⁻² cm² V⁻¹ s⁻¹, 7.5 × 10³, and 2.5 V/decade, respectively. These obtained values did not markedly change when the substrate was bent with a radius of curvature of 0.6 cm. The memory on/off ratio was initially obtained to be 1.5 × 10³ and maintained to be 20 even after a lapse of 2000 s. The fabricated OFMTs exhibited sufficiently encouraging device characteristics even on the PDMS elastomer to realize mechanically stretchable nonvolatile memory devices.     

Characterization of interfacial reaction and chemical bonding features of LaOx/HfO2 stack structure formed on thermally-grown SiO2/Si(1 0 0)

A stack structure consisting of ～1.5 nm-thick LaO_x and ～4.0 nm-thick HfO₂ was formed on thermally grown SiO₂ on Si(1 0 0) by MOCVD using dipivaloymethanato precursors, and the influence of N₂ annealing on interfacial reaction for this stack structure was examined by using X-ray photoelectron spectroscopy and Fourier transform infrared attenuated total reflection. We found that compositional mixing between LaO_x and HfO₂ becomes significant from 600 °C upwards and that interfacial reaction between HfLa_yO_z and SiO₂ proceeds consistently at 1000 °C in N₂ ambience.     

Bottom gate organic thin-film transistors fabricated by ultraviolet transfer embossing with improved device performance

Ultraviolet transfer embossing is optimized to fabricate bottom gate organic thin-film transistors (OTFTs) on flexible plastic substrates, achieving significant improved device performance (μ = 0.01–0.02cm²/Vs; on/off ratio = 10⁴) compared with the top gate OTFTs made previously by the same method (μ = 0.001–0.002 cm²/Vs; on/off ratio = 10²). The performance improvement can be ascribed to the reduced roughness of the dielectric-semiconductor interface (R_rms = 0.852 nm) and thermally cross-linked PVP dielectric which leads to reduced gate leakage current and transistor off current in the bottom-gated configuration. This technique brings an alternative great opportunity to the high-volume production of economic printable large-area OTFT-based flexible electronics and sensors.     

Ferroelectric random access memory based on one-transistor–one-capacitor structure for flexible electronics

We have demonstrated a low temperature process for a ferroelectric non-volatile random access memory cell based on a one-transistor–one-capacitor (1T1C) structure for application in flexible electronics. The n-channel thin film transistors (TFTs) and ferroelectric capacitors (FeCaps) are fabricated using cadmium sulfide (CdS) as the semiconductor and poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] copolymer as the ferroelectric material, respectively. The maximum processing temperature for the TFTs is 100 °C and 120 °C for the FeCaps. The TFT shows excellent access control of the FeCap in the 1T1C memory cell, and the stored polarization signals are undisturbed when the TFT is off. The fabricated 1T1C memory cell was also evaluated in a FRAM circuit. The memory window on the bit line was demonstrated as 2.3 V, based on the 1T1C memory cell with a TFT having dimensions of 80 μm/5 μm (W/L) and a FeCap with an area of 0.2 × 10^?3 cm² using a bit line capacitor of 1 nF pre-charged at 17.2 V. The 1T1C memory cell is fabricated using photolithographic processes, allowing the integration with other circuit components for flexible electronics systems.     

1 Volt organic transistors with mixed self-assembled monolayer/Al2O3 gate dielectrics

Control of the threshold voltage and the subthreshold swing is critical for low voltage transistor operation. In this contribution, organic field-effect transistors (OFETs) operating at 1 V using ultra-thin (∼4 nm), self-assembled monolayer (SAM) modified aluminium oxide layers as the gate dielectric are demonstrated. A solution-processed donor–acceptor semiconducting polymer poly(3,6-di(2-thien-5-yl)-2,5-di(2-octyldodecyl)-pyrrolo[3,4-c]pyrrole-1,4-dione)thieno[3,2-b]thiophene) (PDPP2TTT) is used as the active layer. It is shown that the threshold voltage of the fabricated transistors can be simply tuned by carefully controlling the composition of the applied SAM. The optimised OFETs display threshold voltages around 0 V, low subthreshold slopes (150 ± 5 mV/dec), operate with negligible hysteresis and show average saturated field-effect mobilities in excess of 0.1 cm²/V s at 1 V.     

Demonstrations of 10 and 40 Gbps upstream transmissions using 1.2 GHz RSOA-based ONU in long-reach access networks

Carrier-distributed long-reach passive optical network (LR-PON) is a promising candidate for future access networks. In this work, we analyze and compare the 4 × 2.5 Gb/s and 4 × 10 Gb/s upstream traffics in a carrier-distributed LR-PON using four wavelength-multiplexed 2.5 Gb/s on–off keying (OOK) and 10 Gb/s optical orthogonal frequency division multiplexing-quadrature amplitude modulation (OFDM-QAM) signals. Four commercial 1.2 GHz bandwidth reflective semiconductor optical amplifiers (RSOAs) are used in each optical networking unit (ONU) for the generation of the upstream signal. Due to the limited bandwidth of the RSOA, only up to 2.5 Gb/s upstream OOK signal can be generated. However, by using the spectral efficient modulation, such as OFDM-QAM, 10 Gb/s data rate can be achieved. 20, 50 and 75 km fiber transmissions are also compared using the two different kinds of modulation respectively.     

Natural polyelectrolyte: Major ampullate spider silk for electrolyte organic field-effect transistors

The major ampullate (MA) silk collected from giant wood spiders Nephila pilipes consists of 12% glutamic acid (Glu) and 4% tyrosine (Tyr) acidic amino residues. The MA silk may act as a natural polyelectrolyte for organic field-effect transistors (OFETs). Pentacene and F₁₆CuPc OFETs were fabricated with the MA silk thin film as the gate dielectric. The MA silk thin film with surface roughness of 4 nm and surface energy of 36.1 mJ/m² was formed on glass using a hexafluoroisopropanol (HFIP) organic process. The MA silk gate dielectric in pentacene OFETs may improve the field-effect mobility (μ_FE,sat) value in the saturation regime from 0.11 in vacuum to 4.3 cm² V⁻¹ s⁻¹ in air ambient at ca. 70% RH. The corresponding threshold voltage (V_TH) value reduced from −6 V in vacuum to −0.5 V in air ambient. Similar to other polyelectrolytes, the changes of μ_FE,sat and V_TH may be explained by the generation of electric double layers (EDLs) in the MA silk thin film in air ambient due to water absorption.     

Fabrication of the flexible pentacene thin-film transistors on 304 and 430 stainless steel (SS) substrate

Flexible organic thin-film transistors (OTFT) were fabricated on 304 and 430 stainless steel (SS) substrate with aluminum oxide as a gate insulator and pentacene as an organic semiconductor. Chemical mechanical polishing (CMP) process was used to study the effect of the SS roughens on the dielectric properties of the gate insulator and OTFT characteristics. The surface roughness was decreased from 33.8 nm for 304 SS and 19.5 nm for 430 SS down to ～2.5 nm. The leakage current of the metal–insulator–metal (MIM) structure (Au/Al₂O₃/SS) was reduced with polishing. Mobility and on/off ratio of pentacene TFT with bare SS showed a wide range of values between 0.005 and 0.36 cm²/Vs and between 10³ and 10⁵ depending on the location in the substrate. Pentacene TFTs on polished SS showed an improved performance with a mobility of 0.24–0.42 cm²/Vs regardless of the location in the substrate and on/off ratio of ～10⁵. With self assembled monolayer formation of octadecyltrichlorosilane (OTS) on insulator surface, mobility and on/off ratio of pentacene TFT on polished SS was improved up to 0.85cm²/Vs and ～10⁶. I–V characteristics of pentacene TFT with OTS treated Al₂O₃/304 SS was also obtained in the bent state with a bending diameter (D) of 24, 45 or 70 mm and it was confirmed that the device performed well both in the linear regime and the saturation regime.