CHARACTERIZATION OF CAPACITIVE COUPLING FOR ON-CHIP CIRCULAR STACKED INDUCTORS

Capacitive coupling effects in some circular stacked inductors are studied in this paper, by taking into account the possible incomplete overlapping and cross-overlapping between up and bottom tracks of different layers. Formulas are derived for extracting the equivalent capacitance of double-and multi-spiral circular inductors with integral and fractional number of turns. Compared with the full-wave and the analytical methods with the completely overlapping assumption, the proposed method can predict equivalent capacitance and self-resonance frequency (f _SR ) accurately for on-chip circular stacked inductors used in the design of RFICs.     

An accurate model for a depletion mode IGFET used as a load device

An accurate model has been described for an n-channel, silicon gate, depletion mode insulated gate field effect transitor (IGFET), in configuration most often used in LSI design (V_GS=OV). The model is derived from basic semiconductor charge analysis, approximating the profile of the redistributed implanted impurities in the channel. Excellent agreement with experimental results is shown. This model has the potential to accurately predict the charge capacity behavior in storage cells, in very high density random access memories, where “pseudo depletion mode” devices are used.     

Some aspects of current gain variations in bipolar transistors

This paper deals with the study of the main mechanisms involved in the bipolar transistor current-gain variations.In the first part, we describe some properties of characteristic parameters N_S and I_SR of the surface “diode”; an attempt is made to explain the strong correlation between N_S and I_SR.In a second part, we analyse the influence of emitter current crowding, high injection in the base region, and base widening effects on the high level bias current gain value. Critical current densities beyond which each of these effects takes place are defined, allowing us to evaluate their comparative importance at a given collector current value. Our study shows that, on the one hand, for transistors affected by emitter-current crowding, the surface currents play an essential part in the high level bias current gain fall off and, on the other hand, the base widening effect has a very great influence on the static (I_C, V_EB) characteristic and on the emitter injection efficiency value.In the third part, the experimental results obtained are reported and compared with previously proposed analytical relations.     

Evaluation of mobility gaps and density of localized hole states in p-Ge/Ge1−x Six heterostructures in the quantum Hall effect mode

The temperature (0.1 K?T?20 K) and magnetic field (0 T?B?12 T) dependences of the longitudinal (ρ_xx) and Hall (ρ_xy) resistivities have been studied in detail for p-Ge/Ge_1?x Si_x (x=0.07) multilayer heterostructures with hole density p=(2.4–2.6)×10¹¹ cm^?2 and mobility μ=(1.1–1.7)×10⁴ cm² V^?1 s^?1. The energy spectrum parameters of two-dimensional (2D) hole gas in the quantum Hall effect mode have been determined. The mobility gap W=(2–2.5) meV and the background density of localized states g _c =(5–7)×10¹⁰ cm^?2 meV^?1 for the filling factors ν=1 and 2. The results are discussed in terms of long-range impurity potential models for selectively doped 2D systems.     

A Physical Model for On-Chip Spiral Inductors With Accurate Substrate Modeling

A physical-based analytical model for on-chip inductors is developed. A ladder structure is used to model the skin and proximity effects in metal lines. The substrate electric and substrate magnetic losses are accurately modeled by RC and RL ladder structures, respectively. The effective inductance reduction due to the eddy current in the lossy silicon substrate at high frequency is modeled by a negative mutual inductance between the inductor and the substrate. All the model parameters can be calculated from the layout and process parameters. On-chip inductors with different geometries and substrate resistivities were fabricated for the verifications. The measured results are in very good agreement with the proposed model. This generic model can be applied to various substrate resistivities; thus, it is suitable for different technologies. This model can facilitate the design and optimization of on-chip inductors for RF IC applications     

A new two-dimensional C-V model for prediction of maximum frequency of oscillation (fmax) of deep submicron AlGaN/GaN HEMT for microwave and millimeter wave applications

An analytical two-dimensional capacitance-voltage model for AlGaN/GaN high electron mobility transistor (HEMTs) is developed, which is valid from a linear to saturation region. The gate source and gate drain capacitances are calculated for 120 nm gate length including the effects of fringing field capacitances. We obtain a cut-off frequency (f_T) of 120 GHz and maximum frequency of oscillations (f_max) of 160 GHz. The model is very useful for microwave circuit design and analysis. Additionally, these devices allow a high operating voltage V_DS, which is demonstrated in the present analysis. These results show an excellent agreement when compared with the experimental data.     

The inductance model of coupled high-Tc superconducting microstrip lines

A simple analytical model of odd and even mode external inductance and kinetic inductance for coupled high-temperature superconducting (HTS) microstrip lines is developed. The kinetic inductance model is derived with the extended incremental inductance rule which is applied in a different way for different conductor thickness. The odd and even mode inductance, self- and mutual inductance, characteristic impedance, and attenuation constant are computed with the presented model expressions and the results agree well with that in published literature.     

双曲余弦高斯光束的模相关和模结构分析

基于二阶矩方法和正交模系展开法,推导出双曲余弦高斯光束的光束传输M2因子和模相干系数的解析表达式,从而可对双曲余弦高斯光束的模相关和模结构进行分析。提出了一种在实验室中产生双曲余弦高斯光束的简单方法。     

Effect of Temperature Variation on the Characteristics of Microwave Power AlGaN/GaN MODFET

The prime motivation for developing the proposed model of AlGaN/GaN microwave power device is to demonstrate its inherent ability to operate at much higher temperature. An investigation of temperature model of a 1 μm gate AlGaN/GaN enhancement mode n-type modulation-doped field effect transistor (MODFET) is presented. An analytical temperature model based on modified charge control equations is developed. The proposed model handles higher voltages and show stable operation at higher temperatures. The investigated temperature range is from 100 °K–600 °K. The critical parameters of the proposed device are the maximum drain current (I_Dmax), the threshold voltage (V_th), the peak dc trans-conductance (g_m), and unity current gain cut-off frequency (f_T). The calculated values of f_T (10–70 GHz) at elevated temperature suggest that the operation of the proposed device has sufficiently high current handling capacity. The temperature effect on saturation current, cutoff frequency, and trans-conductance behavior predict the device behavior at elevated temperatures. The analysis and simulation results on the transport characteristics of the MODFET structure is compared with the previously measured experimental data at room temperature. The calculated critical parameters suggest that the proposed device could survive in extreme environments.     

Proper choice of the measuring frequency for determining fT of bipolar transistors

The permissible frequencies (f) for measuring f_T are restricted to a certain range characterized by the condition $\text{f}{}_{\mathrm{T}}\text{= /s|β/s| f =}\text{const., i.e.}\text{/s|β/st| }}\text{1}\text{f}$. The boundaries of this range are determined by an analytical calculation and confirmed both by measurements and accurate computer simulations. It is shown that the upper measuring frequency limit f_h of high-speed transistors may drastically be reduced due to the strong influence of parasitic transistor and package parameters (e.g. f_h = 0,1 … 0,2f_Tmax. Therefore the operator must carefully choose his measuring frequency, by use of the relations presented, in order to avoid large errors in determining f_T and the other important transistor parameters (τ_n,C_eb) which can be derived from the current dependence of f_T.     

Scaling rules for SOI MOSFETs operating in the fully inverted mode

Two-dimensional device simulation was performed on silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect-transistors (MOSFETs) with various gate length L_g various top Si layer thickness t_Si and various buried oxide (BOX) layer thickness t_BOX. As a result, it was found that when t_BOX is large, short channel effect (SCE) cannot be suppressed in a fully depleted (FD) MOSFET only by the simple scaling rule maintaining the ratio of L_g to top Si layer t_Si more than four. It was also found that the scaling rule breaks down more seriously in a fully inverted (FI) MOSFET. It was confirmed that electric field from the drain region penetrates easily into thick BOX layer, which causes drain-induced barrier lowering (DIBL) at the top Si/BOX interface in deep sub-micron gates SOI MOSFETs. Consequently, it was concluded that the DIBL can be suppressed efficiently by reducing t_BOX even in a FI MOSFET.     

Numerical analysis of SiGe heterojunction bipolar phototransistor based on virtual substrate

SiGe heterojunction bipolar phototransistors based on Si_1?yGe_y virtual substrate have been proposed in this paper. The current gain and external quantum efficiency of the heterojunction bipolar phototransistors are calculated by solving one-dimensional diffusion equations. The computed results show that external quantum efficiency increases with the increase of Ge content of Si_1?yGe_y virtual substrate and a high external quantum efficiency of 142 can be obtained in the heterojunction bipolar phototransistor with ten periods of Ge/Si_0.4Ge_0.6 multi-quantum wells on virtual substrate with Ge content of 0.6. The dependences of external quantum efficiency and current gain on structure parameters of the heterojunction bipolar phototransistors are investigated in detail. It is useful for design and optimization of the heterojunction bipolar phototransistors.     

Channel current limitations in GaAs MESFETS

The maximum channel current, I_m, the maximum forward gate bias voltage, V_f, and the corresponding knee voltage, V_kf, play an important role in determining the maximum power handling capability of a GaAs MESFET. The definition of these parameters is given in a practical manner. Simple and yet accurate enough expressions for these parameters derived from a theoretical model are shown in terms of the geometrical and material parameters of the active channel of a device. A very simple expression for I_m obtained on an empirical basis is also shown. For the zero-gate-bias channel current, I_o, simple theoretical and empirical expressions are presented. Calculated values of I_m, V_f, V_kf and I_o using these expressions are in excellent agreement with their measured values for sample devices chosen from a variety of channel properties. A graphical presentation of I_m and that of the maximum channel-current enhancement ratio, I_m/I_o, are given as functions of basic channel parameters for practical purposes.     

Multistandard transceivers: state of the art and a new versatile implementation for fully active frequency agile filters

The various architectures of transceivers for current standards are firstly compared. Different possibilities to achieve multi-standard transceivers are also recalled and compared. We demonstrate that ease of realization and flexibility evolve in opposite directions. The advantages and drawbacks of reconfigurable active filters are indicated. We demonstrate that the second generation current controlled conveyor operating in current mode is perfectly suitable for the realization of frequency-agile filters. After a brief recall of the essential points of agile filters, a second order frequency agile bandpass filter operating in current mode is implemented with CCCII+ . It has four central frequencies whose values could be selected digitally. The validation results show that its tuning ratio n = f _0max/f _0min is equal to 5.1 with f _0max = 1.22 GHz.     

Analytical surface potential modeling and simulation of junction-less double gate (JLDG) MOSFET for ultra low-power analog/RF circuits

In this paper, a simple structure for short channel junction-less double gate (JLDG) MOSFET is proposed. Further expression for surface potential of JLDG has been derived using 2D Poisson׳s equation. Based on the proposed analytical model for surface potential distribution along channel thickness and channel length is derived. The proposed junction-less MOSFET has no p-n junction as the doping of channel is same to that of Source/Drain region. The analytical model is compared with numerical solution using ATLAS device simulator. The result shows the variation of channel potential with channel length, channel thickness, doping concentration and applied gate bias. Further, in this paper the analog performance and RF figure of merits (FOMs) have been investigated. The purpose of this research is to provide a physical explanation for improved analog and RF performance exhibited by the device. In this paper major FOMs such as trans-conductance (g_m), output conductance (g_d), early voltage (V_EA), intrinsic gain (A_V), trans-conductance generation factor (TGF), cut-off frequency (f_T), trans-conductance frequency product (TFP), gain frequency product (GFP), gain trans-conductance frequency product (GTFP) are analyzed. The simulation result shows that the JLDG exhibit a higher trans-conductance, higher cut-off frequency and lower drain conductance.     

Extraction of optimized parameters for Si0.6Ge0.4 material and SPP mode propagation through Si0.6Ge0.4/Ag/Si0.6Ge0.4 waveguide

The Lorentz model and modified Debye model （MDM） parameters forSi0.6Ge0.4 are presented. A nonlinear optimiza- tion algorithm is developed. The obtained parameters are used to determine the complex relative permittivity of Si0.6Ge0.4, and compared with the experimental data for validation. Finally the obtained parameters are used to analyze the properties of symmetric surface plasmon polariton （SPP） mode propagation in a dielectric-metal-dielectric （DMD） material constructed with silver （Ag） and Si0.6Ge0.4 for further verifying the extracted parameters.     

Improved reliability of AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) with high density silicon nitride passivation

We have systematically studied the effects of Si_xN_1 − x passivation density on the reliability of AlGaN/GaN high electron mobility transistors. Upon stressing, devices degrade in two stages, fast-mode degradation and followed by slow-mode degradation. Both degradations can be explained as different stages of pit formation at the gate-edge. Fast-mode degradation is caused by pre-existing oxygen at the Si_xN_1 − x/AlGaN interface. It is not significantly affected by the Si_xN_1 − x density. On the other hand, slow-mode degradation is associated with Si_xN_1 − x degradation. Si_xN_1 − x degrades through electric-field induced oxidation in discrete locations along the gate-edges. The size of these degraded locations ranged from 100 to 300 nm from the gate edge. There are about 16 degraded locations per 100 μm gate-width. In each degraded location, low density nano-globes are formed within the Si_xN_1 − x. Because of the low density of the degraded locations, oxygen can diffuse through these areas and oxidize the AlGaN/GaN to form pits. This slow-mode degradation can be minimized by using high density (ρ = 2.48 g/cm³) Si₃₆N₆₄ as the passivation layer. For slow-mode degradation, the median time to failure of devices with high density passivation is found to increase up to 2× as compared to the low density (ρ = 2.25 g/cm³) Si₄₃N₅₇ passivation. A model based on Johnson-Mehl-Avrami theory is proposed to explain the kinetics of pit formation.     

The quantum Hall effect in a wide p-Ge1−x Six/Ge/p-Ge1−x Six potential well

Quantum magnetotransport is investigated in a series of selectively doped p-type (Ge_1?x Si_x/Ge)×N multilayered structures with Ge layer widths from 100 to 250 Å in fields up to 35 T at 1.5–4.2 K. The plots of the magnetic-field dependence of the longitudinal (ρ _xx) and Hall (ρ _xy) magnetoresistance, as well as the ratio between the oscillation periods in strong and weak fields, vary significantly in samples with wide Ge layers and (or) with a high density of the two-dimensional gas. These features can be attributed to the participation of an additional subband in carrier transport. It follows from calculations of the structure of the Ge valence band under the conditions of size quantization and quantization by a magnetic field (performed in the approximation of an infinite rectangular potential well) that the additional subband can be the second heavy-hole quantum-well subband. Estimates of its population correlate with the experimental manifestations of the participation of the additional subband in galvanomagnetic phenomena.     

The specific contact resistance of Pd2Si contacts on n- and p-Si

The specific contact resistance ρ_c of Al and Pd₂Si contacts has been measured on p- and n-Si substrates of uniform resistivity. The variation of ρ_c with substrate resistivity is described by the following equations:

The specific contact resistance of Al contacts was found to be lower than the values of Pd₂Si contacts on p-Si. Pd₂Si contacts on both n- and p-Si, (111) orientation, become non-ohmic in the resistivity range $\text{0.020?0.10 Ω-}\text{cm}$.The data in this study are not sufficient to distinguish a variation in ρ_c with substrate orientation. Specific contact resistance values of Pd₂Si contacts on $\text{0.005 Ω-}\text{cm}\text{(100) n-}\text{Si}$ and $\text{0.010 Ω-}\text{cm}\text{(100) p-}\text{Si}$ were not significantly different from values expected for the (111) substrates.     

Analysis of the post-breakdown current in HfO2/TaN/TiN gate stack MOSFETs for low applied biases

A thorough analysis of the post-breakdown current-voltage characteristics in HfO₂high-κ/TaN/TiN gate stacks for low positive applied biases reveals an apparent band gap narrowing of the silicon substrate at the very location of the leakage site. This effect may be caused by the migration of gate material through the percolation path during the breakdown runaway. Additionally, the voltage dependence of the current suggests that the origin of the leakage current is thermal generation within the depletion region close to the breakdown spot. A simple analytical model to deal with this current is proposed.