A simple model for scaled MOS transistors that includes field-dependent mobility

A simple MOS model that is suitable for hand calculations, but which includes the effect of normal and tangential electric fields on carrier mobility, is described. This device model is derived from semiphysical models for the field dependence of carrier mobility to accurately predict the effect of reduced dimensions. Fitting parameters for n-channel transistors were extracted. The model is used to examine the effect of reduced mobility at high electric fields on logic switching speed and device transconductance.     

Device to circuit reliability correlations for metal gate/high-k transistors in scaled CMOS technologies

Metal gate/high-k stacks are in CMOS manufacturing since the 45 nm technology node. To meet technology performance and yield targets, gate stack reliability is constantly being challenged. Assessing the associated reliability risk for CMOS products relies on a solid understanding of device to circuit reliability correlations. In this paper we summarize our findings on the correlation between device reliability and circuit degradation and highlight areas for future work to focus on.     

A new quantum mechanical channel mobility model for Si MOSFET's

A new model is presented for the transverse field-dependent mobility in MOSFET's. It is based on the diffuse scattering of electrons at the Si-SiO2interface in the narrow inversion layer, due to the uncertainty principle related momentum, of the electrons in induced quantum levels. Our calculations for unstressed material yield µ ≈ F^-αwith α ≈ 0.67 at high fields. For stressed material α falls to less than 0.2. Combining this channel mobility with bulk phonon scattering gives an excellent fit to a large body of data. Process-induced stress may account for the wide range in µ and α reported in the literature.     

Thermal annealing effect on electrical properties of metal nitride gate electrodes with hafnium oxide gate dielectrics in nano-metric MOS devices

Electrical properties of hafnium oxide (HfO₂) gate dielectric with various metal nitride gate electrodes, i.e., tantalum nitride (TaN), molybdenum nitride (MoN), and tungsten nitride (WN), were studied over a range of HfO₂ thicknesses, e.g., 2.5-10 nm, and post-metal annealing (PMA) temperatures, e.g., 600 °C to 800 °C. The work function of the nitride gate electrode was dependent on the material and the post-metal annealing (PMA) temperature. The scanning transmission electron microscopy technique is used to observe the effect of PMA on the interfacial gate dielectric thickness. After high-temperature annealing, the metal nitride gates were suitable for NMOS. At the same PMA temperature, the oxide-trapped charges increased and the interface state densities decreased with the increase of the HfO₂ thickness for TaN and WN gate electrodes. However, for MoN gate electrode the interface state density is almost independent of film thickness. Therefore, dielectric properties of the HfO₂ high-k film depend not only on the metal nitride gate electrode material but also the post-metal annealing condition as well as the film thickness. During constant voltage stress of the MOS capacitors, an increase in the time-dependent gate leakage current is also observed.     

Compact analytical model for single gate AlInSb/InSb high electron mobility transistors

We have developed a 2D analytical model for the single gate Al In Sb/In Sb HEMT device by solving the Poisson equation using the parabolic approximation method.The developed model analyses the device performance by calculating the parameters such as surface potential,electric field distribution and drain current.The high mobility of the Al In Sb/In Sb quantum makes this HEMT ideal for high frequency,high power applications.The working of the single gate Al In Sb/In Sb HEMT device is studied by considering the variation of gate source voltage,drain source voltage,and channel length under the gate region and temperature.The carrier transport efficiency is improved by uniform electric field along the channel and the peak values near the source and drain regions.The results from the analytical model are compared with that of numerical simulations(TCAD) and a good agreement between them is achieved.     

Threshold voltage model for MOSFETs with high-k gate dielectrics

An analytic threshold voltage model, which can account for the short channel effect and the fringing field effect of sub-100 nm high-k gate dielectric MOSFETs, has been developed. The model considers the two-dimensional (2D) effect both in silicon bulk and in gate dielectric layer. The results of the model are consistent with 2D numerical simulation results     

A microwave model for high electron mobility transistors

In this paper, the authors present a high-frequency model for the high electron mobility transistor (HEMT). The model includes the distributed effects in the channel of the device through two newly developed wave equations in the linear and saturation regimes. The equations are solved taking into account the electric fields along and perpendicular to the flow of the current. The Y and S parameters are derived and the theoretical predictions of the model are compared with the experimental data and shown to be in good agreement over a wide range of frequencies     

A noise model for high electron mobility transistors

A model to explain the noise properties for AlGaAs/GaAs HEMT's, AlGaAs/InGaAs/GaAs pseudomorphic HEMT's (P-HEMT's) and GaAs/AlGaAs inverted HEMT's (I-HEMT's) is presented. The model Is based on a self-consistent solution of Schrodinger and Poisson's equations. The influence of the drain-source current, frequency and device parameters on the minimum noise figure F_min and minimum noise temperature T_min, for different HEMT structures are presented. The study shows that P-HEMT's have a better noise performance than the normal and inverted HEMT's. The present model predicts that a long gate P-HEMT device will exhibit a better noise performance than a conventional HEMT. There is a range of doped epilayer thickness where minimum noise figure is a minimum for pseudomorphic HEMT's which is not observed in conventional and inverted HEMT's. The calculated noise properties are compared with experimental data and the results show excellent agreement for all devices     

Compensation of oxygen defects in La-silicate gate dielectrics for improving effective mobility in high-k/metal gate MOSFET using oxygen annealing process

Oxygen incorporation for compensation of oxygen defects is investigated with La-silicate dielectrics in directly contacted with the Si substrate. The amount of oxygen is controlled by the temperature of annealing in oxygen atmosphere (oxygen annealing) and the thickness of the gate electrode. The positive shift in flatband voltage (V_FB) by oxygen incorporation is an experimental evidence for defects compensation in La-silicate dielectrics. Optimum oxygen annealing provides the V_FB shift toward positive direction without increasing equivalent oxide thickness (EOT). Although the oxygen annealing degrades the interfacial property at La-silicate/Si interface, subsequent forming gas annealing (FGA) can recover the interfacial property. It is experimentally revealed that the positive V_FB shift of La-silicate dielectrics is stable even after subsequent FGA. The supplied oxygen in La-silicate is expected to maintain even after reducing process. Movement of Fermi level toward the Si valence band edge caused by oxygen incorporation is successfully observed by XPS. Moreover, no chemical reaction between La-silicate and Si substrate by oxygen annealing are confirmed from TEM observation and analyses of X-ray photoelectron spectra. It is experimentally demonstrated that effective hole mobility can be improved without increase in EOT by combination of oxygen annealing and FGA.     

超薄EOT高K金属栅结构中串联电阻效应对瞬时击穿特性的影响

本文研究了超薄EOT高K金属栅MOS电容结构的瞬时击穿特性。由于串联电阻效应的影响,MOS电容的瞬时击穿特性的面积依赖关系与理论推导不符。器件中的串联电阻可以通过对IV特性的FN拟合得到。在本文的器件结构中,经验证得到串联电阻主要是由于电极的不对称性引起的扩展电阻。本文提出一种采用串联模型对击穿分布特性进行修正的方法。修正后的瞬时击穿特性与面积的依赖关系符合泊松面积归一规律,这说明对于超薄EOT的高K金属栅结构,瞬时击穿的机制与时变击穿的机制相同,都是由缺陷产生过程导致的击穿过程。     

A new electron-trapping model for the gate insulator of insulated gate field-effect transistors

In the present paper, a new model for electron trapping kinetics in the gate insulator of an insulated gate field-effect transistor (IGFET) is proposed. This model includes a continuous variation of the trapping cross section, σ_o, as a function of the number of filled traps,N _D . The dependency of σ_o is believed to be related physically to the annihilation, or buildup of coulombic charge, which effect has heretofore been neglected in first-order trapping kinetics that describe the entire defect concentration range. The result is that in order to model the experimental data fewer classes of trap cross sections are needed. AsN _D traps fill, the trapping cross section, σ_o, is assumed to be reduced by a factor (1 -N _D /N _T ) whereN _T is the total number of available traps per unit area. This decrease in δ_o is consistent, physically, with a concept of increasing repulsion of carriers as traps fill. This new model also indicates that the number of injected electrons needed to populate 99% of the total traps is about 20 times greater than that predicted by the existing first-order trapping kinetics model. Comparisons between the results of the new model and the first-order trapping kinetics model applied to experimental defect data are also given.     

A low-temperature metal-doping technique for engineering the gate electrode of replacement metal gate CMOS transistors

This work describes a low-temperature metal annealing technique that can be a helpful tool for fabricating the gate electrode of replacement metal gate CMOS transistors. The goal of the technique is to form doped metal (TaSiN, TiSiN, TaCN, TaPN, etc.) to change the work function of the metal gate electrode. The low-temperature doping process was performed in an ambient containing the precursors of the dopants, including silane, phosphine, and carbon-rich organic precursors. Experiments have been conducted to incorporate dopants such as P, C, Si into TaN or TiN. The transistor and C-V data show the resultant doped metals are suitable materials for P- and N-MOSFETs by providing the right metal work function.     

Electrical reliability aspects of HfO2 high-k gate dielectrics with TaN metal gate electrodes under constant voltage stress

The dielectric breakdown property of ultrathin 2.5 and 5.0 nm hafnium oxide (HfO₂) gate dielectric layers with metal nitride (TaN) gate electrodes for metal oxide semiconductor (MOS) structure has been investigated. Reliability studies were performed with constant voltage stressing to verify the processing condition effects (film thicknesses and post metal annealing temperatures) on times to breakdown. The leakage current characteristics are improved with post metal annealing temperatures (PMA) for both 2.5 and 5.0 nm HfO₂ physical thicknesses. However, it is more prominent (2 orders of magnitudes) for 2.5 nm HfO₂ film thickness. The values of oxide-trapped charge density and interface-state density are also improved for 2.5 nm HfO₂ film. The different stages of charge-trapping behaviors, i.e., stress-induced leakage current, soft and hard breakdown mechanisms have been detected. During constant voltage stress of the MOS capacitors, an increase in the time-dependent gate current is observed, followed by the occurrence of several fluctuations. The amplitude of the fluctuations is much larger in the 5.0 nm HfO₂ gate dielectric layer compared to the 2.5 nm HfO₂ layer. After the occurrence of such fluctuations, the current–voltage characteristics exhibited an increased in gate current compared to the fresh (unstressed) devices.     

具有无机有机双绝缘层和修饰电极的薄膜晶体管

研究了有机薄膜晶体管器件.器件是以热生长的SiO2作为有机薄膜晶体管的栅绝缘层,酞菁铜作为有源层的.实验表明采用一种硅烷耦合剂-十八烷基三氯硅烷(OTS)修饰SiO2可以有效地降低栅绝缘层的表面能从而明显提高了器件的性能.器件的场效应迁移率提高了2.5倍、阈值电压降低了3 V、开关电流比从103增加到104.同时我们采用MoO3修饰铝作为器件的源漏电极,形成MoO3/Al双层电极结构.实验表明在同样的栅极电压下,具有MoO3/Al 电极的器件和金电极的器件有着相似的源漏输出电流Ids.结果显示具有OTS/SiO2双绝缘层的及MoO3/Al 电极结构的器件能有效改进有机薄膜晶体管的性能.     

Electrical properties of Ru and RuO2 gate electrodes for Si-PMOSFET with ZrO2 and Zr-silicate dielectrics

In this work, we have studied the electrical and thermal stability of Ru and RuO₂ electrodes on ZrO₂ and Zr-silicate dielectrics. Very low resistivity Ru and rutile stoichiometric RuO₂ films, deposited by reactive sputtering, were evaluated as gate electrodes on ultrathin ZrO₂ and Zr-silicate (∼2.7 nm) films for Si-PMOS devices. Thermal and chemical stability of the electrodes were studied at annealing temperatures up to 800°C in N₂ followed by a forming gas anneal. X-ray diffraction (XRD), transmission electron microscopy (TEM), and x-ray photoelectron spectroscopy (XPS) methods were used to study grain structure and interface reactions. Electrical properties were evaluated using MOS capacitors. The role of oxygen in these dielectrics was studied by comparing equivalent oxide thickness (EOT) changes as a function of annealing temperature for capacitors with ZrO₂ and Zr-silicate dielectrics. For capacitors with Ru and RuO₂ gate electrodes on both ZrO₂ and Zr-silicate, excellent stability of EOT was detected. Flatband voltage and gate current as a function of annealing temperature were also studied. These studies indicate that Ru and RuO₂ are promising gate electrodes for P-MOSFETs.     

Device characteristics of perylene-based transistors and inverters prepared with hydroxyl-free polymer-modified gate dielectrics and thermal post-treatment

Organic field-effect transistors (OFETs) and complementary inverters were produced on the basis of n-type N,N′-dioctyl-3,4,9,10-perylene tetracarboxylic diimide (PTCDI-C8) using the neutral cluster beam deposition (NCBD) method. Significant improvements in surface morphology and crystallinity were observed after the surface modification of SiO₂ gate dielectric layers with hydroxyl-free polymer insulators such as polymethylmethacrylate (PMMA) and cyclic olefin copolymer (COC), and thermal post-treatment. Electric characteristics and operational stability of PTCDI-C8-based OFETs were also clearly enhanced after the surface modification, and in particular, the thermally post-treated OFETs with COC-modified SiO₂ gate dielectrics exhibited a high room-temperature mobility of 0.68 cm²/V s. Two structural types (generic vs. encapsulated) of inverters in top-contact configuration were fabricated by integration of the p-type pentacene and n-type PTCDI-C8 OFETs using COC-modified SiO₂ gate dielectrics. Due to the increased electron mobilities and good coupling between p- and n-type OFETs, hysteresis-free, fast-switching inverters were realized with high gains of ∼20 in the first and third quadrants of voltage transfer characteristics under ambient conditions. The device characteristics of the encapsulated inverters monitored as a function of the time were well maintained with slight degradation.     

A transient model for insulated gate bipolar transistors (IGBTs)

In this paper, we present a physics-based model for the non punch-through (NPT) insulated gate bipolar transistor (IGBT) during transient turn off period. The steady state part of the model is derived from the solution of the ambipolar diffusion equation in the drift region of the NPT IGBT. The transient component of the model is based on the availability of a newly developed expression for the excess carrier concentration in the base. The transient voltage and current are obtained both numerically and analytically from this model. The theoretical predictions of both approaches are compared with experimental data and found to be in good agreement.     

Preparation and properties of thin parylene layers as the gate dielectrics for organic field effect transistors

We report on the fabrication and characterization of parylene C thin layers for organic electronic devices passivation and gate dielectric of organic field effect transistors (OFETs) development. The investigated thin parylene layers were deposited from the vapour phase in thickness ranging from 3 to 800 nm at room temperature. The thickness and surface morphology of parylene layers were characterized by ellipsometry and AFM technique. The quality of parylene structures were analysed by X-ray reflectivity and diffraction as well as micro-Raman spectroscopy. The measurements confirmed perfect homogeneity and structural properties of parylene layers. Two types of pentacene OFETs were prepared on the silicone dioxide and parylene surface with bottom contact structures. The results demonstrated that using parylene, as the gate dielectric layer is an effective method to fabricate OFETs with improved electric characteristics.