A 1-Gb DRAM for file applications

A time-shared offset-canceling sensing scheme, a defective word-line Hi-Z standby scheme, and a flexible multimacro architecture have been developed for 1-Gb DRAM. These circuit technologies have been applied to a 1-Gb DRAM for file applications employing 0.25 μm CMOS process technology, a diagonal bit-line cell, and a two-stage pipeline circuit technique. In this DRAM, a 30% chip size reduction and a 400-MB/s data transfer rate have been achieved. A 100% improvement in yield has been estimated by Monte-Carlo simulation. The 1-Gb DRAM die size is 936 mm². The cell size is 0.54 μm². The operating current is 58 mA at 2 V and 100 MHz     

A cell transistor scalable DRAM array architecture

Presents a new DRAM array architecture for scaled DRAMs. This scheme suppresses the stress bias for memory cell transistors and enables memory cell transistor scaling. In this scheme, the data "1" and data "0" are written to the memory cell in different timing. First, for all selected cells, data "1" is written by boosting wordline (WL) voltage. Second, after pulling down WL voltage to a lowered value, data "0" is written only for data "0" cells. This scheme reduces stress bias for the cell transistor to half of that of the conventional operation. The time loss for data "1" write is eliminated by parallel processing of data "1" write and sense amplifier activation. This scheme realizes fast cycle time of 50 ns. By adopting the proposed scheme, the gate-oxide thickness of the cell transistor is reduced from 5.5 to 3 nm, and the memory cell size is reduced to 87% in 0.13-μm DRAM generation. Moreover, the application of the oxide-stress relaxation technique to all row-path circuits as well as the proposed scheme enables high-performance DRAM with only a thin gate-oxide transistor     

Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM

Circuit techniques for battery-operated DRAMs which cover supply voltages from 1.5 to 3.6 V (universal V_cc), as well as their applications to an experimental 64-Mb DRAM, are presented. The universal-V_cc DRAM concept features a low-voltage (1.5 V) DRAM core and an on-chip power supply unit optimized for the operation of the DRAM. A circuit technique for oxide-stress relaxation is proposed to improve high-voltage sustaining characteristics while only scaled MOSFETs are used in the entire chip. This technique increases sustaining voltage by about 1.5 V compared with conventional circuits and allows scaled MOSFETs to be used for the circuits, which can be operated from an external V_cc of up to 4 V. A two-way power supply scheme is proposed to suppress the internal voltage fluctuation within 10% when the DRAM is operated from external power supply voltages ranging from 1.5 to 3.6 V. An experimental 1.5-3.6-V 64-Mb DRAM is designed based on these techniques and fabricated by using 0.3-μm electron-beam lithography. An almost constant access time of 70 ns is obtained. This indicates that battery operation is a promising target for future DRAMs     

Design of a 128-mb SOI DRAM using the floating body cell (FBC)

A 128-Mb SOI DRAM has been developed featuring the floating body cell (FBC). To keep the cell data state from being degraded by the word-line (WL) disturb due to the charge pumping and to reduce the refresh busy rate, a sense amplifier (S/A) is arranged for every bit-line (BL) and replenishes data "1" cells' bodies with holes which are lost by the disturb in every read and write cycle. The power is reduced by operating the S/As asymmetrically between the selected and the unselected thanks to that the number of holes to be replenished in the unselected S/As for charge pumping is two order of magnitude smaller than that required for writing the data "1". The multi-pair averaging of dummy cells generates a very accurate reference current for distinguishing the data "1" and "0" and a Monte Carlo simulation shows that it achieves a sensing scheme robust enough to realize all good parts of the DRAM with a reasonable amount of redundancy. The cell's feature of quasi-nondestructive read-out is also advantageous for making an SRAM interface of the DRAM or hiding refresh from uses without sacrificing the access time.     

A high-density dual-port memory cell operation and arrayarchitecture for ULSI DRAMs

A high-density dual-port DRAM architecture is proposed. It realizes a two-transistor/one-capacitor (2Tr-1C) dual-port memory cell array with immunity against the array noise caused by the dual-port operation. This architecture, called a truly dual-port (TDP) DRAM, adopts the previously proposed divided/shared bit-line (DSB) sensing scheme in a dual-port 2Tr-1C DRAM array. A 2Tr-1C dual-port memory cell array with folded bit-line sensing operation, which does not increase the number of bit lines of the 1Tr-1C folded bit-line memory array, is realized, thus reducing the memory cell size. This architecture offers a solution to the fundamental limitations in the 2Tr-1C dual-port memory cell, and it is easily applicable to dual-port memory cores in ASIC environments. An analysis of the memory array noise in various dual-port architectures shows a significant improvement with this architecture. Applications to the complete pipelining operation of a DRAM array and a refresh-free DRAM core are also discussed     

A versatile stacked storage capacitor on FLOTOX cell for megabitNVRAM's

A versatile stacked storage capacitor on FLOTOX (SCF) structure is proposed for a megabit nonvolatile DRAM (NV-DRAM) cell that has all the features required for NVRAMs. The SCF structure realizes a 30.94-μm ² NV-DRAM cell with 0.8-μm design rules and allows an innovative flash store/recall (DRAM to EEPROM/EEPROM to DRAM) operation that does not disturb original data in DRAM or EEPROM. This store operation is completed in less than 10 ms. The single cell shows excellent reliability such as store endurance greater than 10⁶ cycles and EEPROM data retention in excess of 10 years under high storage temperatures of 150°C and DRAM write operation at 85°C. The SCF cell has been successfully implemented into the 1 Mb NVRAM     

A submicrometer megabit DRAM process technology using trench capacitors

This paper describes guidelines for developing a 1-4-Mbit DRAM process, and device/process technologies for fabricating an experimental 1-Mbit DRAM. A single transistor cell combined with a trench capacitor and on-chip ECC technologies has the potential to realize a cell size of 10 µm²without degrading soft error immunity. A depletion trench capacitor, submicrometer n-well CMOS process, Mo-poly gate, and submicrometer pattern formation technologies are developed, and an experimental 1-Mbit DRAM with a cell size of 20 µm²is successfully developed by using these technologies.     

A 2.5-V 2.0-Gbyte/s 288-Mb packet-based DRAM with enhanced cellefficiency and noise immunity

A 2.5-V 288-Mb packet-based DRAM with 32 banks and 18-DQ organization architecture achieving a peak bandwidth of 2.0-GB/s at V _DD=2.25 V and T=100°C has been developed using (1) an area- and performance-efficient chip architecture with a mixture of high-speed interface circuits with DRAM peripheral circuits to increase cell efficiency; (2) a multilevel controlled bitline equalizing scheme and a distributed sense amplifier driving scheme to enhance DRAM core timing margin while increasing the number of cells per wordline for cell efficiency over the previous subwordline driving scheme; (3) a flexible column redundancy scheme with multiple fuse boxes instead of excessive spare memory cell arrays for 143 internal I/O architecture; and (4) optimized I/O circuits and pin parasitic design including pad and package to maximize the operating frequency     

A four megabit Dynamic Systolic Associative Memory chip

A Dynamic Random Access Memory (DRAM) chip is to be modified to associatively search data in it as it is being refreshed in the chip and to communicate in a linear systolic array. In a preliminary logic design of a (1024×4096) associative memory chip based on a 4 Mbit DRAM, the 6 transistors per sense amplifier in a DRAM are expanded by 9 transistors per sense amplifier in the modified chip. The chip size is only slightly increased, and it is manufactured using the same processes, in the same plant, as a DRAM chip; thus should cost about the same as a DRAM. A large array of such modified DRAMs could store a terabit database and search all of it every 60 microseconds. Bit pattern searching and search-rewrite algorithms could be economically performed over very large amounts of data. The concepts and the design of the simple modified DRAM will be discussed in the paper.     

A 1-Gb SDRAM with ground-level precharged bit line and nonboosted2.1-V word line

This paper describes the key technologies used in a 1-Gb synchronous DRAM. This DRAM was developed according to a new cell-operating concept in which a ground-level (V_ss) precharged bit line with a negative word-line reset scheme enables a nonboosted 2.1-V word-line architecture. Total power consumption is less than that of the conventional half-V_cc precharged bit-line scheme. We also propose a vernier-type, high-accuracy delay-locked-loop circuit realizing ±20-ps quantization errors for clock recovery and skew elimination     

一种新型高速嵌入式动态随机存储器

基于二维器件模拟工具,研究了一种采用栅控二极管作为写操作单元的新型平面无电容动态随机存储器.该器件由一个n型浮栅MOSFET和一个栅控二极管组成.MOSFET的p型掺杂多晶硅浮栅作为栅控二极管的p型掺杂区,同时也是电荷存储单元.写“0”操作通过正向偏置二极管实现,而写“1”操作通过反向偏置二极管,同时在控制栅上加负电压使栅控二极管工作为隧穿场效应晶体管(Tunneling FET)来实现.由于正向偏置二极管和隧穿晶体管开启时接近1μA/μm的电流密度,实现了高速写操作过程,而且该器件的制造工艺与闪烁存储器和逻辑器件的制造兼容,因此适合在片上系统(SOC)中作为嵌入式动态随机存储器使用.     

2.4F2 memory cell technology with stacked-surroundinggate transistor (S-SGT) DRAM

This paper proposes 2.4F² memory cell technology with stacked-surrounding gate transistor (S-SGT) DRAM. One unit of the S-SGT DRAM is formed by stacking several SGT-type cells in series vertically. The SGT-type cell itself arranges gate, source, drain and plate on a silicon pillar vertically. Both gate and plate electrode surround the silicon pillar. Subsequently applied trench etching and sidewall spacer formation during S-SGT DRAM formation causes a step-like silicon pillar structure. Due to these steps, gate, plate and diffusion layer in one S-SGT DRAM unit are fabricated vertically by a self-aligned process. The cell size dependence of the self-aligned-type S-SGT DRAM was analyzed with regard to the above step widths and the number of cells in one unit. As a result, the cell design for minimizing the cell size of this device has been formulated. By using the proposed cell design, it is demonstrated by process simulation that the S-SGT DRAM in 0.5 μm design rule can achieve a cell size of 2.4F², which is half of the cell size of a conventional SGT DRAM cell (4.8F²). Therefore, the S-SGT DRAM is a promising candidate for future ultra high density DRAMs     

A reliable 1-Mbit DRAM with a multi-bit-test mode

A single 50V supply 1-Mb DRAM using a half V/SUB cc/ biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide world-line technology.     

A Submicrometer Megabit DRAM Process Technology Using Trench Capacitors

This paper describes guidelines for developing a 1-4-Mbit DRAM process, and device/process technologies for fabricating an experimental 1-Mbit DRAM. A single transistor cell combined with a trench capacitor and on-chip ECC technologies has the potential to realize a cell size of 10 /spl mu/m/sup 2/ without degrading soft error immunity. A depletion trench capacitor, submicrometer n-well CMOS process, Mo-poly gate, and sub-micrometer pattern formation technologies are developed, and an experimental 1-Mbit DRAM with a cell size of 20 /spl mu/m/sup 2/ is successfully developed by using these technologies.     

On-wafer BIST of a 200-Gb/s failed-bit search for 1-Gb DRAM

An on-wafer built-in self-test (BIST) technique has been developed to implement a 200 Gb/s failed-bit search for a 1-Gb DRAM. The BIST circuits include a 4-kb very-long word bus and an on-wafer test management unit to probe DRAM arrays and compress test results. The 1-Gb DRAM is fabricated as a test device using a 0.16-μm CMOS technology. As a result, the BIST reduces the wafer test time to less than 1/100 that of bit-by-bit testing     

Trench transistor DRAM cell

A new one-transistor DRAM cell with both the transistor and the capacitor fabricated on the trench sidewalls is described. With the signal stored on the polysilicon node surrounded by oxide, the cell is expected to have a high alpha particle immunity. The cell occupies only 9 µm²using 1-µm design rules. This cell size is sufficiently small to enable a 4-Mbit DRAM of reasonable chip size with these design rules, and possesses further scalability for 16-Mbit DRAM's.     

New three-dimensional memory array architecture for futureultrahigh-density DRAM

In this paper, a three-dimensional (3-D) memory array architecture is proposed. This new architecture is realized by stacking several cells in series vertically on each cell located in a two-dimensional array matrix. Therefore, this memory array architecture has a conventional horizontal row and column address and new vertical row address. The total bit-line capacitance of this proposed architecture's DRAM is suppressed to 37% of normal DRAM when one bit-line has 1-Kbit cells and the same design rules are used. Moreover, an array area of 1-Mbit DRAM using the proposed architecture is reduced to 11.5% of normal DRAM using the same design rules. This proposed architecture's DRAM can realize small bit-line capacitance and small array area simultaneously. Therefore, this proposed 3-D memory array architecture is suitable for future ultrahigh-density DRAM     

The impact of data-line interference noise on DRAM scaling

A kind of data-line (DL) interference noise in a scaled DRAM cell array is found and studied through analysis. The dynamic behavior of cell arrays due to sense-amplifier operation is derived analytically. Analysis shows that the amount of interference noise is more than three times larger than expected from simple data-line coupling. A novel experimental technique for precise noise determination is developed to verify the analysis. Analytical results are in good agreement with the experimental data. It is found that the interference noise plays a dominant role in determining the operating margin of the DRAM and that a novel process or a cell array architecture for minimizing the interference noise is indispensable in 16-Mb DRAM and beyond     

A 180 MHz 0.8 μm BiCMOS modular memory family of DRAM andmultiport SRAM

A family of modular memories with a built-in self-test interface designed using a synchronous self-timed architecture is described. This approach is ideally suited to modular memories embedded within synchronous systems due to its simple boundary specification, excellent speed/power performance, and ease of modelling. The basic port design is self-contained and extensible to any number of ports sharing access to a common-core cell array. The same design has been used to implement modular one-, two-, and four-part SRAMs and a one-port DRAM based on a four-transistor (4-T) cell. The latter provides a 45% core cell density improvement over the one-port SRAM. Nominal access and cycle times of 5.5 ns for 64 kb blocks have been shown for a 0.8 μm BiCMOS process with no memory process enhancements. System operation at 100 MHz has been demonstrated on a broadband time-switch chip containing 96 kb of two-port SRAM     

Tunneling-based SRAM

This paper describes a new high-density low-power circuit approach for implementing static random access memory (SRAM) using low current density resonant tunneling diodes (RTDs). After an overview of semiconductor random access memory architecture and technology, the concept of tunneling-based SRAM (TSRAM) is introduced. Experimental results for a compound semiconductor 1-bit 50-nW TSRAM gain cell using low current density (~1 A/cm²) RTDs and low-leakage heterostructure field effect transistors are presented. We describe a one-transistor TSRAM cell which could convert silicon dynamic RAM (DRAM) to ultradense SRAM if an ultralow current density (~1 μA/cm² ) silicon bistable device is developed. Finally, we present experimental and simulation results for a TSRAM cell using multipeaked I-V curve devices and a multivalued word line. This approach aims at increasing storage density through vertical integration of bistable devices such as RTD's