An analytical back gate bias dependent threshold voltage model forSiGe-channel ultrathin SOI PMOS devices

An analytical threshold voltage model for SiGe-channel ultrathin SOI PMOS devices is presented. As confirmed by the PISCES simulation results, the analytical model provides a good prediction on the threshold voltage. According to the analytical-formula, depending on the back gate bias, the SiGe-channel SOI PMOS device may have a conduction channel at the top or the bottom of the SiGe channel or at the top of the field oxide     

Modeling the effect of back gate bias on the subthreshold behavior of a SiGe-channel SOI PMOS device

This paper reports on a simulation study on the back gate bias effect on the subthreshold behavior of a SiGe-channel SOI PMOS device using a device simulator. With a SiGe channel, the SOI PMOS device shows a smaller back gate bias effect as compared to the one without it.     

基于二维电势分布的一种新型复合多晶硅栅LDMOS阈值电压模型

本文提出了一种新型的复合多晶硅栅LDMOS结构.该结构引入栅工程的概念,将LDMOST的栅分为n型多晶硅栅和p型多晶硅栅两部分,从而提高器件电流驱动能力,抑制SCEs(short channel effects )和DIBL(drain-induced barrier lowering).通过求解二维泊松方程建立了复合多晶硅栅LDMOST的二维阈值电压解析模型.模型考虑了LDMOS沟道杂质浓度分布和复合栅功函数差的共同影响,具有较高的精度.与MEDICI数值模拟结果比较后,模型得以验证.     

TiN栅薄膜全耗尽SOI CMOS器件

制备并研究了TiN栅薄膜全耗尽SOI CMOS器件,并对其关键工艺进行了详细阐述.相对于双多晶硅栅器件,在不改变阈值电压的前提下,可以减小nMOS和pMOS的沟道掺杂浓度,进而提高迁移率.由于TiN的功函数处于中间禁带,在几乎相同的调整阈值注入剂量下,可以得到对称的阈值电压.当顶层硅膜厚度减小时,可以改善短沟道效应.     

W/TiN Gate Thin-Film Fully-Depleted SOI CMOS Devices

TiN gate thin-film fully-depleted SOI CMOS devices are fabricated and discussed.Key process technologies are demonstrated.Compared with the dual polysilicon gate devices,the channel doping concentration of nMOS and pMOS can be reduced without changing threshold voltage (VT)，which enhances the mobility.Symmetrical VT is achieved by nearly the same VT implant dose because of the near mid-gap workfunction of TiN gate.The SCE effect is improved when the thin-film thickness is reduced.     

Threshold voltage roll-up/roll-off characteristic control insub-0.2-μm single workfunction gate CMOS for high-performance DRAMapplications

Threshold voltage (V_t) roll-off/roll-up control is a key issue to achieve high-performance sub-0.2-μm single workfunction gate CMOS devices for high-speed DRAM applications. It is experimentally confirmed that a combination of well RTA and N₂ implant prior to gate oxidation is important to reduce V_t roll-up characteristics both in nFET and pFET. Optimization of RTA conditions after source/drain (S/D) implant is also discussed as a means of improving V_t roll-off characteristics. Finally, the impact of halo implant on V_t variation in sub-0.2-μm buried channel pFETs is discussed. It is found that halo profile control is necessary for tight V_t variation in sub-0.2-μm single workfunction gate pFET     

Optimizing Schottky S/D offset for 25-nm dual-gate CMOS performance

For the first time, mixed mode simulation is used to optimize the design of ultrathin-body dual-gate metal source/drain 25-nm CMOS, showing an advantage for source/drain-to-gate underlap, rather than overlap. The effect of source/drain workfunction and silicon thickness on the optimal underlap, and on the resulting circuit speed, is examined. A substantial performance advantage versus doped source/drain is demonstrated.     

High-mobility modulation-doped SiGe-channel p-MOSFETs

A novel subsurface SiGe-channel p-MOSFET is demonstrated in which modulation doping is used to control the threshold voltage without degrading the channel mobility. A novel device design consisting of a graded SiGe channel, an n⁺ polysilicon gate, and p⁺ modulation doping is used. A boron-doped layer is located underneath the graded and undoped SiGe channel to minimize process sensitivity and maximize transconductance. Low-field hole mobilities of 220 cm²/V-s at 300 K and 980 cm²/V-s at 82 K were achieved in functional submicrometer p-MOSFETs     

A threshold-voltage model of SiGe-channel pMOSFET without Si cap layer

An analytical model on the threshold voltage of SiGe-channel pMOSFET with high-κ gate dielectric is developed by solving the Poisson’s equation. Energy-band offset induced by SiGe strained layer, short-channel effect and drain-induced barrier lowering effect are taken into account in the model. To evaluate the validity of the model, simulated results are compared with experimental data, and good agreements are obtained. This model can be used for the design of SiGe-channel pMOSFET, thus determining its optimal parameters.     

A novel design approach of charge plasma tunnel FET for radio frequency applications

In this paper, the impact of extra electron source (EES) and dual metal gate engineering on conventional charge plasma TFET (CP-TFET) have been done for improving DC and analog/RF parameters. CP-TFET structure is upgraded to double source CP-TFET (DS-CP-TFET) by placing an EES below the source/channel junction for enhancing the device performance in terms of driving current and RF figures of merit (FOMs). But, in spite of these pros, the approach is having cons of higher leakage current similar to MOSFET and negative conductance (inherent nature of TFET). Both the issues have been resolved in the double source dual gate CP-TFET (DS-DG-CP-TFET) by gate workfunction engineering and drain underlapping respectively. Additionally, for getting the optimum performance of DS-DG-CP-TFET, the device sensitivity has been investigated in terms of position of EES, length of drain electrode and workfunction of gate electrode 1 (GE1).     

TCAD Assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and Its Multilayered Gate Architecture—Part I: Hot-Carrier-Reliability Evaluation

This paper discusses a hot-carrier-reliability assessment, using ATLAS device simulation software, of a gate electrode workfunction engineered recessed channel (GEWE-RC) MOSFET involving an RC and GEWE design integrated onto a conventional MOSFET. Furthermore, the impact of gate stack architecture and structural design parameters, such as gate length, negative junction depth, substrate doping (NA), gate metal workfunction, substrate bias, drain bias, and gate oxide permittivity on the device behavior of GEWE-RC MOSFET, is studied in terms of its hot-carrier behavior in Part I. Part II focuses on the analog performance and large signal performance metrics evaluation in terms of linearity metrics, intermodulation distortion, device efficiency and speed-to-power dissipation design parameters, and the impact of gate stack architecture and structural design parameters on the device reliability. TCAD simulations in Part I reveal the reduction in hot-carrier-reliability metrics such as conduction band offset, electron velocity, electron temperature, hot-electron-injected gate current, and impact-ionization substrate current. This paper thus optimizes and predicts the feasibility of a novel design, i.e., GEWE-RC MOSFET for high-performance applications where device and hot-carrier reliability is a major concern.     

Threshold voltage control in NiSi-gated MOSFETs through SIIS

Complete gate silicidation has recently been demonstrated as an excellent technique for the integration of metal gates into MOSFETs. From the various silicide gate materials NiSi has been shown to be the most scalable. In this paper, a versatile method for controlling the workfunction of an NiSi gate is presented. This method relies on doping the poly-Si with various impurities prior to silicidation. The effect of various impurities including B, P, As, Sb, In, and Al is described. The segregation of the impurities from the poly-Si to the silicide interface during the silicidation step is found to cause the NiSi workfunction shift. The effect of the segregated impurities on gate capacitance, mobility, local workfunction stability, and adhesion is studied.     

Fabrication of metal gated FinFETs through complete gate silicidation with Ni

Metal-gate FinFETs were fabricated using complete gate silicidation with Ni, combining the advantages of metal-gate and double-gate transistors. NiSi-gate workfunction control is demonstrated using silicide induced impurity segregation of As, P, and B over a range of 400 mV. High device performance is achieved by integrating the NiSi metal gate with an epitaxial raised source/drain, silicided separately with CoSi/sub 2/. Process considerations for this dual silicide integration scheme are discussed. Poly-Si gated FinFETs are also fabricated and used as references for workfunction and transconductance.     

Extremely scaled silicon nano-CMOS devices

Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator substrates have been demonstrated down to 15-nm gate lengths. We have also introduced the FinFET, a double-gate device structure that is relatively simple to fabricate and can be scaled to gate lengths below 10 nm. In this paper, some of the key elements of these technologies are described, including sublithographic patterning, the effects of crystal orientation and roughness on carrier mobility, gate work function engineering, circuit performance, and sensitivity to process-induced variations.     

Band-Structure Effects on the Performance of III–V Ultrathin-Body SOI MOSFETs

This paper examines the impact of band structure on deeply scaled III-V devices by using a self-consistent 20-band -SO semiempirical atomistic tight-binding model. The density of states and the ballistic transport for both GaAs and InAs ultrathin-body n-MOSFETs are calculated and compared with the commonly used bulk effective mass approximation, including all the valleys (, , and ). Our results show that for III-V semiconductors under strong quantum confinement, the conduction band nonparabolicity affects the confinement effective masses and, therefore, changes the relative importance of different valleys. A parabolic effective mass model with bulk effective masses fails to capture these effects and leads to significant errors, and therefore, a rigorous treatment of the full band structure is required.     

A novel hetero-material gate (HMG) MOSFET for deep-submicron ULSItechnology

A novel hetero-material gate MOSFET intended for integration into the existing deep-submicron silicon technology is proposed and simulated. It is shown that by adding a layer of material with a larger workfunction to the source side of the gate, short-channel effects can be greatly suppressed without degrading the driving ability. The threshold voltage roll-off can be compensated and tuned by controlling the length of this second gate. The new structure has great potential in breaking the barrier of deep-suhmicron MOSFET's scaling beyond 0.1 μm technologies     

Extraction of gate-edge workfunction of metal gate and its impact on scaled MOSFETs

The gate-edge properties of a metal/high-k gate stack are of crucial importance, but they have not been quantitatively investigated. In this paper, we have proposed a new method for extracting the local workfunction of the gate electrode by using a sideways overturned stack. We revealed that the TaSiN workfunction on their 10-nm long gate-edges shifted for 0.1 eV after a 1000 °C annealing. Based on these parameters, we simulated the impact of the gate-edge metamorphoses (GEM) and found that GEM increased the threshold voltage for scaled devices with a 60-nm long or shorter gate without suppressing a short-channel effect.     

The Effect of an Yttrium Interlayer on a Ni Germanided Metal Gate Workfunction in SiO2/HfO2

In this letter, the tuning of a nickel fully germanided metal gate effective workfunction via a hyperthin yttrium (Y) interlayer at the bottom of the metal electrode was demonstrated on both SiO₂ and HfO₂. By varying the Y interlayer thickness from 0 to 9.6 nm, a full range of workfunction tuning from 5.11 to 3.65 eV has been achieved on NiGeY/SiO₂ stacks. It was also found that the chemical potential of the material that is adjacent to the gate electrode/gate insulator plays an important role in the determination of the effective workfunction. This work-function tuning window was observed to decrease to a range of 5.08-4.25 eV on NiGeY/HfO₂ stacks.     

Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET

The novel features of a fully depleted (FD) dual-material gate (DMG) silicon-on-insulator (SOI) MOSFET are explored theoretically and compared with those of a compatible SOI MOSFET. The two-dimensional numerical simulation studies demonstrate the novel features as threshold voltage roll-up and simultaneous transconductance enhancement and suppression of short-channel effects offered by the FD DMG SOI MOSFET. Moreover, these unique features can be controlled by engineering the workfunction and length of the gate material. This work illustrates the benefits of high-performance FD DMG SOI MOS devices over their single material gate counterparts and provides an incentive for further experimental exploration.     

SiGe-channel heterojunction p-MOSFET's

The advances in the growth of pseudomorphic silicon-germanium epitaxial layers combined with the strong need for high-speed complementary circuits have led to increased interest in silicon-based heterojunction field-effect transistors. Metal-oxide-semiconductor field-effect transistors (MOSFET's) with SiGe channels are guided by different design rules than state-of-the-art silicon MOSFET's. The selection of the transistor gate material, the optimization of the silicon-germanium channel profile, the method of threshold voltage adjustment, and the silicon-cap and gate-oxide thickness sensitivities are the critical design parameters for the p-channel SiGe MOSFET. Two-dimensional numerical modeling demonstrates that n⁺ polysilicon-gate SiGe p-MOSFET's have acceptable short-channel behavior at 0.20 μm channel lengths and are preferable to p⁺ polysilicon-gate p-MOSFET's for 2.5 V operation. Experimental results of n⁺-gate modulation-doped SiGe p-MOSFET's illustrate the importance of the optimization of the SiGe-channel profile. When a graded SiGe channel is used, hole mobilities as high as 220 cm² /V.s at 300 K and 980 cm²/V.s at 82 K are obtained