10 GHz dual-conversion low-IF downconverter with microwave and analogue quadrature generators

A 10 GHz dual-conversion low-IF downconverter using 0.18-mum CMOS technology is demonstrated. The high-frequency quadrature RF and LO₁ signals are generated by broadside-coupled quadrature couplers while a two-section polyphase filter is utilised for the low-frequency LO₂ quadrature signal generation. As a result, the demonstrated downconverter achieves a conversion gain of 7 dB, IP_{1 dB} of -16 dBm, IIP₃ of -5 dBm and noise figure of 26 dB at a 1.8 V supply. The image-rejection ratio of the first/second image signal is 33/42 dB for IF frequency ranging from 10 to 60 MHz, respectively.     

Calibration study of dual-band Weaver–Hartley receiver architecture

This paper presents a calibration study of dual-band image rejection receiver based on combined Weaver–Hartley architecture, with improved image rejection of first and second image signals. The system implementation is based on dual-band WLAN 802.11 a/g. When the desired signal is at 5.7-GHz band, the 2.4-GHz band becomes the first image signal and vice versa. The output IF frequency is at 30-MHz. The detection of the gain and phase mismatches is based on modeling, extraction of related error signals and correcting them in closed loop. Moreover, we demonstrate an open loop technique to reach the phase and gain correction signals. The correction signals can be digitally stored and applied as digital trimming control on the LO signals. Simulation showed close to 60 dB of image rejection ratio for the first image signal. Second image signal is rejected by a 4-section poly-phase filter.     

A 5.2-GHz GaInP/GaAs HBT double-quadrature downconverter with polyphase filters for 40-dB image rejection

A 5.2-GHz 11-dB gain, IP/sub 1 dB/=-17 dBm and IIP/sub 3/=-10 dBm double-quadrature Gilbert downconversion mixer with polyphase filters is demonstrated by using GaInP/GaAs heterojunction bipolar transistor (HBT) technology. The image rejection ratio is better than 40 dB when LO=5.17 GHz and intermediate frequency (IF) is in the range of 15 MHz to 40 MHz. The Gilbert downconverter has four-stage RC-CR IF polyphase filters for image rejection. Polyphase filters are also used to generate local (LO) and radio frequency (RF) quadrature signals around 5 GHz in the double-quadrature downconverter because GaAs has accurate thin film resistors and the low parasitic semi-insulating substrate.     

Effect of Phase Mismatch on Image Rejection in Weaver Architecture

In a radio frequency receiver, image signals degrade the sensitivity of the receiver for receiving desired signals. This letter analyzes the effect of phase mismatch on image rejection in the Weaver architecture, which has been proposed to reject image signals. Weaver architecture requires the phase difference between the I signal and Q signal of the first and second local oscillators (LOs) to be 90deg. However, the realization of accurate 90deg phase shifters is very difficult. It is found here that an accurate 90deg phase shifter is not essential in Weaver architecture. Instead, by making the phase mismatch between the I and Q signals of the first LO be equal to that of the second LO, image rejection can be performed, being insensitive to the phase mismatch. The reason for this is mathematically analyzed and simulation results are presented     

Highly integrated 60 GHz transmitter and receiver MMICs in a GaAs pHEMT technology

Highly integrated transmitter and receiver MMICs have been designed in a commercial 0.15 /spl mu/m, 88 GHz f/sub T//183 GHz f/sub MAX/ GaAs pHEMT MMIC process and characterized on both chip and system level. These chips show the highest level of integration yet presented in the 60 GHz band and are true multipurpose front-end designs. The system operates with an LO signal in the range 7-8 GHz. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO chain, resulting in an IF center frequency of 2.5 GHz. Although the chips are inherently multipurpose designs, they are especially suitable for high-speed wireless data transmission due to their very broadband IF characteristics. The single-chip transmitter MMIC consists of a balanced resistive mixer with an integrated ultra-wideband IF balun, a three-stage power amplifier, and the X8 LO chain. The X8 is a multifunction design by itself consisting of a quadrupler, a feedback amplifier, a doubler, and a buffer amplifier. The transmitter chip delivers 3.7/spl plusmn/1.5 dBm over the RF frequency range of 54-61 GHz with a peak output power of 5.2 dBm at 57 GHz. The single-chip receiver MMIC contains a three-stage low-noise amplifier, an image reject mixer with an integrated ultra-wideband IF hybrid and the same X8 as used in the transmitter chip. The receiver chip has 7.1/spl plusmn/1.5 dB gain between 55 and 63 GHz, more than 20 dB of image rejection ratio between 59.5 and 64.5 GHz, 10.5 dB of noise figure, and -11 dBm of input-referred third-order intercept point (IIP3).     

Design of Weaver topology

A novel design based on Weaver topology is proposed. Studies showed that the image-rejection ratio (IRR) performance of the design is insensitive to the phase errors of the LO₁ and the IRR against gain mismatch is inherently about 6 dB superior to the conventional Weaver topology. The design greatly increases the practicality of the Weaver receiver     

A 5.2-GHz CMOS receiver with 62-dB image rejection

A 5.2-GHz CMOS receiver employs a double downconversion heterodyne architecture with a local oscillator frequency of 2.6 GHz and applies offset cancellation to the baseband amplifiers. Placing the image around the zero frequency, the receiver achieves an image rejection of 62 dB with no external components while minimizing the flicker noise upconversion in the first mixing operation. Realized in a 0.25-μm digital CMOS technology, the circuit exhibits a noise figure of 6.4 dB, an IP₃ of -15 dBm, and a voltage conversion gain of 43 dB, while draining 29 mW from a 2.5-V supply     

A 1.9-GHz silicon receiver with monolithic image filtering

A 1.9-GHz fully monolithic silicon superheterodyne receiver front-end is presented; it consists of a low noise amplifier (LNA), a tunable image reject filter, and a Gilbert cell mixer integrated in one die. The receiver was designed to operate with a 1.9-GHz RF and a 2.2-GHz local oscillator (LO) for a 300-MHz IF. Two chip versions were fabricated on two different fabrication runs using a 0.5-μm bipolar technology with 25 GHz transit frequency (f_T). Measured performance for the receiver front-end version 1, packaged and without input matching, was: conversion gain 33.5 dB, noise figure 4.9 dB, input IP3 -28 dBm, image rejection 53 dB (tuned to reject a 2.5-GHz image frequency), and 15.9 mA current consumption at +3 V. The image rejection was tunable from 2.4-2.63 GHz by means of an on-chip varactor. Version 2 had increased mixer degeneration for improved linearity. Its measured performance for the packaged receiver with its input matched to 50 Ω was: conversion gain 24 dB, noise figure 4.8 dB, input IP3 -19 dBm, and 65 dB image rejection for a 2.5-GHz image with an image tuning range from 2.34-2.55 GHz     

2.4/5.7-GHz CMOS Dual-Band Low-IF Architecture Using Weaver–Hartley Image-Rejection Techniques

A 2.4/5.7-GHz dual-band Weaver–Hartley architecture, using 0.18-$mu{hbox{m}}$ CMOS technology, is demonstrated in this paper. The 2.4-GHz signal is set to be the image signal when the desired signal is at 5.7 GHz, and vice versa. Since the Weaver and Hartley systems are combined into this architecture, the demonstrated architecture rejects not only the first image signal, but also the secondary image signal. The image-rejection ratios of the first image signal and the secondary image signal are better than 40 and 46 dB, respectively. In this paper, a diagrammatic explanation is employed to obtain the image-rejection mechanisms of the Weaver–Hartley architecture.      

A 22-GHz-band low-noise down-converter for satellite broadcastreceivers

A simple low-cost and high-performance 22 GHz band down-converter developed for a direct-to-home satellite broadcasting system is discussed. The down-converter consists of a low-noise high electron mobility transistor (HEMT) preamplifier, an image recovery mixer with a particular structure using dielectric resonator filters, a 21.4 GHz GaAs FET oscillator stabilized by a dielectric resonator, and an IF amplifier. These components are fully integrating using microwave integrated circuit technology into a small size. A total noise figure of less than 2.8 dB is obtained over the 22.5-23.0 GHz frequency range. The local oscillator achieves a frequency variation of less than 600 kHz_p-p over a temperature range of -20° to +60°C     

A 5.4 mW/0.07 mm$^{2}$ 2.4 GHz Front-End Receiver in 90 nm CMOS for IEEE 802.15.4 WPAN Standard

An integrated 2.4 GHz CMOS receiver front-end according to the IEEE 802.15.4 standard is presented in this paper. It integrates the overall RF part, from the balun up to the first stage of the channel filter, as well as the cells for the LO signal conditioning. The proposed architecture is based on a 6 MHz low-IF topology, which uses an inductorless LNA and a new clocking scheme for driving a passive mixer. When integrated in a 90 nm CMOS technology, the receiver front-end exhibits an area of only 0.07 mm², or 0.23 mm² when including an input integrated balun. The overall chip consumes 4 mA from a single 1.35 V supply voltage and it achieves a 35 dB conversion gain from input power in dBm to output voltage in dBvpk, a 7.5 dB NF value, -10 dBm of IIP3 and more than 32 dB of image rejection.     

应用于太赫兹源信号实现的宽带四倍频链路设计

由于集成电路工艺截止频率Ft的限制,直接通过振荡器获取的太赫兹信号源具有输出功率低、带宽较窄等问题。针对该问题,提出一种可实现高性能太赫兹源的宽带倍频链路设计。对比了传统push-push技术与改进的跨导增强push-push技术,并提出将跨导增强push-push技术运用到倍频器中,提高了倍频链路的倍频增益;在链路级间采用具有幅度与相位纠正功能的新型有源巴伦结构,进一步提高了倍频器的倍频增益与谐波抑制性能。仿真结果表明,倍频链路可实现带宽为210~256 GHz,饱和输出功率为-0.5 dBm,峰值倍频增益为-0.55 dB的太赫兹信号源,链路的总直流功耗仅为30.6 mW。     

A 2.45/5.2 GHz Image Rejection Mixer With New Dual-Band Active Notch Filter

A 2.45/5.2 GHz dual-band Gilbert downconversion mixer with image rejection function is presented, which is implemented using the 0.18 $mu$m CMOS technology. The proposed differential dual-band image rejection circuitry is employed for the 2.45/5.2 GHz WLAN application to effectively diminish the dc power consumption and complexity of circuit design compared to the traditional Hartley or Weaver architectures. Moreover, the cross-connected pair consisted of NMOS and PMOS transistors in the proposed notch filter will further ameliorate the image rejection capability. The IC prototype achieves conversion gain of $10.5/11$ dB, IIP3 of ${-}4.9/-5.2$ dBm for ${rm RF}= 2.45/5.2$ GHz and ${rm IF}=500$ MHz while the image rejection ratio is better than 36/45 dB in the whole operation bandwidth.      

A 90 nm CMOS 15/60 GHz frequency quadrupler

The design and characterisation of a 60?GHz frequency quadrupler implemented in a conventional 90?nm CMOS technology is presented. The proposed fully differential frequency quadrupler is formed by properly combining a 15?GHz to 30?GHz doubler, two 30?GHz amplifiers, a polyphase filter, a 30 to 60?GHz doubler and two 60?GHz amplifiers. The proposed design is based on a differential architecture and achieves enhanced characteristics in terms of harmonics rejection, bandwidth, power consumption and die area. Conversion loss of 9.3?dBm at 60?GHz with 1.1?dBm input power is achieved. The 3?dB bandwidth lies between 51.5?GHz and 61?GHz, while the total current consumption is 100?mA from a 1.2?V supply voltage for the fully balanced implementation.     

Dual-Band Adjustable and Reactive I/Q Generator With Constant Resistance for Down- and Up-Converters

Adjustable and reactive in-phase/quadrature (I/Q) generators with constant resistance are proposed for the first time in this paper with the properties of low loss, dual-band implementation, and high quadrature accuracy. The quadrature phase property and input matching of the I/Q generator can be achieved at all frequencies simultaneously by the constant-resistance I/Q generator. However, the magnitude balance of the dual-band I/Q generator is achieved at two designed frequencies. A 2.4/5.2-GHz I/Q down-converter and a 2.4/5.7-GHz single-sideband up-converter are fabricated using 0.35- $mu{hbox{m}}$ SiGe BiCMOS technology. The dual-band I/Q generator along with two single-to-differential amplifiers is integrated to provide differential quadrature local oscillator signals for dual-band mixers. The magnitude imbalance and phase error between the I and Q channels of the down-converter are $≪$1% and $≪{hbox{1}}^{circ}$, respectively, while the maximum sideband rejection ratio of the up-converter is up to 50 dB. Additionally, the operation bandwidth (sideband rejection ratio $> $30 dB) is 200 MHz at 2.4 GHz and 720 MHz at 5.7 GHz.      

10-GHz Highly Symmetrical Sub-Harmonic Gilbert Mixer Using GaInP/GaAs HBT Technology

A 10-GHz sub-harmonic Gilbert mixer is demonstrated using GaInP/GaAs hetero-junction bipolar transistor technology. The local oscillator (LO) signal time-delay path in the sub-harmonic LO stage is compensated using the fully symmetrical stacked-LO doubler; therefore, the balance of the sub-harmonic LO stage, the radio frequency to intermediate frequency isolation, and IIP₂ are improved. The demonstrated 10-GHz sub-harmonic mixer achieves 10 dB conversion gain, IP_1dB of -12 dBm, IIP₃ of 2 dBm and IIP₂ of 33 dBm     

5.7 GHz Gilbert I/Q Downconverter Integrated With a Passive LO Quadrature Generator and an RF Marchand Balun

A 5.7 GHz downconversion mixer is demonstrated in this letter using 0.35 mum SiGe BiCMOS technology. A quarter-wavelength coupled line and two center-tapped transformers are utilized to generate differential quadrature LO signals. A miniaturized Marchand balun is placed before the common-base-configured RF input stage of each Gilbert mixer to generate balanced RF signals. All the reactive passive elements are placed directly on the standard silicon substrate. The 5.7 GHz downconverter achieves 7 dB conversion gain, 26dBm _1dB, and 18dBm IIP₃ at the power consumption of 3.875 mW and 2.5 V supply voltage.     

SSB MMIC mixer with subharmonic LO and CPW circuits for 38 GHz bandapplications

A single side-band (SSB) MMIC mixer employing a sub-harmonic configuration with an anti-parallel diode (APD) pair for 38 GHz band applications is designed and fabricated. Coplanar waveguide (CPW) models were used to design the mixer circuit. It acts as both an up- and down-converter with a conversion loss of less than 12.4 dB and a high image rejection ratio of greater than 15.1 dB over a wide frequency range from 32.5 to 42.0 GHz     

A 5-10 GHz octave-band AlGaAs/GaAs HBT-Schottky diodedown-converter MMIC

The authors describe an AlGaAs/GaAs heterojunction bipolar transistor (HBT) X-band down-converter monolithic microwave integrated circuit (MMIC) which integrates a double double-balanced Schottky mixer and five stages of HBT amplification to achieve greater than 30 dB conversion gain over an RF bandwidth from 5 to 10 GHz. In addition, an output IP3 as high as +15 dBm has been achieved. The Schottky diodes are constructed from the existing N^$collector and N⁺ subcollector layers of the HBT molecular beam epitaxy (MBE) device structure. A novel HBT amplifier topology employing active feedback which provides wide bandwidth in a compact area is used for the RF, LO, and IF amplifier stages. The complete down-converter MMIC is realized in a 3.6×3.4 mm² area, is self-biased through a 6 V supply, and consumes 530 mW. This MMIC represents the highest complexity X-band down-converter MMIC demonstrated using GaAs HBT-Schottky diode technology     

Design and implementation of a 94 GHz CMOS down-conversion mixer with integrated miniature planar baluns for image radar sensors

A 94 GHz down-conversion mixer for image radar sensors using standard 90 nm CMOS technology is reported. The down-conversion mixer comprises a double-balanced Gilbert cell with peaking inductors between RF transconductance stage and LO switching transistors for conversion gain (CG) enhancement and noise figure suppression, a miniature planar balun for converting the single RF input signals to differential signals, another miniature planar balun for converting the single LO input signals to differential signals, and an IF amplifier. The mixer consumes 22.5 mW and achieves excellent RF-port input reflection coefficient of ?10 to ?35.9 dB for frequencies of 87.6–104.4 GHz, and LO-port input reflection coefficient of ?10 to ?31.9 dB for frequencies of 88.2–110 GHz. In addition, the mixer achieves CG of 4.9–7.9 dB for frequencies of 81.8–105.8 GHz (the corresponding 3-dB CG bandwidth is 24 GHz) and LO–RF isolation of 37.7–47.5 dB for frequencies of 80–110 GHz, one of the best CG and LO–RF isolation results ever reported for a down-conversion mixer with operation frequency around 94 GHz. Furthermore, the mixer achieves an excellent input third-order intercept point of ?3 dBm at 94 GHz. These results demonstrate the proposed down-conversion mixer architecture is promising for 94 GHz image radar sensors.