A 750 MHz semi-digital clock and data recovery circuit with 10~(-12) BER

A semi-digital clock and data recovery（CDR） is presented.In order to lower CDR trace jitter and decrease loop latency,an average-based phase detection algorithm is adopted and realized with a novel circuit. Implemented in a 0.13μm standard 1P8M CMOS process,our CDR is integrated into a high speed serial and de-serial（SERDES） chip.Measurement results of the chip show that the CDR can trace the phase of the input data well and the RMS jitter of the recovery clock in the observation pin is 122 ps at 75 MHz clock frequency,while the bit error rate of the recovery data is less than 10×10^-12.     

A wide-range all digital DLL for multiphase clock generation

This paper presents a wide-range all digital delay-locked loop (DLL) for multiphase clock generation. Using the phase compensation circuit (PCC), the large phase difference is compensated in the initial step. Thus, the proposed solution can overcome the false-lock problem in conventional designs, and keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. Furthermore, the proposed all digital multiphase clock generator has wide ranges and is not related to specific process. Thus, it can reduce the design time and design complexity in many different applications. The DLL is implemented in a 0.13 μm CMOS process. The experimental results show that the proposal has a wide frequency range. The peak-to-peak jitter is less than 7.7 ps over the operating frequency range of 200 MHz-1 GHz and the power consumption is 4.8 mW at 1 GHz. The maximum lock time is 20 clock cycles.     

An all-analog multiphase delay-locked loop using a replica delayline for wide-range operation and low-jitter performance

This paper describes an all-analog multiphase delay-locked loop (DLL) architecture that achieves both wide-range operation and low-jitter performance. A replica delay line is attached to a conventional DLL to fully utilize the frequency range of the voltage-controlled delay line. The proposed DLL keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. The DLL incorporates dynamic phase detectors and triply controlled delay cells with cell-level duty-cycle correction capability to generate equally spaced eight-phase clocks. The chip has been fabricated using a 0.35-μm CMOS process. The peak-to peak jitter is less than 30 ps over the operating frequency range of 62.5-250 MHz, At 250 MHz, its jitter supply sensitivity is 0.11 ps/mV. It occupies smaller area (0.2 mm²) and dissipates less power (42 mW) than other wide-range DLL's [2]-[7]     

A 10-Gb/s 16:1 multiplexer and 10-GHz clock synthesizer in0.25-μm SiGe BiCMOS

A 10-Gb/s 16:1 multiplexer, 10-GHz clock generator phase-locked loop (PLL), and 6 × 16 b input data buffer are integrated in a 0.25-μm SiGe BiCMOS technology. The chip multiplexes 16 parallel input data streams each at 622 Mb/s into a 9.953-Gb/s serial output stream. The device also produces a 9.953-GHz output clock from a 622- or 155-MHz reference frequency. The on-board 10-GHz voltage-controlled oscillator (VCO) has a 10% tuning range allowing the chip to accommodate both the SONET/SDH data rate of 9.953 Gb/s and a forward error correction coding rate of 10.664 Gb/s. The 6 × 16 b input data buffer accommodates ±2.4 ns of parallel input data phase drift at 622 Mb/s. A delay-locked loop (DLL) in the input data buffer allows the support of multiple input clocking modes. Using a clock generator PLL bandwidth of 6 MHz, the 9.953-GHz output clock exhibits a generated jitter of less than 0.05 UI_P-P over a 50-kHz to 80-MHz bandwidth and jitter peaking of less than 0.05 dB     

Fast lock-on time mixed mode DLL with 10 ps jitter

A fast lock-on time mixed mode delay locked loop (DLL) is proposed to eliminate phase error in two steps. A digital fixed delay line compensates for the initial large phase error and an analogue voltage controlled delay line compensates for the small static phase error, resulting in low jitter. The lock-on time of the DLL is less than 10 clock cycles and the simulated jitter is below 10 ps at 200 MHz     

A 2.5-10-Gb/s CMOS transceiver with alternating edge-sampling phase detection for loop characteristic stabilization

This paper describes a technique for stabilizing the binary phase detector (PD) gain under various jitter conditions. A dead zone in the phase detector estimates the magnitude of high-frequency data jitter, and the resulting jitter information is used to control the charge-pump current. An alternating edge-sampling (AES) PD reduces hardware overhead by removing possible redundancies in previous dead-zone implementations. A series sense amplifier driven by a single-phase clock helps high-speed data sampling with increased data evaluation time. A dual path voltage-controlled oscillator incorporating dual-loop architecture enables wide-range operation of clock/data recovery circuits with low jitter. Fabricated in a 0.18-/spl mu/m CMOS process, a test transceiver operates from 2.5 to 11.5 Gb/s with a bit-error rate of less than 10/sup -12/ while consuming 540 mW from a 1.8-V supply.     

A simple precharged CMOS phase frequency detector

We propose a simple precharged CMOS phase frequency detector (PFD). The circuit uses 18 transistors and has a simple topology. Therefore, the detector, in a 0.8-μm CMOS process, works up to clock frequencies of 800 MHz according to SPICE simulations on extracted layout. Further, the detector has no dead-zone in the phase characteristic which is important in low jitter applications. The phase and frequency characteristics are presented and comparisons are made to other PFDs. The phase offset of the detector is sensitive to differences of the duty-cycle between the inputs. Mixed-mode simulations are presented of the lock-in procedure for a phase-locked loop (PLL) where the detector is used. Measurements on the detector are presented for a test-chip with a delay-locked loop (DLL) where the phase detection ability of the detector has been verified     

A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector

A jitter-tolerance-enhanced 10 Gb/s clock and data recovery (CDR) circuit is presented. The proposed architecture cascades 2 half-rate CDRs with different loop bandwidth to relax the design bottleneck and the predicted jitter tolerance can be enhanced without sacrificing the jitter transfer. By using a gated digital-controlled oscillator (GDCO), the proposed GDCO-based phase detector may reduce the cost of this architecture and achieve a wide linear range. This CDR circuit has been fabricated in a 0.13 mum CMOS technology and consumes 60 mW from a 1.5 V supply. It occupies an active area of 0.36 mm². The measured rms jitter is 0.96 ps and the peak-to-peak jitter is 7.11 ps for a 10 Gb/s 2⁷-1 PRBS. The measured bit error rate for a 10 Gb/s 2⁷-1PRBS is less than 10^-12.     

A low jitter, low spur multiphase phase-locked loop for an IR-UWB receiver

A low jitter,low spur multiphase phase-locked loop(PLL) for an impulse radio ultra-wideband(IR-UWB) receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output.In this design,a noise and matching improved voltage-controlled oscillator(VCO) is devised to enhance the timing accuracy and phase noise performance of multiphase clocks.By good matching achieved in the charge pump and careful choice of the l...     

A low-noise fast-lock phase-locked loop with adaptive bandwidthcontrol

This paper presents a salient analog phase-locked loop (PLL) that adaptively controls the loop bandwidth according to the locking status and the phase error amount. When the phase error is large, such as in the locking mode, the PLL increases the loop bandwidth and achieves fast locking. On the other hand, when the phase error is small, this PLL decreases the loop bandwidth and minimizes output jitters. Based on an analog recursive bandwidth control algorithm, the PLL achieves the phase and frequency lock in less than 30 clock cycles without pre-training, and maintains the cycle-to-cycle jitter within 20 ps (peak-to-peak) in the tracking mode. A feed forward-type duty-cycle corrector is designed to keep the 50% duty cycle ratio over all operating frequency range     

A 155-MHz clock recovery delay- and phase-locked loop

The authors describe a completely monolithic delay-locked loop (DLL) that may be used either by itself as a deskewing element, or in conjunction with an external voltage-controlled crystal oscillator (VCXO) to form a delay- and phase-locked loop (D/PLL). By phase shifting the input data rather than the clock, the DLL and D/PLL provide jitter-peaking-free clock recovery. Additionally, the jitter transfer function of the D/PLL has a low bandwidth for good jitter filtering without compromising acquisition speed. The D/PLL described here exhibits less than 1° r.m.s. jitter on the recovered clock, independent of the input data density. No jitter peaking is observed over the 40-kHz jitter bandwidth     

SiGe clock and data recovery IC with linear-type PLL for 10-Gb/sSONET application

An integrated 10 Gb/s clock and data recovery (CDR) circuit is fabricated using SiGe technology, It consists of a linear-type phase-locked loop (PLL) based on a single-edge version of the Hogge phase detector, a LC-tank voltage-controlled oscillator (VCO) and a tri-state charge pump. A PLL equivalent model and design method to meet SONET jitter requirements are presented. The CDR was tested at 9.529 GB/s in full operation and up to 13.25 Gb/s in data recovery mode. Sensitivity is 14 mV_pp at a bit error rate (BER)=10^-9 . The measured recovered clock jitter is less than 1 ps RMS. The IC dissipates 1.5 W with a -5 V power supply     

A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector

A 10-Gb/s phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a half-rate phase/frequency detector with automatic data retiming. Fabricated in 0.18-/spl mu/m CMOS technology in an area of 1.75/spl times/1.55 mm/sup 2/, the circuit exhibits a capture range of 1.43 GHz, an rms jitter of 0.8 ps, a peak-to-peak jitter of 9.9 ps, and a bit error rate of 10/sup -9/ with a pseudorandom bit sequence of 2/sup 23/-1. The power dissipation excluding the output buffers is 91 mW from a 1.8-V supply.     

Practical measurement of timing jitter contributed by a clock-and-data recovery circuit

This paper describes a measurement of high-frequency jitter contributed by a clock-and-data recovery circuit. The contributed jitter is expressed with deterministic and random jitter terms and is given for a specific bit sequence. The measurement is illustrated on two multichannel CMOS serializer/deserializer chips applicable to 10-G Ethernet, 10-G Fibre Channel, and InfiniBand at per-channel rates of 2.5 and 3.125 GBaud.     

A Single-Stage Direct Interpolation Multiphase Clock Generator with Phase Error Averaging

Multiphase clock generators are conventionally implemented with a feedback loop. This paper presents a non-feedback approach to generate multiphase clocks. A simple architecture of direct phase interpolation is proposed, in which the edges of two phase-adjacent signals are used to control the discharge (or charge) of two capacitors respectively, producing time-overlapped slopes. A resistor chain connected to the two capacitors is used to interpolate a number of new slopes in between. The generated phase resolution depends on the number and ratios of resistors thus is not limited by an inverter delay. Based on this architecture, a multiphase clock generator is developed. In addition, a phase error averaging circuit is used to correct interphase errors. The multiphase clock generator has been fabricated in a 0.35 m, 3.3 V CMOS process. The measured performance shows it can produce 8 evenly spaced clock signals in one input clock period and work in an input clock range from 300 MHz to 600 MHz. The measured maximum jitter performance is rms 6.8 ps and peak-to-peak 47 ps, respectively.     

Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection

A fully integrated clock and data recovery circuit (CDR) using a multiplying shifted-averaging delay locked loop and a rate-detection circuit is presented. It can achieve wide range and low jitter operation. A duty-cycle-insensitive phase detector is also proposed to mitigate the dependency on clock duty cycle variations. The experimental prototype has been fabricated in a 0.25-/spl mu/m 1P5M CMOS technology and occupies an active area of 2.89 mm/sup 2/. The measured CDR could operate from 125 Mb/s to 2.0 Gb/s with a bit error rate better than 10/sup -12/ from a 2.5-V supply. Over the entire operating frequency range, the maximum rms jitter of the recovered clock is less than 4 ps.     

一种基于55nmCMOS工艺，输出频率0.1G-1.5G Hz的低抖动锁相环

本文设计了一种0.1G-1.5GHz,3.07pS RMS 抖动的多相位输出锁相环。通过引入双路径电荷泵,极大的减小了锁相环中的低通滤波器的尺寸。基于指定的功耗约束,提出了一种新颖的压控振荡器、电荷泵与鉴频鉴相器的尺寸优化方法,使用该方法,每个模块输出相位噪声减小了约3-6dBc/Hz。该锁相环在55nm的工艺下流片,集成了16pF的MOM电容,占用面积仅为0.05平方毫米。输出1.5GHz信号时,功耗2.8mW,相位噪声为-102dBc/Hz@1MHz。     

A new ADPLL architecture dedicated to program clock references synchronization

This paper presents a totally digital phase locked loop (PLL) used for the recovery of a MPEG-2 decoder clock. The All Digital PLL (ADPLL) is implemented with a frequency synthesizer based on a new technique for phase shifting, avoiding the phase accumulation of ADPLL using a ring oscillator or avoiding the multiphase generation if a delay-locked loop (DLL) is used. The strongest point of the proposed configuration is the possibility of implementing as many ADPLLs as needed in a single circuit, in the limit of the circuit resources, without additional external circuit. The transfer characteristic, frequency resolution and jitter performance are computed and discussed. Then, the ADPLL resources and the ADPLL performances in term of time response and jitter are reported.     

Low-jitter 10 GHz multiphase PLL in 90 nm CMOS

A 10 GHz multiphase phase-locked loop (PLL) implemented in 90 nm bulk CMOS technology is presented that uses a bootstrapped NMOS inverter oscillator to obtain steeper clock edges, which may yield an improved jitter performance. The measured values for the rms and peak-to-peak jitter are better than 1 and 7 ps, respectively.     

A 2.5-GHz eight-phase VCO in SiGe BiCMOS technology

We present a 2.5-GHz voltage-controlled oscillator (VCO) with eight equally distributed phases derived from a 10-GHz LC VCO. Stochastic and static phase errors were obtained by spectrum analyzer measurements in conjunction with an on-chip single-sideband mixer. From the measured phase noise spectrum, we predict an absolute rms jitter contribution of 130 fs in a 2-MHz bandwidth phase-locked loop. A static phase error of less than 0.7/spl deg/ was deduced from the sideband suppression. The eight-phase VCO is tunable from 2.35 to 2.85 GHz and draws 16 mA from a 2.0-V supply. Possible applications include clock and data recovery of a 10-Gb/s signal in a fiber-optic receiver as well as high-precision image rejection receivers and I/Q direct up-converters for radio-frequency applications.