An inductively coupled single-flux quantum NDRO memory cell

An inductively coupled single-flux quantum nondestructive readout (NDRO) memory cell was fabricated. Control lines of this memory cell are coupled to the main inductance loop. The margin for the damping resistor becomes larger than for a multiflux quantum memory cell. The memory cell containing all return lines occupies only 247 minimum-linewidth squares, on the basis of a 5-µm rule Pb-alloy technique.     

A Compact 60-GHz Transmitter--Receiver

A new, compact, low-cost, and reliable 60-GHz transmitier-receiver was developed for civilian use. Common components are used for transmitting and receiving functions. An IMPATT oscillator generates the millimeter-wave output power for both the transmitter and the receiver local oscillator. A common antenna is also used for transmitting and receiving signals without a circulator. A mixer is used as a modulator in transmission as well as a receiver front end. A noise figure of 13 dB is obtained by a balanced mixer with a 200-MHz IF frequency differential preamplifier. A reliable packaged GaAs varactor diode is used for the mixer-modulator (MM).     

A 60-GHz CMOS receiver front-end

The unlicensed band around 60 GHz can be utilized for wireless communications at data rates of several gigabits per second. This paper describes a receiver front-end that incorporates a folded microstrip geometry to create resonance at 60 GHz in a common-gate LNA and active mixers. Realized in 0.13-/spl mu/m CMOS technology, the receiver front-end provides a voltage gain of 28 dB with a noise figure of 12.5 dB while consuming 9 mW from a 1.2-V supply.     

A novel 3.5-GHz microwave counter using an opto-electronic harmonicheterodyne technique

A novel 3.5-GHz microwave counter using an optoelectronic harmonic heterodyne technique has been demonstrated. The system's performance has been discussed and evaluated, and is viewed as good, in comparison with today's microwave-counting systems. It is believed that this novel device has potential for measuring signals above 100 GHz     

A 60-GHz point-to-multipoint millimeter-wave fiber-radio communication system

A 60-GHz point-to-multipoint wireless access link with data rate of 156 Mb/s incorporating 60-GHz transceiver modules and full-duplex fiber-optic millimeter-wave transmission is developed for short-range applications such as indoor wireless local area networks and intelligent transport systems. For compact system configuration, a small-size millimeter-wave transceiver module with planar antennas is developed. The transceiver module is based on broadband planar integration and packaging of millimeter-wave circuits. The RF output power is +10 dBm and the measured 3-dB antenna beamwidth is 30/spl deg/. The total size of the developed 60-GHz transceiver module, except input and output connectors, is 50 mm /spl times/ 75 mm /spl times/ 35 mm. A point-to-point full duplex fiber-optic configuration is extended to the scheme with multiple access points (APs) by using a tree coupler and a dense wavelength division multiplexing multiplexer. The AP has a simple configuration without frequency conversion. The bit error rate and packet error rate performances of the 60-GHz fiber-radio access link are evaluated. Furthermore, the effect of the extension to the scheme with multiple APs is investigated.     

Submicron NbN/MgO/NbN Josephson tunnel junctions and theirapplication to the logic circuit

An improved fabrication process for submicron NbN/MgO/NbN Josephson tunnel junctions has been developed. By introducing a contact layer between the junction and the wiring layer, the critical current of the wiring above the junction was considerably enhanced. A logic circuit composed of four-junction logic gates was fabricated using 0.9-μm-square junctions. Logic delay measurement was successfully achieved with a minimum logic delay of 3.6 ps/gate and a wide operating margin of ±17% within 50 gates     

New binary counter circuit

A new binary counter circuit is described. The relevance of the design to solid-circuit techniques is discussed, and the simplicity and performance of the circuit are compared with other binary counter circuits suitable for realisation in solid form.     

A 1-GHz logic circuit family with sense amplifiers

This paper describes a newly developed logic circuit family based on dual-rail bit lines and sense amplifiers that is used extensively in a 1.0-GHz, single-issue, 64-bit PowerPC integer processor, gigahertz unit test site (guTS). The family consists of an incrementor, a count-leading-zero, a rotator, and a read-only memory. Each macro consists of a leaf-cell array, dual-rail bit lines, a row of sense amplifiers, a control block, and peripheral circuits. A common read-out scheme sensing the differential voltage of dual-rail bit lines is used. The hardware was fabricated in a 0.25-μm drawn channel length, six-metal-layer (Al) CMOS technology (1.8-V nominal VDD). Wafer testing was performed using a probe card. The macros were tested cycle by cycle by scanning the input data to the read/write address latches and data latches, and scanning the result out from the output receiving latches. Functional testing was performed on guTS macros at frequencies up to 1.0 GHz at 25°C with nominal VDD (1.1 GHz for the ROM)     

A 16–18.8-GHz Sub-Integer-N Frequency Synthesizer for 60-GHz Transceivers

An 18-GHz range frequency synthesizer is implemented in 0.13-mum SiGe BiCMOS technology as part of a 60-GHz superheterodyne transceiver chipset. It provides for RF channels of 56.5-64 GHz in 500-MHz steps, and features a phase-rotating multi-modulus divider capable of sub-integer division. Output frequency range from the synthesizer is 16.0 to 18.8 GHz, while the enabled RF frequency range is 3.5 times this, or 55.8 to 65.8 GHz. The measured RMS phase noise of the synthesizer is 0.8deg (1 MHz to 1 GHz integration), while phase noise at 100-kHz and 10-MHz offsets are -90 and -124 dBc/Hz, respectively. Reference spurs are 69 dBc; sub-integer spurs are -65 dBc; and combined power consumption from 1.2 and 2.7 V is 144 mW.     

110-GHz monolithic resonant-tunneling-diode trigger circuit

The design and fabrication of a novel resonant tunneling diode (RTD) structure to be used in a monolithically integrated trigger circuit are reported. The structure has been designed to have high peak current densities with relatively low resonant voltages. These devices have been monolithically integrated with resistors to build a high-frequency trigger circuit. Experiments demonstrated triggering performance up to 110 GHz with subpicosecond timing jitter     

一个改进的量子隐形传态回路

量子隐形传态是一种典型的量子通信方式,它用经典辅助的方法来传送量子态,并引入了量子纠缠的特性.实现隐形传态的量子回路形式有很多,为了更有效地传递量子态,本文在Brassard回路的基础上提出一个改进的量子回路,它具有更简洁的结构,并能实现量子隐形传态.     

A 60-GHz HEMT-MMIC analog frequency divider by two

This paper describes an analog frequency divider by two working in the millimeter wave frequency range around 60 GHz. This circuit is analyzed with a new method that allows one to determine the steady-state regime of any synchronized circuits with standard CAD commercial software. The method proposed relies upon the concept of open loop systems and is applicable to any feedback transistor circuits. The designed circuit was processed using a standard 0.25-μm HEMT technology. Four transistors were used for realizing the frequency division function as well as the input and output amplification. More than 10% frequency lock-in bandwidth was achieved, and conversion gain was obtained using input and output buffers. Measured results were found to be in good agreement with simulated ones     

应用于60GHz的CMOS频率生成器

本文提出一种用于60GHz的频率生成器,其由电流模二分频器和倍频器组成. 得益于电流模结构和差分对的非线性,该频率生成器具有很宽的工作频率范围以补偿工艺,电压和温度的偏差。频率生成器用90nm 工艺投片验证。芯片的面积为0.64X0.65mm^2,。测试结果表明在输入0dBm功率的时候,该频率生成器可以工作在15GHz-25GHz。整个芯片工作电压是1.2V,消耗12.1mW功耗。     

A New Transceiver Architecture for the 60-GHz Band

A new “half-RF” architecture incorporates a polyphase filter in the signal path to allow the use of a local oscillator frequency equal to half the input frequency. The receiver performs 90 $^{circ}$ phase shift and two downconversion steps to produce quadrature baseband outputs. The transmitter upconverts the quadrature baseband signals in two steps, applies the results to a polyphase filter, and sums its outputs. Each path employs a dedicated 30-GHz oscillator and is fabricated in 90-nm CMOS technology. The receiver achieves a noise figure of 5.7–7.1 dB and gain/phase mismatch of 1.1 dB/2.1$^{circ}$ while consuming 36 mW. The transmitter produces a maximum output level of $-$7.2 dBm and an image rejection of 20 dB while drawing 78 mW.      

A high-Q quasi-planar filtering solution for 60-GHz applications

A low insertion loss 2.2% bandwidth two-pole cavity filter was fabricated at 60 GHz by bonding metallized lids on each side of a 250-/spl mu/m silicon substrate. The lids are made by dry etching of a 500-/spl mu/m silicon substrate. The same process is used to etch via holes on the intermediate substrate. The position of these via holes fixes the external coupling and the coupling between the resonators. The measured unloaded quality factor is lied on the height of the cavity (1.05 mm) and is around 1100.     

A 60-GHz IMPATT oscillator array with pulsed operation

Describes the design and operation of a 60-GHz quasi-optical power combining array employing IMPATT diodes in a weakly coupled, hybrid, two-by-four arrangement. Frequency-locked operation of all eight elements has been achieved for CW operation with a total radiated power in excess of 2 W. Approximately 61 W of DC power was required to drive the array. Pulsed operation was investigated as a means of preventing overheating. The locking behavior of these pulsed arrays was characterized. The array was pulsed with a 2-ms-risetime, low-duty-cycle, 4-kHz bias. Under these conditions, single-frequency operation was observed throughout the duration of the pulse, including the turn-on period     

A 60- to 96-GHz high-temperature pressure window

Construction details of a mica millimeter-wave pressure window are given. Insertion loss under 0.4 dB from 60 to 90 GHz was achieved.     

A 1.5-GHz programmable divide-by-N GaAs counter

A GaAs divide-by-N programmable counter has been fabricated for use in microwave frequency synthesizers and other applications. The counter uses a 1-μm depletion-mode MESFET process. The counter is typically capable of dividing an input frequency of DC to 1.5 GHz by any divisor from 3 to 64 over a temperature range of -60 to 100°C. Input and output translators are incorporated to render the device fully compatible with emitter-coupled logic (ECL) logic levels. Power dissipation for the chip is 1.4 W. A custom gigahertz-rate automated digital IC tester has been used to characterize the counter. Reliability data to date indicate a minimum mean time to failure (MTTF) of 1.8×10⁶ h at 100°C     

60-GHz pseudomorphic-MODFET low-noise MMIC amplifiers

The development of V-band low-noise monolithic microwave integrated circuits (MMICs) based on pseudomorphic modulation-doped FETs (P-MODFETs) is presented. These dual-stage MMICs incorporate P-MODFETs, with 0.35-μm×60-μm gates, as the active elements, electron-beam-written tuning elements, and DC-blocking and bias networks. The dual-stage chips exhibited a maximum gain of 10.2 dB at 59.5 GHz and a minimum noise figure of 5.3 dB, with an associated gain of 8.2 dB at 58.2 GHz. A cascaded four-stage amplifier using two MMIC modules exhibited 5.8-dB minimum noise figure with an associated gain of 18.3 dB at 58 GHz and up to 21.1 dB of maximum gain