A power efficient differential 20-GHz low noise amplifier with 5.3-GHz 3-dB bandwidth

A 20-GHz differential two-stage low-noise amplifier (LNA) is demonstrated in a foundry digital 130-nm CMOS technology with 8-metal layers. This LNA has 20-dB voltage gain and /spl sim/5.5-dB noise figure at 20GHz with 24-mW power consumption. The measured IP/sub 1 dB/ and IIP/sub 3/ are -11 dBm and -4dBm. Compared to the previously published bulk CMOS LNAs operating above 20GHz, this LNA has exceptionally low power and current consumption especially considering its differential topology and wide bandwidth.     

0.18 /spl mu/m 3-6 GHz CMOS broadband LNA for UWB radio

A 3-6 GHz CMOS broadband low noise amplifier (LNA) for ultra-wideband (UWB) radio is presented. The LNA is fabricated with the 0.18 /spl mu/m 1P6M standard CMOS process. Measurement of the CMOS LNA is performed using an FR-4 PCB test fixture. From 3 to 6 GHz, the broadband LNA exhibits a noise figure of 4.7-6.7 dB, a gain of 13-16 dB, and an input/output return loss higher than 12/10 dB, respectively. The input P/sub 1 dB/ and input IP3 (IIP3) at 4.5 GHz are about -14 and -5 dBm, respectively. The DC supply is 1.8 V.     

Packaged single-ended CMOS low noise amplifier with 2.3 dB noise figure and 64 dBm IIP/sub 2/

A single-ended low noise amplifier (LNA) implemented in a foundry 0.18 /spl mu/m CMOS process is tested on a PC board using the chip-on-board technique. The measured S/sub 11/ and S/sub 22/ are less than -10 dB over 5.15-5.35 GHz, which is the lower subband of UNII and HIPERLAN/2 band. The measured noise figure is 2.0 dB and power gain is 15.5 dB at 5.15 GHz, while drawing 5.8 mA of current from a 1.8 V supply. The measured IIP/sub 2/ is greater than 64 dBm. This extremely high IP/sub 2/ is due to the tuned response of the LNA. The LNA is suitable for WLAN applications in the lower UNII and HIPERLAN/2 subband.     

Low-power programmable gain CMOS distributed LNA

A design methodology for low power MOS distributed amplifiers (DAs) is presented. The bias point of the MOS devices is optimized so that the DA can be used as a low-noise amplifier (LNA) in broadband applications. A prototype 9-mW LNA with programmable gain was implemented in a 0.18-/spl mu/m CMOS process. The LNA provides a flat gain, S/sub 21/, of 8 /spl plusmn/ 0.6dB from DC to 6.2 GHz, with an input impedance match, S/sub 11/, of -16 dB and an output impedance match, S/sub 22/, of -10 dB over the entire band. The 3-dB bandwidth of the distributed amplifier is 7GHz, the IIP3 is +3 dBm, and the noise figure ranges from 4.2 to 6.2 dB. The gain is programmable from -10 dB to +8 dB while gain flatness and matching are maintained.     

A fully monolithic 260-/spl mu/W, 1-GHz subthreshold low noise amplifier

A micro-power complementary metal oxide semiconductor (CMOS) low-noise amplifier (LNA) is presented based on subthreshold MOS operation in the GHz range. The LNA is fabricated in an 0.18-/spl mu/m CMOS process and has a gain of 13.6 dB at 1 GHz while drawing 260 /spl mu/A from a 1-V supply. An unrestrained bias technique, that automatically increases bias currents at high input power levels, is used to raise the input P1dB to -0.2 dBm. The LNA has a measured noise figure of 4.6 dB and an IIP3 of 7.2 dBm.     

Low-power W-band CPWG InAs/AlSb HEMT low-noise amplifier

We present the development of a low-power W-band low-noise amplifier (LNA) designed in a 200-nm InAs/AlSb high electron mobility transistor (HEMT) technology fabricated on a 50-/spl mu/m GaAs substrate. A single-stage coplanar waveguide with ground (CPWG) LNA is described. The LNA exhibits a noise figure of 2.5 dB and an associated gain of 5.6 dB at 90 GHz while consuming 2.0 mW of total dc power. This is, to the best of our knowledge, the lowest reported noise figure for an InAs/AlSb HEMT LNA at 90 GHz. Biased for maximum gain, the single-stage amplifier presents 6.7-dB gain and an output 1-dB gain compression point (P1dB) of -6.7dBm at 90 GHz. The amplifier provides broad-band gain, greater than 5dB over the entire W-band.     

Highly integrated 60 GHz transmitter and receiver MMICs in a GaAs pHEMT technology

Highly integrated transmitter and receiver MMICs have been designed in a commercial 0.15 /spl mu/m, 88 GHz f/sub T//183 GHz f/sub MAX/ GaAs pHEMT MMIC process and characterized on both chip and system level. These chips show the highest level of integration yet presented in the 60 GHz band and are true multipurpose front-end designs. The system operates with an LO signal in the range 7-8 GHz. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO chain, resulting in an IF center frequency of 2.5 GHz. Although the chips are inherently multipurpose designs, they are especially suitable for high-speed wireless data transmission due to their very broadband IF characteristics. The single-chip transmitter MMIC consists of a balanced resistive mixer with an integrated ultra-wideband IF balun, a three-stage power amplifier, and the X8 LO chain. The X8 is a multifunction design by itself consisting of a quadrupler, a feedback amplifier, a doubler, and a buffer amplifier. The transmitter chip delivers 3.7/spl plusmn/1.5 dBm over the RF frequency range of 54-61 GHz with a peak output power of 5.2 dBm at 57 GHz. The single-chip receiver MMIC contains a three-stage low-noise amplifier, an image reject mixer with an integrated ultra-wideband IF hybrid and the same X8 as used in the transmitter chip. The receiver chip has 7.1/spl plusmn/1.5 dB gain between 55 and 63 GHz, more than 20 dB of image rejection ratio between 59.5 and 64.5 GHz, 10.5 dB of noise figure, and -11 dBm of input-referred third-order intercept point (IIP3).     

A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-/spl mu/m CMOS

A low-noise amplifier (LNA) uses low-loss monolithic transformer feedback to neutralize the gate-drain overlap capacitance of a field-effect transistor (FET). A differential implementation in 0.18-/spl mu/m CMOS technology, designed for 5-GHz wireless local-area networks (LANs), achieves a measured power gain of 14.2 dB, noise figure (NF, 50 /spl Omega/) of 0.9 dB, and third-order input intercept point (IIP3) of +0.9 dBm at 5.75 GHz, while consuming 16 mW from a 1-V supply. The feedback design is benchmarked to a 5.75-GHz cascode LNA fabricated in the same technology that realizes 14.1-dB gain, 1.8-dB NF, and IIP3 of +4.2 dBm, while dissipating 21.6 mW at 1.8 V.     

A 5.7-GHz 0.18-/spl mu/m CMOS gain-controlled differential LNA with current reuse for WLAN receiver

This letter presents a 5.7 GHz 0.18 /spl mu/m CMOS gain-controlled differential LNA for an IEEE 802.11a WLAN application. The differential LNA, fabricated with the 0.18 /spl mu/m 1P6M standard CMOS process, uses a current-reuse technology to increase linear gain and save power consumption. The circuit measurement is performed using an FR-4 PCB test fixture. The LNA exhibits a noise figure of 3.7 dB, linear gain of 12.5 dB, P/sub 1dB/ of -11 dBm, and gain tuning range of 6.9 dB. The power consumption is 14.4 mW at V/sub DD/=1.8 V.     

A 17.1-17.3-GHz image-reject downconverter with phase-tunable LO using 3/spl times/ subharmonic injection locking

A 17-GHz RF receiver, consisting of a low-noise amplifier (LNA) and doubly balanced mixers coupled by a monolithic 3.7:1 step-down transformer, realizes over 75 dB of image rejection in a production 100-GHz f/sub T/ SiGe BiCMOS technology. A new coupling transformer winding improves the magnetic coupling coefficient by more than 20% compared to conventional designs, which reduces parasitic effects and increases the overall efficiency of the LNA/mixer combination. Quadrature LO signals with electronically tunable phase are generated by a subharmonically injection-locked oscillator. The measured receiver IIP3 is -5.1 dBm with 17.3-dB conversion gain and 6.5-dB noise figure (SSB 50 /spl Omega/) at 17.2 GHz. The 1.9/spl times/1.0 mm/sup 2/ IC consumes 62.5 mW from a 2.2-V supply.     

A 24-GHz 3.9-dB NF low-noise amplifier using 0.18 /spl mu/m CMOS technology

A 24-GHz low-noise amplifier (LNA) was designed and fabricated in a standard 0.18-/spl mu/m CMOS technology. The LNA chip achieves a peak gain of 13.1 dB at 24 GHz and a minimum noise figure of 3.9 dB at 24.3 GHz. The supply voltage and supply current are 1 V and 14 mA, respectively. To the author's knowledge, this LNA demonstrates the lowest noise figure among the reported LNAs in standard CMOS processes above 20 GHz.     

A 24-GHz CMOS front-end

This paper reports the first 24-GHz CMOS front-end in a 0.18-/spl mu/m process. It consists of a low-noise amplifier (LNA) and a mixer and downconverts an RF input at 24 GHz to an IF of 5 GHz. It has a power gain of 27.5 dB and an overall noise figure of 7.7 dB with an input return loss, S/sub 11/ of -21 dB consuming 20 mA from a 1.5-V supply. The LNA achieves a power gain of 15 dB and a noise figure of 6 dB on 16 mA of dc current. The LNA's input stage utilizes a common-gate with resistive feedthrough topology. The performance analysis of this topology predicts the experimental results with good accuracy.     

An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system

An ultra-wideband (UWB) CMOS low noise amplifier (LNA) topology that combines a narrowband LNA with a resistive shunt-feedback is proposed. The resistive shunt-feedback provides wideband input matching with small noise figure (NF) degradation by reducing the Q-factor of the narrowband LNA input and flattens the passband gain. The proposed UWB amplifier is implemented in 0.18-/spl mu/m CMOS technology for a 3.1-5-GHz UWB system. Measurements show a -3-dB gain bandwidth of 2-4.6GHz, a minimum NF of 2.3 dB, a power gain of 9.8 dB, better than -9 dB of input matching, and an input IP3 of -7dBm, while consuming only 12.6 mW of power.     

A low power dual-band multi-mode RF front-end for GNSS applications

A CMOS dual-band multi-mode RF front-end for the global navigation satellite system receivers of all GPS,Bei-Dou,Galileo and Glonass systems is presented.It consists of a reconfigurable low noise amplifier(LNA),a broadband active balun,a high linearity mixer and a bandgap reference(BGR) circuit.The effect of the input parasitic capacitance on the input impedance of the inductively degenerated common source LNA is analyzed in detail.By using two different LC networks at the input port and the switched cap...     

一种5~6 GHz宽带全集成CMOS低噪声放大器

采用55 nm标准CMOS工艺,设计并流片实现了一种应用于Wi-Fi 6(5 GHz)频段的宽带全集成CMOS低噪声放大器(LNA)芯片,包括源极退化共源共栅放大器、负载Balun及增益切换单元。在该设计中,所有电感均为片上实现;采用Balun负载,实现信号的单端转差分输出;具备高低增益模式,以满足输入信号动态范围要求。测试结果表明,在高增益模式下该放大器的最大电压增益为20.2 dB,最小噪声系数为2.2 dB;在低增益模式下该放大器的最大电压增益为15 dB,最大输入1 dB压缩点为-3.2 dBm。芯片核心面积为0.28 mm²,静态功耗为10.2 mW。     

一个应用于卫星导航接收机的低功耗可配置双频多模射频前端

本文给出了一个应用于GPS、北斗、伽利略和Glonass四种卫星导航接收机的高性能双频多模射频前端。该射频前端主要包括有可配置的低噪声放大器、宽带有源单转双电路、高线性度的混频器和带隙基准电路。详细分析了寄生电容对源极电感负反馈低噪声放大器输入匹配的影响,通过在输入端使用两个不同的LC匹配网络和输出端使用开关电容的方法使低噪声放大器可以工作在1.2GHz和1.5GHz频带。同时使用混联的有源单转双电路在较大的带宽下仍能获得较好的平衡度。另外,混频器采用MGTR技术在低功耗的条件下来获得较高的线性度,并不恶化电路的其他性能。测试结果表明：在1227.6MHz和1557.42MHz频率下,噪声系数分别为2.1dB和2.0dB,增益分别为33.9dB和33.8dB,输入1dB压缩点分别0dBm和1dBm,在1.8V电源电压下功耗为16mW。     

A miniature Q-band low noise amplifier using 0.13-/spl mu/m CMOS technology

A miniature Q-band low noise amplifier (LNA) using 0.13-/spl mu/m standard mixed signal/radio frequency complementary metal-oxide-semiconductor (CMOS) technology is presented in this letter. This three-stage common source thin-film microstrip LNA achieves a peak gain of 20dB at 43GHz with a compact chip size of 0.525mm/sup 2/. The 3-dB frequency bandwidth ranges from 34 to 44GHz and the minimum noise figure is 6.3dB at 41GHz. The LNA outperforms all the reported commercial standard CMOS Q-band LNAs, with the highest gain, highest output IP3, and smallest chip size.     

Wideband Balun-LNA With Simultaneous Output Balancing, Noise-Canceling and Distortion-Canceling

An inductorless low-noise amplifier (LNA) with active balun is proposed for multi-standard radio applications between 100 MHz and 6 GHz. It exploits a combination of a common-gate (CGH) stage and an admittance-scaled common-source (CS) stage with replica biasing to maximize balanced operation, while simultaneously canceling the noise and distortion of the CG-stage. In this way, a noise figure (NF) close to or below 3 dB can be achieved, while good linearity is possible when the CS-stage is carefully optimized. We show that a CS-stage with deep submicron transistors can have high IIP2, because the nu_gsldr nu_ds cross-term in a two-dimensional Taylor approximation of the I_DS(V_GS, V_DS) characteristic can cancel the traditionally dominant square-law term in the I_DS(V_GS) relation at practical gain values. Using standard 65 nm transistors at 1.2 V supply voltage, we realize a balun-LNA with 15 dB gain, NF < 3.5 dB and IIP2 > +20 dBm, while simultaneously achieving an IIP3 > 0 dBm. The best performance of the balun is achieved between 300 MHz to 3.5 GHz with gain and phase errors below 0.3 dB and plusmn2 degrees. The total power consumption is 21 mW, while the active area is only 0.01 mm².     

基于移动数字电视应用的宽带可变增益LNA设计

提出了0.13 μm CMOS工艺下可兼容多标准DVB-H/DAB/CMMB的移动数字电视调谐器射频前端双通道LNA设计。在UHF频段和L波段下,设计分别采用片上balun电路、双交叉耦合技术、开关转换电路、伪差分电路等技术以达到LNA宽带匹配、可变增益、低NF及高线性度的指标要求。版图后仿真结果显示:在UHF频段,仿真频率范围为470~860MHz,LNA增益范围为14.7~38.8dB,NF<2.4dB,IIP3=1.979dBm;在L波段,仿真频率范围为1.4~1.8 GHz,LNA增益范围为13~38.5 dB,NF<2.7 dB,IIP3=3.605 dBm。该设计较好地实现了多标准下LNA宽带可变增益性能。     

应用于S波段的高线性低噪声放大器

采用E-mode 0.25um GaAs pHEMT工艺,2.0mm × 2.0mm 8-pin双侧引脚扁平封装,设计了一款应用于S波段的噪声系数低于0.5dB的低噪声放大器。通过采用共源共栅结构、有源偏置网络和多重反馈网络等技术改进了电路结构,该放大器具有低噪声,高增益,高线性等特点,是手持终端应用上理想的一款低噪声放大器。测试结果表明在2.3-2.7GHz内,增益大于18dB,输入回波损耗小于-10dB,输出回波损耗小于-16dB,输出三阶交调点大于36dB。