18‐31 GHz GaN wideband low noise amplifier (LNA) using a 0.1 μm T‐gate high electron mobility transistor (HEMT) process

GaN technology has attracted main attention towards its application to high‐power amplifier. Most recently, noise performance of GaN device has also won acceptance. Compared with GaAs low noise amplifier (LNA), GaN LNA has a unique superiority on power handling. In this work, we report a wideband Silicon‐substrate GaN MMIC LNA operating in 18‐31 GHz frequency range using a commercial 0.1 μm T‐Gate high electron mobility transistor process (OMMIC D01GH). The GaN MMIC LNA has an average noise figure of 1.43 dB over the band and a minimum value of 1.27 dB at 23.2 GHz, which can compete with GaAs and InP MMIC LNA. The small‐signal gain is between 22 and 25 dB across the band, the input and output return losses of the MMIC are less than ?10 dB. The P_1dB and OIP3 are at 17 dBm and 28 dBm level. The four‐stage MMIC is 2.3 × 1.0 mm² in area and consumes 280 mW DC power. Compared with GaAs and InP LNA, the GaN MMIC LNA in this work exhibits a comparative noise figure with higher linearity and power handling ability.     

A CMOS low noise amplifier based on common source technique for ISM band application

In this paper a 2.45 GHz narrowband low noise amplifier (LNA) for wireless communication system is enunciated. The proposed CMOS Low Noise amplifier has been verified through cadence spectre RF simulation in standard UMC 90 nm CMOS process. The proposed LNA is designed by cascoding of two transistors; that is the common source transistor drives a common gate transistor. To achieve better power gain along with low noise figure, cascoding of two transistor and source degeneration technique is used and for low power consumption, the MOS transistors are biased in subthreshold region. At 2.45 GHz frequency, it exhibits power gain 31.53 dB. The S11, S22 and S12 of the circuit is ?9.14, ?9.22 and ?38.03 dB respectively. The 1 dB compression point of the circuit is ?16.89 dBm and IIP3 is ?5.70 dBm. The noise figure is 2.34 dB, input/output match of ?9.14 dB/?9.22 dB and power consumption 8.5 mW at 1.2 V.     

一款RFID低噪声放大器的设计与仿真

电子标签的广泛应用对UHF RFID(超高频射频识别)阅读器的性能提出了更高的要求.低噪声放大器能降低系统的噪声和提高接收机灵敏度,是接收系统的关键部件.设计的LNA应用于UHF RFID阅读器前端,要求工作频率为900一930MHz,噪声系数小于1dB,带内增益大于15dB以及高线性度指标包括输出1dB压缩点大于15dBm和输出三阶互调点大于30dBm.结合相关设计理论,利用安捷伦科技的E-PHEMT(增强型伪高电子迁移率晶体管)ATF54143,完成了电路设计并通过ADS2006对直流偏置、输入输出匹配以及源极加负反馈进行优化等仿真,结果表明:电路的噪声系数可达到0.54dB,功率增益高达23.4dB,输入、输出匹配良好,各种线性度指标也完全符合设计要求.     

Survey on parameter optimization of mobile communication band low noise amplifier design

A comparative study on recent works on low noise amplifiers (LNAs) designed to be operated at mobile communication band is performed in this article. Here, specifications of different generations of mobile communication are listed, which are considered to classify recent works on LNAs. Even though gain and noise figure (NF) are the primary parameters of LNA; other parameters like power, linearity, bandwidth, and area also get importance. Due to this, optimization techniques handpicked for all those parameters are discussed. The inverse relation between gain and NF is exploited to achieve low noise and high gain together. While increasing the gain, power consumption is increased by drain current. Each LNA is found as good in terms of gain and other parameters to satisfy the requirements. The figure of merit is opted to find the performance of each LNA, and the comparison is performed. The best parameters reported in the comparison are 31.53 dB of gain, 0.7 dB of NF, 0.03 mw of power consumption, 18.14 dBm of third‐order input intercept point (IIP3), 24 GHz bandwidth and 0.0052 mm² of area at different frequencies and technology nodes. In this survey, as per the optimized FoM for mobile communication, cross‐coupled common gate differential LNA, which was designed to be operated at 0.3 to 2.96 GHz gives better results among CMOS LNAs.     

Analysis and design of packaged and ESD protected BiCMOS RF front‐end for a UHF receiver

The design of packaged and ESD protected RF front‐end circuits for UHF receiver working at ISM band is presented. By extensively evaluating the effects of the package and ESD parasitics on the LNA input impedance, transconductance, and noise figure, some useful guidelines on the design of inductively degenerated common emitter LNA with package and ESD protection are provided. In addition, by taking advantage of both the bipolar and MOSFET devices, a BiFET mixer with low noise and high linearity is also described in this article. With the careful consideration of the tradeoffs among noise figure, linearity, power gain, and power consumption, the front‐end is implemented in a generic low‐cost 0.8‐μm BiCMOS technology. The on‐board measurement of the packaged RF front‐end circuits demonstrates a 20.3‐dB power gain, 2.6‐dB DSB noise figure, and ?9.5‐dBm input referred third intercept point while consuming about 3.9‐mA current. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.     

A miniature low‐power ultra‐wideband low noise amplifier in 0.18 μm CMOS

A 0.18‐μm CMOS low‐noise amplifier (LNA) operating over the entire ultra‐wideband (UWB) frequency range of 3.1–10.6 GHz, has been designed, fabricated, and tested. The UWB LNA achieves the measured power gain of 7.5 ± 2.5 dB, minimum input matching of ?8 dB, noise figure from 3.9 to 6.3 dB, and IIP3 from ?8 to ?1.9 dBm, while consuming only 9 mW over 3–10 GHz. It occupies only 0.55 × 0.4 mm² without RF and DC pads. The design uses only two on‐chip inductors, one of which is such small that could be replaced by a bonding wire. The gain, noise figure, and matching of the amplifier are also analyzed. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE , 2011.     

Design of 5.5 GHz linear low noise amplifier using post distortion technique with body biasing

A highly linear 5.5 GHz low noise amplifier (LNA) has been designed exploiting source inductive degeneration topology by using post distortion linearization techniques in 0.18 m CMOS technology. This technique improves the input third order intercept point \((IIP_{3})\) of a low noise amplifier. For enhancing the linearity, this technique used a diode connected MOSFET as IMD sinker and forward body biased which is done in cadence tool. The proposed low noise amplifier achieves high \(IIP_{3}\) by using two transistors, main and auxiliary transistors. Also source inductive degeneration topology is employed in the proposed LNA to optimize the noise figure (NF) and \(S_{11}\) at high frequency. In order to reduce power consumption and threshold voltage, Forward Body Biased technique was implemented. In this paper, the first section discusses the most widely used eight linearization techniques and in the second section, the proposed circuit is represented along with its employed topology, techniques and the simulated results. The proposed LNA achieves a simulated third order input intercept \((IIP_{3})\) of 9.20 dBm while consuming 10.8 mW from a power supply of 1.8 V. it also exhibits a measured gain of 11.34 dB and NF, NF of 2.33 dB.     

PVT‐compensated low‐voltage and low‐power CMOS LNA for IoT applications

In this paper, a low‐noise amplifier (LNA) with process, voltage, and temperature (PVT) compensation for low power dissipation applications is designed. When supply voltage and LNA bias are close to the subthreshold, voltage has significant impact on power reduction. At this voltage level, the gain is reduced and various circuit parameters become highly sensitive to PVT variations. In the proposed LNA circuit, in order to enhance efficiency at low supply voltage, the cascade technique with g_m boosting is used. To improve circuit performance when in the subthreshold area, the forward body bias technique is used. Also, a new PVT compensator is suggested to reduce sensitivity of different circuit's parameters to PVT changes. The suggested PVT compensator employs a current reference circuit with constant output regarding temperature and voltage variations. This circuit produces a constant current by subtracting two proportional to absolute temperature currents. At a supply voltage of 0.35 V, the total power consumption is 585 μW. In different process corners, in the proposed LNA with PVT compensator, gain and noise figure (NF) variations are reduced 10.3 and 4.6 times, respectively, compared to a conventional LNA with constant bias. With a 20% deviation in the supply voltage, the gain and noise NF variations decrease 6.5 and 34 times, respectively.     

A low power fully differential RF receiver front-end for 2.4 GHz wireless sensor networks

In this paper, a novel merged LNA-mixer denoted as LNMA is proposed. The proposed LNMA consisting of a folded cascode LNA using improved derivative superposition technique and folded double-balanced subthreshold mixer using capacitor cross-coupled common-gate transconductor and it is integrated with on-chip LC voltage controlled oscillator (LC-VCO). In LNMA, a diode and power clamp based on-chip ESD protection circuit is used to tolerate ESD current of human-body-model specifications. To evaluate its performance, it is implemented in 0.18-µm MMRF CMOS process with 1-V supply, studied through post layout simulation and compared the results with other reported works. It achieves higher conversion gain of 27 dB, lower noise figure of 9.5 dB, lower input return loss (S11) of − 20 dB, higher third-order input intercept point (IIP₃) of – 16 dBm and higher IIP₂ of + 29.9 dBm compared to the works reported in the literature. The on-chip oscillator has the lower phase noise of – 114 dBc/Hz. The proposed LNMA and the LC-VCO achieves the power consumptions of 1.6 and 1.72 mW, respectively at 1-V power supply.

     

自偏置低噪放的设计与改进

分析了贴片电容的非理想特性在C波段及以上频率的自偏置电路旁路应用中对低噪放设计的不利影响.分析表明,贴片电容用做自偏置旁路时将严重恶化电路的稳定性和噪声指标.提出了对自偏置电路的改进方法及工艺实现,从而避免了电容对指标的负面影响.为了验证改进电路的优势,采用改进的自偏置电路设计了6 GHz～9 GHz低噪放,实验结果很...     

Performance comparison of a single and multiband power amplifiers using IHP 0.25 μm SIGe HBT technology

In this work, a single‐band power amplifier (PA) with a fixed‐frequency/band output matching network and multiband PA with a switch‐tuned output matching network is designed, using IHP (Innovations for High Performance), 0.25 μm‐SiGe HBT process. The behavior of the amplifiers has been optimized for 2.4 GHz (WLAN), 3.6 GHz (UWB‐WiMAX), and 5.4 GHz (WLAN) frequency bands for a higher 1‐dB compression point and efficiency. Multiband characteristics of the amplifier were obtained by using a MOS‐based switching network. Two MOS switches were used for tuning the band of the output matching network. Postlayout simulations of the multiband‐PA provided the following performance parameters: 1‐dB compression point of 25.2 dBm, gain value of 36 dB, efficiency value of 12.8% operation and maximum output power of 26.8 dBm for the 2.4 GHz WLAN band, 1‐dB compression point of 25.5 dBm, gain value of 32 dB, efficiency value of 13.3% and maximum output power of 26.6 dBm for the 3.6 GHz UWB‐WiMAX band and 1‐dB compression point of 24.8 dBm, gain value of 23 dB, efficiency value of 12.5% and maximum output power of 26.3 dBm for the 5.4 GHz WLAN band. For the fixed‐band, at 3.6 GHz, the postlayout simulations resulted the following parameters: 1‐dB compression point of 25.5 dBm, gain value of 32 dB, efficiency value of 18% and maximum output power value of 26.8 dBm. Measurement results of the single‐band PA provided the following performance parameters: 1‐dB compression point of 20.5 dBm, gain value of 23 dB and efficiency value of 7% operation for the 2.4 GHz band; 1‐dB compression point of 25.5 dBm, gain value of 31.5 dB and efficiency value of 17.5% for the 3.6 GHz band; 1‐dB compression point of 22.4 dBm, gain value of 24.4 dB and efficiency value of 9.5% for the 5.4 GHz band. Measurement results show that using multistage topologies and implementing each parasitic as part of the matching network component has provided a wider‐band operation with higher output power levels, above 25 dBm, with SiGe:C process. These results proved that the PA, with switching/tunable output matching network, provides compatible performance parameters, when compared with the fixed‐band PA. The ability of being capable of operation in different frequency bands with compatible performance parameters, when compared with fixed‐band PA, multiband PA can be realized with additional less parasitics, area, and cost advantages. © 2009 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

Modelling of navigation based LNA parameters using neural network technique

An approach to model the parameters of LNA which is ideal for GLONASS navigation system. To design LNA, multilayer perceptron architecture is used. The parameters of LNA are calculated using Levenberg Marquardt Backpropagation Algorithm for the frequency range 300 MHz to 18 GHz. ANN model is trained using Agilent MGA 71543 Low Noise Amplifier datasheet and this model shows high regression. The smith and polar charts are plotted for frequency range 300 MHz to 18 GHz and parameters are calculated for center frequency of L1 band of GLONASS, which is 1.602 GHz.     

A W‐band RF‐MEMS switched LNA in a 70 nm mHEMT process

This work presents a monolithic integrated reconfigurable active circuit consisting of a W‐band RF micro‐electro‐mechanical‐systems (MEMS) Dicke switch network and a wideband low‐noise amplifier (LNA) realized in a 70 nm gallium arsenide (GaAs) metamorphic high electron mobility transistor process technology. The RF‐MEMS LNA has a measured gain of 10.2–15.6 dB and 1.3–8.2 dB at 79–96 GHz when the Dicke switch is switched ON and OFF, respectively. Compared with the three‐stage LNA used in this design the measured in‐band noise figure (NF) of MEMS switched LNA is minimum 1.6 dB higher. To the authors’ knowledge, the experimental results represent a first time demonstration of a W‐band MEMS switched LNA monolithic microwave integrated circuit (MMIC) in a GaAs foundry process with a minimum NF of 5 dB. The proposed novel integration of such MEMS switched MMICs can enable more cost‐effective ways to realize high‐performance single‐chip mm‐wave reconfigurable radiometer front‐ends for space and security applications, for example. © 2015 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:639–646, 2015.     

一种开环自动电平控制系统的研究

针对分频器输出信号功率对输入信号功率不敏感的特性,提出了一种简单实用的开环式自动电平控制系统。该系统的电路由一个以10 dB为步进的衰减器和一个以1 dB为步进的可变增益放大器级联而成,其实现算法主要由前期建表与功率控制算法组成,而功率控制算法主要由双线性插值算法和直接赋值算法组成。通过实验对设计的电路及算法进行了验证,当输入信号功率范围为0~+10 dBm时,系统输出功率范围为-30~+10 dBm,步进为1 dB,功率误差为±2 dB。     

一种新型负反馈超宽带低噪声放大器的设计与实现

随着超宽带技术的发展,系统设计对低噪声放大器的性能提出了越来越高的要求。针对宽带放大器增益平坦度低。匹配性差等问题,本文从负反馈理论着手,改进了负反馈网络。通过ADS软件的辅助设计,实现了30MH—1．35GHz频段下的低噪声放大器的设计。通过对各项电路参数的优化,实现了增益为17．7dB,增益平坦度小于dB,输入输出电压驻波比小于1．5,噪声系数小于2．6的技术指标。     

Artificial neural network approach for LNA design of GPS receiver

Paper presents an ANN modeling of microwave LNA for the global positioning front end receiver, operating at 1.57542 GHz. To design LNA, multilayer perceptron architecture is used. The scattering parameters of LNA are calculated using Levenberg Marquardt Backpropagation Algorithm for the frequency range 100 MHz to 8 GHz. The inputs given to this architecture are drain to source current, drain to source voltage, temperature and frequency and the outputs are maximum available gain, noise figure and scattering parameters (magnitude as well as angle). ANN model is trained using Agilent MGA 72543 GaAs pHEMT Low Noise Amplifier datasheet and this model shows high regression. The smith and polar charts are plotted for frequency range 100 MHz to 8 GHz.     

基于CMOS模拟开关实现平衡混频器

详细介绍了有源单平衡混频器的电路组成,分析了有源平衡混频器的工作原理。基于CMOS模拟开关设计实现了一种(低功耗、高线性度的)开关平衡混频器,最后对混频器的指标进行了测量和分析。测试结果表明(在3.3V电源电压下,消耗电流小于10mA,射频输入信号)在60～110MHz频带范围内,(本振信号+10dBm时)插入损耗小于7dB,波动小于1dB,输入P1dB压缩点大于13dBm。     

一种0.8GHz～6GHz CMOS超宽带低噪声放大器设计

给出了一个针对0.8GHz～6GHz 的超宽带低噪声放大器 UWB LNA(ultra-wideband low noiseamplifier)设计。设计采用0.18μm RF CMOS 工艺完成。在0.8GHz～6GHz 的频段内,放大器增益 S21达到了17.6dB～13.6dB。输入、输出均实现良好的阻抗匹配,S11、S22均低于-10dB。噪声系数(NF)为2.7dB～4.6dB。在1.8V 工作电压下放大器的直流功耗约为12mW。     

An efficient wideband low noise amplifier (WLNA) using advanced design system based industrial micro strip antenna

An efficient architecture to design low noise amplifier methods aimed at reducing the radar cross-section (RCS) under the X - and Y-polarizations with incident waves, the characteristics of radiation has been analyzed. The goal is to carry out the Polarization Conversion Meta Material (PCM) implementation and passive cancelation policy. The Low-Noise Amplifier (LNA) supports the use of multi-stable applications being the front end of any micro strip antenna with the need for a multiband receiver is very high in technology development. This LNA design requires the synchronization of a single device frequency of a different device. So researchers work on developing a Wideband Low noise Amplifier (WLNA) with the wideband receiver. An LNA radio receiver from the mainstream is that the subsequent stages of the signal are lossless and the low noise rate has the highest gain. LNA design is an important task for the proper management of trade between all parameters of it, including gain, noise, stability, and power consumption. Advanced Design System (ADS) software is used to design and simulated the proposed micro strip antenna with LNA. The proposed micro strip antenna is to be fabricated using the Fr4 substrate and investigated by simulation and measurements like radiation patterns, S-parameters and return loss by using Advanced Design System software to improve the existing System.     

A compact omnidirectional dual‐circinal rectenna for 2.45 GHz wireless power transfer

A compact dual‐circinal rectenna with omnidirectional characteristic is designed for microwave wireless power transmission at 2.45 GHz. A novel dual‐circinal receiving antenna with the reflection coefficient of ?32.5 dB is proposed which is formed by expanding folded curves. By designing an impedance matching network with a 60 ° radial stub and a single stub, a rectifier is presented with the maximum efficiency of 55.6 % and the output dc voltage of 1.19 V under the input power of 0 dBm. Simulation and measurements have been carried out for the antenna and the rectifier. The measured results agree well with the simulated value. The results of rectenna experiment show that the maximum conversion efficiency is 51% at 2.45 GHz when the input power is 0 dBm. The proposed rectenna has the characteristics of compact size and omnidirectional harvesting which are advantageous in RF energy harvesting applications.