A soft-output decoding algorithm for concatenated systems

In order to fully utilize the SDD (soft-decision decoding) capacity of the outer codes in a concatenated system, reliability information on the inner decoder outputs (called soft outputs) needs to be provided to the outer decoder. This paper shows that a modified MAP algorithm can be effectively and accurately used to generate such information. In the course of the presentation, a metric based on the reliability information is proposed for the outer decoder. This metric has the Euclidean metric on AWGN channels as its special case, which leads to the concept of generalized SDD (GSDD). Several practical concerns regarding the proposed soft-output decoder are addressed through theoretical analysis and simulation: the effect of finite decoding depth, computational complexity, range overflow, and scaling. Comparisons to previous work on soft-output decoders are made     

A general-purpose high-speed equalizer

The circuit presented is a high-speed self-adaptive filter achieving equalization over a wide range of signals, with a frequency of up to 40.5 MHz, as for the European D2-MAC and high-definition multiplexed analog components (HD-MAC) transmission standards. The circuit is a self-adaptive 16-tap transversal filter achieving equalization on any 8-b coded signal. It contains periodically a window of binary or duobinary data samples, such as the D, D2, and HD-MAC signals. This chip includes a delay line of 240 8-b data samples which are used for the internal gradient computations. Only linear distortions (echos) can be corrected by this chip. This 105000-transistor chip has been designed in a CMOS 1.0-μm technology and is being used in a D2-MAC reception environment     

A blind equalizer for nonstationary discrete-valued signals

Adaptive algorithms are proposed for blind equalization of communication channels. The algorithms explicitly utilize the finite alphabetical set of the input signals and minimize a criterion that depends solely on the alphabetical set. The method is shown to be able to handle nonstationary signals without requiring or estimating their time-varying statistical parameters. Simulation results are presented to test and demonstrate the method     

A DECISION FEEDBACK EQUALIZER FOR NON-LINEAR CHANNELS

A Simple and useful decision feedback equalizer used for non-linear channels with severe linear distortion and mild non-linear distortion is proposed. It is a combination of a nonlinear channel equalizer based on connectionist model and a common decision feedback equalizer for linear channels. For a typical non-linear channel model it is shown that the equalization performances of the proposed equalizer are improved significantly.     

A concatenated coded modulation scheme for error control

A concatenated coded modulation scheme is presented for error control in data communications. The scheme is achieved by concatenating a Reed-Solomon outer code and a bandwidth efficient block inner code for M-ary phase-shift keying (PSK) modulation. Error performance of the scheme is analyzed for an additive white Gaussian noise (AWGN) channel. It is shown that extremely high reliability can be attained by using a simple M-ary PSK modulation inner-code and a relatively powerful Reed-Solomon outer code. Furthermore, if an inner code of high effective rate is used, the bandwidth expansion required by the scheme due to coding will be greatly reduced. The scheme is particularly effective for high-speed satellite communications for large file transfer where high reliability is required. A simple method is also presented for constructing block codes for M-ary PSK modulation. Soome short M-ary PSK codes with good minimum squared Euclidean distance are constructed. These codes have trellis structure and hence can be decoded with a soft-decision Viterbi decoding algorithm. Furthermore, some of these codes are phase invariant under multiples of 45° rotation     

一种新型上行SCMA系统接收机

稀疏码多址接入(SCMA)是一种码域非正交多址接入技术,以其优异性能成为5G多址接入技术的热门候选方案.上行SCMA系统一般采用消息传递算法(MPA)接收机,检测过程中存在由先验信息带来的误差.针对这一问题提出一种新型接收机,称为环MPA (R-MPA)接收机,其通过一种联合检测方案来消除上述误差对最终检测结果的影响.理论分析和仿真验证表明,与现有的log-MPA接收机及经典MPA接收机相比,所提R-MPA接收机是一种检测精度更高而实施复杂度较低的上行SCMA系统接收机.     

Energy and delay aware routing algorithm for fiber-wireless networks

Access networks consume significant portion of the overall energy consumed by internet. The power consumption growth rate of internet is higher than any other consumer of energy. With the introduction of more and more bandwidth hungry applications, there is a huge pressure to reduce network energy consumption while still growing network capacity and functionality. We propose an energy and delay aware routing algorithm for fiber-wireless (FiWi) networks (EDAR) which not only reduce the energy consumption of the FiWi networks and but also does not degrade the overall delay of the network. We introduce dynamic thresholds for switching nodes into sleep and active mode. Our analyses show a significant reduction in the energy consumption of the FiWi networks while keeping the performance of the network up to an acceptable limit.     

A mixed-signal RAM decision-feedback equalizer for disk drives

A mixed-signal RAM decision-feedback equalizer (DFE) that operates at 90 Mb/s is described. In the analog domain, the DFE subtracts intersymbol interference caused by the past four outputs. The equalized signal is fed into a nonuniform flash analog-to-digital converter (ADC) to produce the decision output and error signal used to adapt the RAM contents in the digital domain. With a 5 V supply voltage, the power dissipation is 260 mW during steady-state operation. The active area is 4.5 mm² in a 1 μm CMOS process     

A NEW ADAPTIVE EQUALIZER STRUCTURE FOR NONLINEAR CHANNELS

Based on the analysis of nonlinear channel models,a new connectionist model ofadaptive equalizer is constructed.Comparing with the connectionist model using the Volterraseries to extend the input vector space,the number of weights with the new structure is reducedsignificantly.It is shown by simulations that the weight values of the new scheme converge to theoptimal values closely for non-minimum phase channels as well minimum phase channels,if thechannel noise is small enough.Testing results of the BER(Bit Error Rate)tell us that the newadaptive equalizer for nonlinear channels is superior to the conventional linear equalizers in theequalization performances.     

A MAP equalizer for the optical communications channel

A maximum a posteriori (MAP) equalizer is presented for optical fiber communication systems. Assuming that the span of the intersymbol interference (ISI) does not extend beyond neighboring bits-typically the case for the distortion introduced by polarization-mode dispersion (PMD)-we derive the conditional probability density function (pdf) in the electrical domain in the presence of PMD and amplified spontaneous emission (ASE)-dominated noise. Simulation results with an accurate receiver model and all-order PMD show the success of the MAP equalizer in reducing the bit error rate (BER) degradation due to PMD.     

A low-power backward equalizer for DFE read-channel applications

A general-purpose backward equalizer for use in decision feedback equalization systems is described. Current-steering techniques are used to achieve high-speed low-power operation. A four-tap prototype for use in a magnetic disk read-channel chip has been implemented in a standard digital 1.2-μm n-well CMOS process. The circuit operates at 67 MHz and dissipates 1 mW/tap from a 3.3 V power supply     

A linear equalizer for high-speed APD-Based integrate-and-dump receivers

A linear minimum mean-square error (LMMSE) equalizer for avalanche-photodiode (APD) based integrate-and-dump receivers is designed to compensate for intersymbol-interference (ISI) introduced by the APD's random impulse response. Recent work on the characterization of the joint probability distribution of the APD's gain and buildup-time are adopted and utilized to determine the mean and correlation matrix of the APD-based receiver's random impulse response. This LMMSE equalizer is shown to improve the bit-error-rate dramatically at high transmission rates, resulting in an improvement in the receiver sensitivity by approximately 2.3 dB at 15 GHz.     

A current-mode biquadratic amplitude equalizer

A boost biquad transfer function with two symmetrical zeros on the real axis is derived; it provides a technique for amplitude equalization with a second-order continuous-timeg _m -C section using current injection. The synthesis procedure yields a differential boost biquad consisting of three double-input OTAs and a single-input high-g _m boost OTA. SPICE simulations show that for boost gain up to 20 dB the phase of the biquad is essentially unaffected. The presented technique is found suitable for amplitude equalization of disk-drive read channels operating in the range of 100 MHz.     

A fast computation algorithm for the decision feedback equalizer

A novel fast algorithm for computing the minimum MSE decision feedback equalizer settings is proposed. The equalizer filters are computed indirectly, first by estimating the channel, and then by computing the coefficients in the frequency domain with the discrete Fourier transform (DFT). Approximating the correlation matrices by circulant matrices facilitates the whole computation with very small performance loss. The fractionally spaced equalizer settings are derived. The performance of the fast algorithm is evaluated through simulation. The effects of the channel estimation error and finite precision arithmetic are briefly analyzed. Results of simulation show the superiority of the proposed scheme     

A DSP line equalizer VLSI for TCM digital subscriber-linetransmission

The architecture of a line equalizer using digital-signal-processing (DSP) techniques is described. The equalizer is utilized in 320-kb/s time-compression multiplexing (TCM) subscriber-line transmission systems in the integrated services digital network (ISDN). It consists of two digital filter blocks, called the √f equalizer and the bridged-tap equalizer, and gain- and timing-control blocks. The √f equalizer achieves the processing speed of 20 MOPS by a powerful arithmetic unit composed of multipliers and adders. It provides an FIR filter with nine taps which satisfies an accurate equalization for the 1.92-Msample/s data. The bridged-tap equalizer performs both the adaptation algorithm of the √f equalizer and the decision-feedback algorithm. The microprogram control enables the hardware to be shared between these functions and assures flexibility. Algorithm-oriented instructions implemented in the ALU realize high-speed execution of the decision-feedback algorithm with a simple architecture. The 11.3-mm×8.5-mm chip with 61 K transistors has been implemented using 1.5-μm double-metal-layer CMOS technology     

A new equalizer for multitone systems without guard time

We propose a new, low-complexity frequency-domain equalizer, which, in the absence of a guard interval, utilizes redundancy in the frequency domain to completely eliminate intersymbol and interchannel interference. Simulation results show that the new equalization scheme has at least the same potential compared to conventional DMT/OFDM while offering the shortest possible latency at a reasonable complexity enhancement     

A high-performance custom standard-cell CMOS equalizer for telecommunications applications

A high-performance CMOS programmable amplitude equalizer has been implemented with a dynamic range greater than 100 dB and supply rejection greater than 60 dB at 1 kHz from both supplies. This was accomplished using a balanced architecture. A nonreturn-to-zero sample-and-hold circuit is proposed that is also parasitic-insensitive. The circuits are implemented using a standard-cell methodology.     

A CMOS line equalizer for a digital subscriber loop

An adaptive line equalizer for a 200-kb/s digital subscriber loop is developed in the form of a monolithic LSI and implemented using 2.5-/spl mu/m CMOS technology. Most analog portions consist of switched-capacitor circuits successfully designed to minimize power consumption, the amount of hardware, and off-chip components. The main features of the LSI equalizer are an /spl radic/f step equalizer, a five-tap decision-feedback equalizer using /spl Delta/M D/A conversion, a newly developed wave difference method (WDM), tankless timing extraction PLL, and a line driver. Consequently, the LSI can equalize a 52-dB line loss with four bridge taps; it dissipates only 67 mW, and the chip area is 5.7/spl times/5.9 mm/SUP 2/.     

A 50 MHz eight-tap adaptive equalizer for partial-response channels

A new architecture for digital implementation of the adaptive equalizer in Class IV partial-response maximum likelihood (PRML) channels employing parallelism and pipelining is described. The architecture was used in a prototype integrated circuit in a 1.2 μm CMOS technology to implement an eight-tap adaptive equalizer and Viterbi sequence detector which consumes a total of 70 mW from a 3.3 V supply operating at an input sampling rate of 50 MHz