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1.
High speed analogue-to-digital conversion using a photonic time-stretch preprocessor followed by an electronic digitiser is demonstrated. The preprocessing increases the effective sampling rate and input bandwidth of the digitiser. The system exhibits 30 Gsample/s sampling rate with 26 dB signal-to-noise ratio over a 4 GHz bandwidth 相似文献
2.
A fully-differential, 10-b, 40-Msample/s pipelined analog-to-digital converter (ADC) has been developed and tested. The converter exhibits a signal-to-(noise+distortion) ratio (SNDR) of 57.1 dB and consumes <400 mW of power from a single 5 V supply. The converter can digitize not only a fully-differential but also a single-ended input signal over a wide input range with little variation in converter performance. In addition, a full-power bandwidth (FPBW) of >250 MHz is made possible with the open-loop sampling scheme 相似文献
3.
A new architecture for a CMOS A/D converter overcomes many of the known problems in the parallel operation of multiple pipelined stages. The input signal is sampled in one channel, and after quantization to 4 b, the residue is distributed into many channels. A prototype implemented in 1-μm CMOS achieves 60 dB signal-to-noise plus distortion ratio (SNDR) at low conversion rates, with a resolution bandwidth of greater than 20 MHz. The SNDR drops by 3 dB at a 95 MHz conversion rate, and the bandwidth remains the same 相似文献
4.
Jaesik Lee Roux P. Ut-Va Koc Link T. Baeyens Y. Young-Kai Chen 《Solid-State Circuits, IEEE Journal of》2004,39(10):1671-1679
A 5-b flash A/D converter (ADC) is developed in an 0.18-/spl mu/m SiGe BiCMOS that supports sampling rates of 10 Gsample/s. The ADC is optimized to operate in digital equalizers for 10-Gb/s optical receivers, where the ADC has to deliver over three effective number of bits (ENOBs) at Nyquist. A fully differential flash ADC incorporating a wide-band track-and-hold amplifier (THA), a differential resistive ladder, an interpolation technique, and a high-speed comparator design is derived to resolve the aperture jitter and metastability error. The ADC achieves better than 4.1 effective bits for lower input frequencies and three effective bits for Nyquist input at 10 GS/s. The ADC dissipates about 3.6 W at the maximum clock rate of 10 GS/s while operating from dual -3.7/-3V supplies and occupies 3/spl times/3mm/sup 2/ of chip area. 相似文献
5.
A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter 总被引:3,自引:0,他引:3
van den Bosch A. Borremans M.A.F. Steyaert M.S.J. Sansen W. 《Solid-State Circuits, IEEE Journal of》2001,36(3):315-324
In this paper, a 10-bit 1-GSample/s current-steering CMOS digital-to-analog (D/A) converter is presented. The measured integral nonlinearity is better than ±0.2 LSB and the measured differential nonlinearity lies between -0.08 and 0.14 LSB proving the 10-bit accuracy. The 1-GSample/s conversion rate has been obtained by an, at transistor level, fully custom-designed thermometer decoder and synchronization circuit. The layout has been carefully optimized. The parasitic interconnect loads have been estimated and have been iterated in the circuit design. A spurious-free dynamic range (SFDR) of more than 61 dB has been measured in the interval from dc to Nyquist. The power consumption equals 110 mW for a near-Nyquist sinusoidal output signal at a 1-GHz clock. The chip has been processed in a standard 0.35-μm CMOS technology and has an active area of only 0.35 mm2 相似文献
6.
This paper presents a 10-bit 100-MSample/s analog-to-digital(A/D) converter with pipelined folding architecture.The linearity is improved by using an offset cancellation technique and a resistive averaging interpolation network.Cascading alleviates the wide bandwidth requirement of the folding amplifier and distributed interstage track/hold amplifiers are used to realize the pipeline technique for obtaining high resolution.In SMIC 0.18μm CMOS,the A/D converter is measured as follows:the peak integral nonlinearity and differential nonlinearity are±0.48 LSB and±0.33 LSB,respectively.Input range is 1.0 VP-P with a 2.29 mm2 active area.At 20 MHz input @ 100 MHz sample clock,9.59 effective number of bits,59.5 dB of the signal-to-noise-and-distortion ratio and 82.49 dB of the spurious-free dynamic range are achieved.The dissipation power is only 95 mW with a 1.8 V power supply. 相似文献
7.
采用流水折叠结构设计了一种10位100-MSample/s A/D转换器。失调取消技术和电阻平均插值网络提高了转换器的线性度。级联结构放宽了折叠放大器的带宽要求,采用分布式级间跟踪保持放大器实现流水线技术来获得更高的转换精度。基于SMIC 0.18 μm CMOS工艺的测试结果如下:INL和DNL的峰值分别为0.48 LSB and 0.33 LSB。输入电压范围VP-P为1.0 V,芯片面积2.29 mm2。100 MHz采样,20 MHz输入信号下,ENOB为9.59位,SNDR为59.5 dB,SFDR为82.49 dB。1.8V电源电压下功耗仅为95 mW。 相似文献
8.
A 10-bit 200-MS/s CMOS parallel pipeline A/D converter 总被引:1,自引:0,他引:1
This paper describes a 10-bit 200-MS/s CMOS parallel pipeline analog-to-digital (A/D) converter that can sample input frequencies above 200 MHz. The converter utilizes a front-end sample-and-hold (S/H) circuit and four parallel interleaved pipeline component A/D converters followed by a digital offset compensation. By optimizing for power in the architectural level, incorporating extensively parallelism and double-sampling both in the S/H circuit and the component ADCs, a power dissipation of only 280 mW from a 3.0-V supply is achieved. Implemented in a 0.5-μm CMOS process, the circuit occupies an area of 7.4 mm2. The converter achieves a differential nonlinearity and integral nonlinearity of ±0.8 LSB and ±0.9 LSB, respectively, while the peak spurious-free-dynamic-range is 55 dB and the total harmonic distortion better than 46 dB at a sampling rate of 200 MS/s 相似文献
9.
Ito M. Miki T. Hosotani S. Kumamoto T. Yamashita Y. Kijima M. Okuda T. Okada K. 《Solid-State Circuits, IEEE Journal of》1994,29(12):1531-1536
A 10 bit CMOS A/D converter with 3 V power supply has been developed for being integrated into system VLSI's. In this A/D converter, redundant binary encoders named “twin encoders” enhance tolerance to substrate noise, together with employing differential amplifiers in comparators. The bias circuit using a replica of the amplifier is developed for biasing differential comparators with 3 V power supply. Subranging architecture along with a multilevel tree decoding structure improves dynamic performance of the ADC at 3 V power supply. The A/D converter is fabricated in double-polysilicon, double-metal, 0.8 μm CMOS technology. The experimental results show that the ADC operates at 20 MS/s and the twin encoders suppress the influence of substrate noise effectively. This ADC has a single power supply of 3 V, and dissipates 135 mW at 20 MS/s operation 相似文献
10.
10 bit 200 MS/s CMOS D/A converter employing high-speed limiter 总被引:1,自引:0,他引:1
Seung-Chul Lee Min-Hyung Cho Hyun-Kyu Yoo 《Electronics letters》2002,38(23):1407-1408
A 10 bit 200 MS/s CMOS current-steering digital-to-analogue converter (DAC) employing a new voltage limiter to reduce the feedthrough of the control signals is presented. For high-speed operation of the limiter, a design technique based on the parasitic capacitor of a PMOS transistor is proposed. At 200 MS/s, a spurious-free dynamic range of 65 dBc for a 40 MHz output signal has been achieved from the proposed DAC. 相似文献
11.
Miki T. Kouno H. Kumamoto T. Kinoshita Y. Igarashi T. Okada K. 《Solid-State Circuits, IEEE Journal of》1994,29(4):516-522
A BiCMOS A/D converter using a “differential voltage subconverter,” which directly converts a voltage difference of complementary analog inputs to a digital code, is described. Fully differential architecture has advantages in immunity of common-mode error and in reduction of supply voltage. This differential-voltage subconverter realizes the fully differential A/D conversion without using interpolation technique. This subconverter is free from CR delay caused in the ladder resistors. Circuit techniques for high-accuracy conversion with single 5-V power supply, such as compensation technique for VBE modulation in emitter degeneration amplifier, are also described. A 10-b A/D converter is fabricated in a 0.8-μm BiCMOS process with fT of 9 GHz. It successfully operates at 50 MS/s with 500-mW power consumption and with 5-V single supply 相似文献
12.
Fernandes J. Lewis S.R. Mallinson A.M. Miller G.A. 《Solid-State Circuits, IEEE Journal of》1988,23(6):1309-1315
A microprocessor-compatible, 14-bit, 10-μs subranging analog-to-digital converter with a sample/hold amplifier (SHA) is described. The chip architecture is based on a five-cycle subranging flash technique using both analog and digital error correction. The conversion speed is enhanced by an analog correction method, whereby redundant bit currents allow digital/analog converter updates without changing bits determined in previous cycles. The residue signal path uses simple circuitry and is highly differential. Prototype performance has been demonstrated 相似文献
13.
This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 μm CMOS technology which achieves a power dissipation of 35 mW at full speed operation. Circuit techniques used to achieve this level of power dissipation include digital correction to allow the use of dynamic comparators, and optimum scaling of capacitor values through the pipeline. Also, to be compatible with low voltage mixed-signal system environments, a switched capacitor (SC) circuit in each pipeline stage is implemented and operated at 3.3 V with a new high-speed, low-voltage operational amplifier and charge pump circuits. Measured performance includes 0.6 LSB of INL, 59.1 dB of SNDR (Signal-to-Noise-plus-Distortion-Ratio) for 100 kHz input at 20 Msample/s. At Nyquist sampling (10 MHz input) SNDR is 55.0 dB. Differential input range is ±1 V, and measured input referred RMS noise is 220 μV. The power dissipation at 1 MS/s is below 3 mW with 58 dB of SNDR 相似文献
14.
A modified RSD algorithm has been implemented in a switched-current pipelined A/D converter. The offset insensitivity of the RSD Converter reduces the effect of several nonidealities proper to current copier cells. Moreover, the benefits resulting from the large tolerances inherent to the RSD algorithm and the pipelined architecture result in an improved conversion rate. Measurements on a first prototype give an integral nonlinearity error less than 0.8 LSB for 10-bit accuracy. Power dissipation is 20 mW and silicon area is 2.5 mm2 . The measured sampling rate is 550 kS/s. It is an improvement by a factor of twenty compared to known equivalent CMOS switched-current converters. It is nevertheless still well below the predicted conversion rate of 4.5 MHz, which should be obtained once this A/D converter is integrated into an analog front-end. Full compatibility with standard digital technologies makes this kind of converter attractive for low power, medium-fast converters with 10-bit accuracy 相似文献
15.
《Solid-State Circuits, IEEE Journal of》1973,8(6):404-408
A monolithic 10-b plus sign D/A converter has been developed that incorporates all necessary circuit functions including voltage reference and internally compensated high-speed output op amp in a single 82/spl times/148 mil chip. A unique logic switch and current source configuration achieves 0.05 percent nonlinearity with /spl plusmn/10 V compliance current output option as well as true or complementary binary coding. The design constraints and area requirements for scaling of current source emitter areas are reduced by using a new active current-splitting technique. The circuit features a 1.5 /spl mu/s settling time voltage output and sign-magnitude coding. 相似文献
16.
The continuous calibration of high-linearity, highspeed analog/digital converters (ADCs) can minimize system complexity by allowing a single converter to maintain its accuracy over time. This paper introduces a continuous calibration technique for pipelined and successive approximation ADCs that avoids some of the limitations of earlier designs by performing the calibration in the analog domain. The calibration is made transparent to the overall system by employing an extra stage that is calibrated outside of the main converter's operation and periodically substituted for a stage within the main converter. A 12-b, pipelined ADC employing this architecture has been integrated in a 0.5-μm, single-poly, quadruple-metal, 3.3-V CMOS technology. The measured dynamic performance indicates that at a 10-MHz sampling rate, the circuit achieves a peak signal-to-noise-plus-distortion ratio of 67 dB and a total harmonic distortion of -77 dR for a 4.8-MHz input. The total power dissipated by the prototype is 335 mW, and its active area is 3.71×3.91 mm2 相似文献
17.
A 10-b 20-Msample/s analog-to-digital converter 总被引:1,自引:0,他引:1
Lewis S.H. Fetterman H.S. Gross G.F. Jr. Ramachandran R. Viswanathan T.R. 《Solid-State Circuits, IEEE Journal of》1992,27(3):351-358
A 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9-μm CMOS technology is described. The converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-and-distortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies a 8.7 mm2 and dissipates 240 mW 相似文献
18.
Kimura H. Matsuzawa A. Nakamura T. Sawada S. 《Solid-State Circuits, IEEE Journal of》1993,28(4):438-446
A monolithic 10-b A/D converter that realized a maximum conversion frequency of 300 MHz is described. Through the development of the interpolated-parallel scheme, the severe requirement for the transistor V be matching can be alleviated drastically, which improves differential nonlinearity (DNL) significantly to within ±0.4 LSB. Furthermore, an extremely small input capacitance of 8 pF can be attained, which translates into better dynamic performance such as SNR of 56 dB and THD of -59 dB for an input frequency of 10 MHz. Additionally, the folded differential logic circuit has been developed to reduce the number of elements, power dissipation, and die area drastically. Consequently, the A/D converter has been implemented as a 9.0-mm×4.2-mm chip integrating 36 K elements, which consumes 4.0 W using a 1.0-μm-rule, 25-GHz f t, double-polysilicon self-aligned bipolar technology 相似文献
19.
本文设计了一种可满足视频速度应用的低电压低功耗10位流水线结构的CMOS A/D转换器.该转换器由9个低功耗运算放大器和19个比较器组成,采用1.5位/级共9级流水线结构,级间增益为2并带有数字校正逻辑.为了提高其抗噪声能力及降低二阶谐波失真,该A/D转换器采用了全差分结构.全芯片模拟结果表明,在3V工作电压下,以20MHz的速度对2MHz的输入信号进行采样时,其信噪失调比达到53dB,功率消耗为28.7mW.最后,基于0.6μm CMOS工艺得到该A/D转换器核的芯片面积为1.55mm2. 相似文献