Superconductive A/D converters

A number of superconductive A/D (analog/digital) converter designs that show promise for superiority in high-bandwidth or high-resolution applications are known. On the high-resolution side, counting-type converters appear quite attractive. Voltage-to-frequency and tracking A/D converters are reviewed in this category. On the ultra-high-bandwidth side (greater than about 1 GHz) the parallel-type A/D converters seem to be advantageous. A number of parallel periodic-threshold A/D converters that have been attempted over the years as well as a fully parallel (2^N-1 comparators) A/D converter are reviewed     

Design and experiments on a high-resolution multi-gigahertzsampling rate superconducting A/D converter

Work towards a high-resolution multi-gigahertz sampling rate A/D converter is presented. A brief review of the overall architecture which consists of a coarse section and an interpolator section is given. Experiments on two designs for the coarse sections are discussed. One is a 6-bit A/D converter built with two-leaf phase tree periodic comparators. Asynchronous beat frequency tests at 2.01 GHz sampling rates indicate this circuit is capable of 6 bits of resolution at 2 GHz input bandwidth. The resolution falls off to about 5 bits at 4 GHz and 4 bits at 6 GHz. The other approach involves two related novel single threshold comparators with large dynamic range. For one of the comparators, dynamic range in excess of 60 db is demonstrated by transfer characteristic and input current noise measurements, while the other showed 54 db of dynamic range. A chain of 15 comparators based on one of the designs has been designed and tested. Asynchronous beat frequency tests at 2.01 GHz sampling rates show a monotonic response for input frequencies up to 8 GHz. Threshold offsets due to flux trapping limited the resolution in this set of experiments to about 5 bits. Experiments on a periodic interpolator circuit based on the two-leaf phase tree comparator are also presented. The results suggest that it should be possible to obtain 10-bits of resolution with this approach     

High-speed experiments on a QFP-based comparator for ADCs with18-GHz sample rate and 5-GHz input frequency

The authors report on the high-speed operation of a superconducting comparator circuit, based on coupling the quantum flux parametron (QFP) to an RF SQUID, which can be used to build a flash-type analog-to-digital converter (ADC). Simulations of this circuit show that it is expected to achieve operation with input signal bandwidths greater than 4 GHz and with a dynamic range equal to at least 4 b of resolution. A QFP-based comparator fabricated with a process using NbN/Pb-alloy Josephson junctions of 5 μm by 5 μm and a current density of 100 A/cm² has been examined to evaluate the properties of the QFP-ADC. Analog-to-digital conversion of the comparator has been observed with a QFP activation frequency up to 18.2 GHz. By employing a sampling method, input signals with frequencies up to 5.4 GHz have also been digitized     

Static linearity error analysis of subranging A/D converters

An 8- to 10-bit CMOS A/D converter with a conversion rate of more than 16 megasample/second is required in consumer video systems. Subranging architecture is widely used to realize such A/D converters. This architecture, however, exhibits a reference voltage error caused by resistor ladder loadings. The error has been discussed with respect to a flash A/D converter by Dingwall. However, it can not be applied for a subranging A/D converter as it is. The analysis of this error is very important in realizing the desired accuracy of a subranging A/D converter. This paper describes a static analysis to improve the linearity, and reports the results of this analysis for two typical types, one with individual comparator arrays for coarse and fine A/D conversions, and the other with the same comparator array for both conversions. This analysis makes it clear that a subranging A/D converter has unique saw-tooth characteristic in fine linearity errors. Furthermore, this analysis clarifies what conditions are necessary to achieve the desired accuracy. It is necessary, for example, that the product of the total input capacitance of the comparators C, the conversion rate f _sand the total ladder resistance R is less than 0.03 in A/D converters with individual comparator arrays and 0.016 in A/D converters with the same comparator array in order to achieve 10-bit accuracy.     

A 5-GHz SiGe HBT return-to-zero comparator for RF A/D conversion

This paper presents a monolithic comparator implemented in a 0.5-μm SiGe heterojunction bipolar transistor (HBT) process. The SiGe HBT process provides HBT npn transistors with maximum f_T over 40 GHz and f_max over 55 GHz. The comparator circuit employs a resettable slave stage, which was designed to produce return-to-zero output data. Operation with sampling rates up to 5 GHz has been demonstrated by both simulation and experiments. The comparator chip attains an input range of 1.5 V, dissipates 89 mW from a 3-V supply, and occupies a die area of 407×143 μm². The comparator is intended for analog-to-digital (A/D) conversion of 900 MHz RF signals     

Design of concurrent error detectable current-mode A/D converters for real-time applications

Analog MOS circuits are becoming increasingly sophisticated in terms of checking and correcting themselves. Self-correcting, self-compensating, or self-calibrating techniques eliminate errors traditionally associated with analog circuits. For real-time applications, however, it is rather difficult to achieve validation of the data generated from analog-to-digital (A/D) converters in the presence of faulty switching element(s). Conventionally, the validation is accomplished by using a high resolution and high accuracy D/A converter and a window comparator; i.e., the validation must highly depend on the reliability of both the D/A converter and the window comparator. In this paper, a novel current-mode A/D converter design with concurrent error detection (CED) capability is presented. The A/D converter does not need well-matched components and high-gain amplifiers. Results show that the proposed design can detect all the transient faults and most of the permanent faults. The proposed design allows users to easily switch to the normal operation mode where CED capability is not used, without causing any performance degradation.     

Error suppressing encode logic of FCDL in a 6-b flash A/D converter

A 6-b, 166-Ms/s BiCMOS flash A/D converter was fabricated using a folded cascoded differential logic (FCDL). This FCDL reduces glitch errors caused by comparator metastability and improves encoder operation speed. The measured error rates of a chip implemented in a 0.7-μm, f _t=12 GHz BiCMOS was less than 10^-10 times/sample. Without power-consuming highspeed track and hold circuit, the FCDL achieved low error rate and low power consumption of 505 mW at a 5.0-V power supply     

A 25-Ms/s 8-bit CMOS A/D converter for embedded application

The design of an 8-bit CMOS A/D converter is described which is intended for embedded operation in VLSI chips for video applications. The requirements on accuracy are analyzed and a comparator circuit is shown which realizes a high bandwidth. The full-flash architecture operates on wideband signals like CVBS in television systems. The A/D converter core measures 2.8 mm² in a 1 μm CMOS process. The embedded operation of the A/D converter is illustrated on a video line-resizing chip     

A monolithic charge-balancing successive approximation A/D technique

A new multiple-differential-voltage input, MOS, sampled-data, `charge-balance' comparator which can `weight' or scale each of many input voltage pairs has been developed. This comparator easily allows a differential analog input voltage capability on a monolithic A/D converter and greatly reduces the required number of resistors and decoding switches of a potentiometric successive approximation register (SAR) A/D design. An 8 bit converter has been built which uses 20 Rs and 32 switches as compared to the 256 Rs and 512 switches of a standard 2/SUP N/R ladder design. Measurements made on the 8 bit A/D converter are reported and indicate that at least 12 bit converters are possible with this technique. Therefore, a 13 bit converter has been designed which exhibits even greater component reductions-33 Rs and 64 switches instead of 8192 Rs and 16384 switches. A simple interface to microprocessors is provided for both converters which makes use of the standard logic signals of the control bus where the A/D is designed to appear as memory or an I/O port to the microprocessor. A new flexible reference voltage circuit is presented which, in combination with the analog differential input voltage feature, can accommodate arbitrary analog input voltage spans with any desired zero scale offset.     

Design, Fabrication, and Evaluation of 2 and 3-Bit GaAs MESFET Analog-to-Digital Converter IC's

The analog-to-digital converter (A/D) is a critical component of a signal processing system. GHz-rate A/D's will be required in many future systems. While Si bipolar based A/D's can easily meet 4-6-bit resolution requirements, excessive power dissipation (1 W per bit) limits their operation to 100-400-MHz sampling rates. Recently, GaAs MES-FET's have demonstrated high frequency operation with relatively low power dissipation. This paper describes the design of 2- and 3-bit A/D's using GaAs MESFET's. Monolithic integrated A/D circuits were fabricated and successfully operated at gigahertz sampling rates. This sampling rate is the highest reported for any AD technology at room temperature. The power dissipation is 150-200 mW per bit. With further improvements in comparator sensitivity, the design can be extended to 4-bit A/D for GHz rate operation.     

A high-speed and high-resolution CMOS comparator with three-stage preamplifier

The accuracy of A/D and D/A converters depend largely upon their inner comparators. To guarantee 12-bit high resolution for an A/D converter, a precise CMOS comparator consisting of a three-stage differential preamplifier together with a positive feedback latch is proposed. Circuit structure, gain, the principle of input offset voltage storage and latching time constant for the comparator will be analyzed and optimized in this article. With 0.5 μm HYNIX mixed signal technology, the simulation result shows that the circuit has a precision of 400 μV at 20 MHz. The test result shows that the circuit has a precision of 600 μV at 16 MHz, and dissipates only 78 μW of power dissipation at 5 V. The size of the chip is 210 × 180 μm2. The comparator has been successfully used in a 10 MSPS 12-bit A/D converter. The circuit can be also used in a less than 13-bit A/D converter.     

A single-chip A/D converter in PMOS technology for digital voltmeter applications

A single-chip A/D converter in p-channel MOS enhancement depletion-mode technology is presented, using a single-slope conversion technique. The analog part consists of a constant-current source and a comparator with internal digitally corrected offset. The A/D converter for a 3/SUP 1///SUB 2/-digit DVM can be operated with only two external components (integration capacitor and oscillator capacitor) and is mounted in a DIL 18 package.     

Design, fabrication, and evaluation of 2- and 3-bit GaAs MESFET analog-to-digital converter IC's

the analog-to-digital converter (A/D) is a critical component of a signal processing system. GHz-rate A/D's will be required in many future systems. While Si bipolar based A/D's can easily meet 4-6-bit resolution requirements, excessive power dissipation (1 W per bit) limits their operation to 100-400-MHz sampling rates. Recently, GaAs MESFET's have demonstrated high frequency operation with relatively low power dissipation. This paper describes the design of 2- and 3-bit A/D's using GaAs MESFET's. Monolithic integrated A/D circuits were fabricated and successfully operated at gigahertz sampling rates. This sampling rate is the highest reported for any A/D technology at room temperature. The power dissipation is 150-200 mW per bit. With further improvements in comparator sensitivity, the design can be extended to 4-bit A/D for GHz rate operation.     

一种用于半并行A/D转换器的比较器设计

简要介绍了半并行结构的A/D转换器原理。针对该结构的A/D转换器,提出了一种能自动校零、迟滞、全差分输入及多级前置放大的比较器。解决了输入失调电压、噪声环境下单转换、电荷注入、带宽、转换速度等问题。给出了应用该比较器的0.6μm CMOS半并行A/D转换器的性能。结果表明,设计的比较器能使丰并行ADC的DNL和INL小于±0.5 LSB,SNR大于48dB。     

A 1.5 V, 8 mW, 8 b, 15 Msps BiCMOS A/D Converter

A 1.5 V 8 mW BiCMOS video A/D converter has been developed by using a BiCMOS pumping comparator. Combining Bipolar high-speed and good-matching characteristics with CMOS switched capacitor techniques, this A/D converter is suitable for use in battery-operated multimedia terminals.     

A 16-GHz ultra-high-speed Si-SiGe HBT comparator

This paper presents an improved master-slave bipolar Si-SiGe HBT comparator design for ultra-high-speed data converter applications. The latch is maintained during the track stage facilitating quick transition back to the latch stage, increasing the sampling speed of the comparator. Implemented in a 0.5-/spl mu/m 55-GHz BiCMOS Si-SiGe process, this comparator consumes approximately 80 mW with sampling speeds up to 16 GHz.     

A precision variable-supply CMOS comparator

Several new techniques are presented for the design of precision CMOS voltage comparator circuits which operate over a wide range of supply voltages. Since most monolithic A/D converter systems contain an on-chip voltage reference, techniques have been developed to replicate the reference voltage in order to provide stable supply-independent DC bias voltages, and controlled internal voltage swings for the comparator. These techniques are necessary in order to eliminate harmful bootstrapping effects which can potentially occur in all AC coupled MOS analog circuits. An actively controlled biasing scheme has been developed to allow for differentially autozeroing the comparator for applications in differential A/D converter systems. A general approach for selecting the gain in AC-coupled gain stages is also presented. The comparator circuit has been implemented in a standard metal-gate CMOS process. The measured comparator resolution is less than 1 mV, and the allowable supply voltages range from 3.5 to 10 V.     

A behavioral model of A/D converters using a mixed-mode simulator

A mixed-mode behavioral model of analog-to-digital (A/D) converters is described. A generalized model structure is introduced. The basic function of an A/D converter is to convert an analog voltage into a digital code, for example, a binary number. Three conversion methods (successive approximation, flash, and dual integration) which are commonly used in A/D converters are modeled and can be selected simply by specifying a parameter of the model. For brevity, only the successive-approximation method is described. The modeling considerations of various parts in the A/D converter, including the input amplifier, D/A converter, comparator, and the synchronization problem, are described. The model has been implemented in the Saber mixed-mode simulator. Simulation results are given     

A monolithic voltage-comparator array for A/D converters

Describes a monolithic circuit consisting of an array of 8 voltage comparators, a resistive voltage divider, and associated logic circuits. Intended as an encoding component for high-speed parallel A/D converters, this `3-bit quantizer' uses regeneration for voltage gain and signal storage. A Gray-code output minimizes the problem of comparator indecision. The principal error sources are an asymmetry-induced comparator offset with 2-mV standard deviation and a thermally induced offset of a much as /spl plusmn/2.5 mV, dependent on signal history. The quantizer has been incorporated in an experimental 6-bit 200 megasample/s (MS/s) A/D converter.     

A CMOS 8-Bit High-Speed A/D Converter IC

A novel high-speed low-power CMOS balanced comparator circuit is proposed and implemented in an 8M fully parallel analog-to-digital (A/D) converter IC. A 20-MHz sampling rate with 350-mW power dissipation from a single 5-V power supply has been realized. Integral linearity of /spl plusmn/ 1/2 LSB to 8-bit conversion has been achieved through intensive transistor dimension optimization applied to the comparator circuit, instead of employing an offset canceling technique.