一种用于模拟电路修调的EEPROM电路

介绍了一种用在模拟电路中修调的EEPROM电路.该电路采用一种新型的单层多晶EEPROM结构,与传统的双栅EEPROM结构相比,该结构与数字CMOS工艺兼容,成本低、成品率高.使用在一个基准电压电路中时,其基准电压的调节范围达到±4.82%,调节精度达到4mV.EEPROM修调电路可广泛应用于各种高精度需求的电路中.     

一种高精度片内电阻校准电路设计

设计了一种适用于40 Ω~100 Ω内调节的高精度片内电阻校准电路,该电路可精确调整因工艺波动产生变化的片内电阻阻值。片内电阻校准电路采用模数混合控制方法,即以片外电阻为基准,采用高精度回滞比较器比较片内和片外电阻转换的电压值,采用自适应控制电路精确调整电阻阵列开关,使得片内电阻的阻值与片外基准电阻的阻值相等。电路基于40 nm CMOS工艺进行设计,仿真结果表明,比较器的电压比较阈值最小为2 mV,电路实现40 Ω~100 Ω内电阻阻值可调节,校准误差小于2%。     

一种高精度CMOS带隙基准电压源设计

介绍了带隙基准电压源的基本原理,设计了一种高精度带隙基准电压源电路.该电路采用中芯国际半导体制造公司0.18 μm CMOS工艺.Hspice仿真表明,基准输出电压在温度为-10～120 ℃时,温度系数为6.3×10-6/℃,在电源电压为3.0～3.6 V内,电源抑制比为69 dB.该电压基准在相变存储器芯片电路中,用于运放偏置和读出/写驱动电路中所需的高精度电流源电路.     

高精度CMOS带隙基准电压源电路设计

设计了一种应用于集成稳压器的高精度带隙基准电压源电路。采用共源共栅电流镜结构以及精度调节技术,有效提高了电压基准的温度稳定性和输出电压精度。经Hynix 0.5μm CMOS工艺仿真验证表明,在25℃时,温度系数几乎为零,基准电压随电源电压变化小于0.1 mV;在-40~125℃温度变化范围内,基准电压变化最大4.8 mV,满足设计指标要求。     

一种大电流高精度集成汽车电压调节器

介绍了一种大电流高精度集成汽车电压调节器的设计原理及电路结构.该集成汽车电压调节器由基准电压源、比较放大器、保护电路和调整管等单元组成.该电路采用硅双极型对通隔离功率IC工艺研制,具有过流/过压、过热保护功能,以及电压调节精度高、调整电流大等特点.     

几种典型的电流源结构和高精度基准电流源的设计

本文介绍并分析了几种典型的电流源结构,并设计了一种具有良好稳定性和高精度的CMOS基准电流源.在高精度的基准电流源电路中使用了带隙电路,使电路获得一个不受电源电压、温度和工艺参数影响的基准电压,然后通过电压-电流转换电路获得稳定的基准电流.HSPICE的仿真结果表明:当温度从-55℃到125℃变化时,电流输出仅变化了0.004.     

温度系数可调的基准电压产生电路研究与设计

由于TFT-LCD显示屏的物理特性随温度而发生变化,驱动电路必须提供具有相同温度特性的驱动电压,以补偿显示屏的温度特性,进而提高显示画质。文章研究并设计了一种用于TFT-LCD彩屏手机驱动芯片的基准电压产生电路,其输出电压的绝对值与温度系数可编程调节,从而可实现与液晶显示屏的温度特性相匹配。介绍了该电路的各子模块电路,包括偏置电路、带隙基准电路和输出电压调节电路,详细分析了带隙基准电路所产生的基准电压的温度系数及其调节原理。用Hspice对采用0.25μmCMOS工艺设计的电路进行了仿真。仿真结果表明,基准电压的温度系数可从-1.24~1.13mV/℃变化,输出电压的绝对值可从1.8~2.1V调节,最大可提供负载电流40mA。     

一种输出可调的高精度开关电容基准电压源

设计了一种输出可调的高精度开关电容基准电压源,与现有基准电压源相比,该电路可在圆片阶段利用熔丝修调校正技术对基准电压进行修正,降低芯片制造成本。电路采用开关电容结构降低运放输入失调电压对电路的影响,具有高精度的特点。将该基准电压源应用于一款语音编解码芯片,测试结果表明,其在25℃下输出基准电压为2.355V,在-40～80℃范围内温度系数为19.46×10^-6/℃。     

高精度电流源电路的设计

提出了一种高精度的电流源电路,通过V/I变换,将由带隙基准电压电路产生的与温度和电源电压无关的带隙基准电压转换成与温度和电压无关的高精度基准电流,并通过高精度电流镜结构产生所需的镜像电流,有效地抑制了由于温度、电源电压、负载阻抗的变化及干扰对电流源的影响.用HSPICE对改进前后的电路进行对比测试,结果表明,改进后电流镜的镜像误差约减小90%,电流源的精度显著提高.     

一种全MOS高精度基准电压源电路

基于0.35 μm CMOS工艺,设计了一种高精度基准电压源电路。采用全MOS管实现电路,避免使用大电阻以减小芯片面积。采用新型可变电阻方法,实现了精确补偿。采用两级式基准电压源,提高了电源抑制比。使用Cadence Virtuoso对该基准电压源进行仿真。结果表明,当温度范围 为-40 ℃~125 ℃ 时,基准电压为1.146 V,温度系数为1.025×10-5 ℃-1。在27 ℃时,静态电流为6.57 μA,PSRR分别为-96.64 dB @100 Hz、-93.94 dB@10 kHz。电源电压在2.9~5 V范围变化时,基准电压的线性调整度为0.047％。该电路适用于低功耗、高精度的模拟集成电路。     

A curvature-corrected low-voltage bandgap reference

A curvature-corrected bandgap reference that can function at supply voltages as low as 1 V, at a supply current of only 100 μA, is presented. After trimming, this bandgap reference has a temperature coefficient (TC) of ±4 p.p.m./°C. The reference voltage is about 200 mV and it can easily be adjusted to higher values. The temperature range of this circuit is from 0 to 125°C. This bandgap reference is realized using a standard bipolar process with base-diffused resistors     

Trimming process and temperature variation in second-order bandgap voltage reference circuits

This paper presents the design and experimental performance of a second-order bandgap voltage reference integrated circuit (IC). Experimentally observed nominal reference voltage at room temperature is 1.150 V with best temperature performance of 3 mV variation over −40 to 120 °C. A 5-bit resistor trimming is used to compensate the variation of reference voltage due to layout mismatch and process variation. A trimming methodology is described in this paper to optimize both the temperature performance and reduce the variation of the room temperature voltage over different samples. Even with best temperature performance trim-code, the absolute variation in reference voltage over 20 samples is 85 mV which is trimmed to ±11 mV (1.3%) using the proposed trimming methodology. The second-order bandgap circuit is designed in a 0.5 μm BiCMOS process with less than 50 μA current consumption.     

Low-power bandgap references featuring DTMOSTs

This paper describes two CMOS bandgap reference circuits featuring dynamic-threshold MOS transistors. The first bandgap reference circuit aims at application in low-voltage, low-power ICs that tolerate medium accuracy. The circuit runs at supply voltages down to 0.85 V while consuming only 1 μW; the die area is 0.063 mm² in a standard digital 0.35-μm CMOS process. The second bandgap reference circuit aims at high accuracy operation (σ=0.3%) without trimming. It consumes approximately 5 μW from a 1.8-V supply voltage and occupies 0.06 mm² in a standard 0.35-μm CMOS process     

A CMOS bandgap reference for differential signal processing

A switched-capacitor fully differential bandgap reference that uses a standard double-poly CMOS process is presented. It generates a differential reference voltage of 6.2 V with a standard deviation of about 24 mV and a typical temperature stability of 15.2 p.p.m./°C over an extended temperature range from -40 to +85°C. These performance results are obtained without using any trimming in mass production. The bandgap reference only occupies 730 mil² and dissipates 4.8 mW at±5-V power supplies. A measured power supply rejection of about 90 dB until 500 kHz is the best ever reported at high frequency     

一种新型CMOS电流模带隙基准源的设计

设计了一种新型电流模带隙基准源电路和一个3bit的微调电路。该带隙基准源可以输出可调的基准电压和基准电流,避免了在应用中使用运算放大器进行基准电压放大和利用外接高精度电阻产生基准电流的缺点,同时该结构克服了传统电流模带隙基准源的系统失调、输出电压的下限限制以及电源抑制比低等问题。该带隙基准源采用0.5μm CMOS混合信号工艺进行实现,有效面积450μm×480μm;测试结果表明在3 V电源电压下消耗1.5mW功耗,电源抑制比在1 kHz下为72dB,当温度从-40～85°C变化时,基准电压的有效温度系数为30×10-6V/°C。该带隙基准电路成功应用在一款高速高分辨率模数转换器电路中。     

A CMOS bandgap reference without resistors

This paper describes a bandgap reference fabricated in a 0.5-μm digital CMOS technology without resistors. The circuit uses ratioed transistors biased in strong inversion together with the inverse-function technique to produce a temperature-insensitive gain applied to the proportional to absolute temperature (PTAT) term in the reference. After trimming, the peak-to-peak output voltage change is 9.4 mV from 0°C to 70°C. It occupies 0.4 mm² and dissipates 1.4 mW from a 3.7-V supply     

A sub-1-V 15-ppm/°C CMOS bandgap voltage reference withoutrequiring low threshold voltage device

A sub-1-V CMOS bandgap voltage reference requiring no low threshold voltage device is introduced in this paper. In a CMOS technology with V_thn ≈ |V_thp| ≈ 0.9 V at 0°C, the minimum supply voltage of the proposed voltage reference is 0.98 V, and the maximum supply current is 18 μA. A temperature coefficient of 15 ppm/°C from 0°C to 100°C is recorded after trimming. The active area of the circuit is about 0.24 mm²     

A low supply voltage high PSRR voltage reference in CMOS process

This paper describes a bandgap voltage reference circuit that operates with a 3 V power supply and is compatible with a digital CMOS process. The use of a simple circuit topology results in a small silicon area of 0.07 mm², a power consumption of 1 mW and a high power supply rejection over a wide frequency band. The circuit realizes a temperature coefficient of 85 ppm/°C and a standard deviation of 20 mV without trimming     

一种串并结合的多Site熔丝编程算法

随着集成电路产业的迅猛发展,熔丝修调越来越广泛地应用于集成电路测试工序,熔丝段数目随着需要修调参数的增多而逐步增长,传统的串行熔丝编程方案程序存在代码长、可维护性差、执行时间长等缺点,为了改进代码的可读性和可维护性,文章引进了改进型算法,但对测试执行时间没有任何改善。随着测试代工市场竞争日益激烈,多Site测试方案被广泛使用,但是熔丝编程还继续着串行编程的老算法,Site数目越多,熔丝编程时间越长。针对以上,文章提出了一种串并结合的多Site熔丝编程算法,将多Site熔丝编程时间控制在和单Site熔丝串行编程时间几乎一致。