A liquid-triggered liquid microvalve for on-chip flow control

This work introduces a novel surface tension and geometry based liquid-triggered liquid microvalve for on-chip liquid flow control. The simultaneous presence of two liquid plugs at the uncomplicated valve junction triggers the further movement of the liquids and overcomes the stop valve function of the device, thereby providing a precise means of timing liquid movement on-chip. The generic structure was shown to successfully function and forms the basis for several novel and useful functions, including fluidic AND gates, contactless on-chip liquid sample control, timing of independent processes on the same microchip, bubble-free joining of liquids, all of which pose great challenges in the area of microfluidics. The device may be applied to chemical analysis, drug discovery, medical diagnostics and biochemistry.     

REFLICS: Real-time flow imaging and classification system

An accurate analysis of a large dynamic system like our oceans requires spatially fine and temporally matched data collection methods. Current methods to estimate fish stock size from pelagic (marine) fish egg abundance by using ships to take point samples of fish eggs have large margins of error due to spatial and temporal undersampling. The real-time flow imaging and classification system (REFLICS) enhances fish egg sampling by obtaining continuous, accurate information on fish egg abundance as the ship cruises along in the area of interest. REFLICS images the dynamic flow with a progressive-scan area camera (60 frames/s) and a synchronized strobe in backlighting configuration. Digitization and processing occur on a dual-processor Pentium II PC and a pipeline-based image-processing board. REFLICS uses a segmentation algorithm to locate fish-egg-like objects in the image and then a classifier to determine fish egg, species, and development stage (age). We present an integrated system design of REFLICS and performance results. REFLICS can perform in real time (60 Hz), classify fish eggs with low false negative rates on real data collected from a cruise, and work in harsh conditions aboard ships at sea. REFLICS enables cost-effective, real-time assessment of pelagic fish eggs for research and management. Received: 12 April 2000 / Accepted: 6 July 2000     

An energy-efficient design of microkernel-based on-chip OS for NOC-based manycore system

The chip multiprocessor is the most prolific processor design because its many cores enhance system performance. Network on chip (NOC) has been proposed as a promising model to solve the connection problem of the cores. However, a new challenge consists of fully benefiting from the on-chip network and the cores. In this paper, we propose a novel energy-efficient design of a microkernel-based on-chip operating system for an NOC-based manycore system. The operating system (OS) is partitioned into the microkernel and the other OS modules. They are distributed on the network to provide services to the user programs. Our experimental results show that our design can improve system performance with reduced power consumption.     

Fluorescence detection in a micro flow cytometer without on-chip fibers

This paper describes a novel concept of integrated on-chip fiber free laser-induced fluorescence detection system. The poly-dimethylsiloxane (PDMS) chip was fabricated using soft lithography and was bonded with a glass substrate of 150 μm thickness that reduced the distance of channel-to-sidewall to less than 180 μm. The cells and particles detection was conducted by an external single fiber close to the glass substrate that transmitted laser light for simultaneous excitation and receipt of the emission light signals. The performance of the proposed device was demonstrated using fluorescence beads, stained white blood cells, and yeast cells. The experimental results showed the simplicity and flexibility of the proposed device configuration which can provide convenient on-chip integration interface for fast, high throughput, and low-cost laser-induced fluorescence detection micro flow cytometer.     

基于片上系统的EFI安全机制研究

实现了基本的Winnow算法、Balanced Winnow算法和带反馈学习功能的Winnow算法,并将其成功地应用于大规模垃圾邮件过滤,分别在SEWM2007和SEWM2008数据集上对上述三个算法进行了对比实验.实验结果表明,Winnow算法及其变体在分类效果和效率上都优于Logiisfic算法.     

A CMOS image sensor with optical and potential dual imaging function for on-chip bioscientific applications

An optical and potential dual imaging CMOS sensor for bioscientific applications was proposed and fabricated. The CMOS image sensor has the capability to simultaneously capture optical and on-chip potential images. The sensor is designed with target applications of on-chip DNA (or protein) microarray analysis and on-chip neural imaging. A potential imaging function was implemented onto a CMOS image sensor with a simple pixel circuitry that is compatible with optical image sensor pixels. The basic properties of the potential-sensing pixel were characterized. By choosing an appropriate operating sequence and off-chip configuration, the sensor can be operated in either a wide-range potential imaging mode (>5 V) or a high-resolution potential imaging mode (1.6 mV). The sensor is applicable for most of the target applications and is capable of detecting a pH change in the solution placed on the surface. Two-dimensional optical and potential dual imaging was successfully demonstrated, and the profile of a potential spot smaller than 50 μm was clearly observed.     

片上逻辑分析仪的设计

提出了一种用在FPGA上实现的片上逻辑分析仪的设计方案;随着FPGA的规模的增大,在其内部可以实现复杂的SoC设计,但是I/O端口数量有限,采用VHDL设计,可以在源代码级插入到设计中,这也使得它与FPGA的器件类型和开发软件保持独立,它可以对FPGA内部的任何信号和复杂的事件进行追踪,采样的结果保存在通过片上的同步RAM实现的循环跟踪缓存区,通过AMBAAPB总线接口完成对触发引擎控制和缓存区的读写;这种实现方案的逻辑分析仪占用资源小,可以达到的频率高,可广泛应用到基于AMBA总线的SoC设计中;最后,对可改进的方向进行了分析。     

An on-chip cell culturing and combinatorial drug screening system

A low-cost, convenient and precise drug combination screening microfluidic platform is developed, in which cell culture chambers designed with micropillars integrate with three laminar flow diffusion channels. This platform has several distinct features, including minimum shear stress on cells, biocompatibility, optimum concentration distribution and automatic combinatorial gradient generation, which can potentially speed up the discovery of an effective drug combination for cancer ablations. The presented device can generate two-drug combination gradients at the optimum flow rate of 90 μL/h and can be applied to identify the optimal combination of two clinically relevant chemotherapy drugs. For demonstration, paclitaxel at 0.77 × 10^?3 mg/mL and cisplatin at 0.23 × 10^?4 mg/mL were studied against lung cancer cells (A549). This microfluidic device has the potential to provide a precise and robust screening for anticancer combinational drugs practiced in clinics.     

Design and fabrication of an on-chip micro flow cytometer with integrated micro-lens

Microsystem Technologies - In this paper, the design and fabrication of an on-chip micro flow cytometer chip with integrated micro-lens with a size of...     

Optimizing array-intensive applications for on-chip multiprocessors

With energy consumption becoming one of the first-class optimization parameters in computer system design, compilation techniques that consider performance and energy simultaneously are expected to play a central role. In particular, compiling a given application code under performance and energy constraints is becoming an important problem. In this paper, we focus on an on-chip multiprocessor architecture and present a set of code optimization strategies. We first evaluate an adaptive loop parallelization strategy (i.e., a strategy that allows each loop nest to execute using a different number of processors if doing so is beneficial) and measure the potential energy savings when unused processors during execution of a nested loop are shut down (i.e., placed into a power-down or sleep state). Our results show that shutting down unused processors can lead to as much as 67 percent energy savings at the expense of up to 17 percent performance loss in a set of array-intensive applications. To eliminate this performance penalty, we also discuss and evaluate a processor preactivation strategy based on compile-time analysis of nested loops. Based on our experiments, we conclude that an adaptive loop parallelization strategy combined with idle processor shut down and preactivation can be very effective in reducing energy consumption without increasing execution time. We then generalize our strategy and present an application parallelization strategy based on integer linear programming (ILP). Given an array-intensive application, our optimization strategy determines the number of processors to be used in executing each loop nest based on the objective function and additional compilation constraints provided by the user/programmer. Our initial experience with this constraint-based optimization strategy shows that it is very successful in optimizing array-intensive applications on on-chip multiprocessors under multiple energy and performance constraints.     

基于Fution模数混合FPGA芯片的心电仪片上系统开发

利用Actel公司的基于Flash构架的模数混合型Fusion系列FPGA芯片,设计了一款低功耗片上的心电监护仪采集显示系统.结合Fusion系列的FPGA芯片的各种资源,实现了心电采集预处理模块、数据的处理和显示模块的系统集成,完整地形成了片上系统.     

Dual partitioning multicasting for high-performance on-chip networks

As the number of cores integrated onto a single chip increases, power dissipation and network latency become ever-increasingly stringent. On-chip network provides an efficient and scalable interconnection paradigm for chip multiprocessors (CMPs), wherein one-to-many (multicast) communication is universal for such platforms. Without efficient multicasting support, traditional unicasting on-chip networks will be low efficiency in tackling such multicast communication. In this paper, we propose Dual Partitioning Multicasting (DPM) to reduce packet latency and balance network resource utilization. Specifically, DPM scheme adaptively makes routing decisions based on the network load-balance level as well as the link sharing patterns characterized by the distribution of the multicasting destinations. Extensive experimental results for synthetic traffic as well as real applications show that compared with the recently proposed RPM scheme, DPM significantly reduces the average packet latency and mitigates the network power consumption. More importantly, DPM is highly scalable for future on-chip networks with heavy traffic load and varieties of traffic patterns.     

Silicon-aware distributed switch architecture for on-chip networks

It is well-known that current Chip MultiProcessor (CMP) and high-end MultiProcessor System-on-Chip (MPSoC) designs are growing in their number of components. Networks-on-Chip (NoC) provide the required connectivity for such CMP and MPSoC designs at reasonable costs. As technology advances, links become the critical component in the NoC due to their long delay and power consumption, becoming unacceptable for long global interconnects.In this paper we present a new switch architecture that reduces the negative impact of links on the NoC. We call our proposal distributed switch. The distributed switch spreads the circuitry of the switch onto the links. Thus, packets are buffered, routed, and forwarded at the same time they are crossing the link.Distributing a modular switch onto the link improves the trade off between the power consumption and the operating frequency of the entire network. On the contrary, area resources are increased. Additionally, the distributed switch presents better fault tolerance and process variation behavior with respect to a non-distributed switch.     

Lightweight authenticated encryption for embedded on-chip systems

ABSTRACT

Embedded systems are routinely deployed in critical infrastructures nowadays, therefore their security is increasingly important. This, combined with the pressing requirement of deploying massive numbers of low-cost and low-energy embedded devices, stimulates the evolution of lightweight cryptography and other green-computing security mechanisms. New crypto-primitives are being proposed that offer moderate security and produce compact implementations. In this article, we present a lightweight authenticated encryption scheme based on the integrated hardware implementation of the lightweight block cipher PRESENT and the lightweight hash function SPONGENT. The presented combination of a cipher and a hash function is appropriate for implementing authenticated encryption schemes that are commonly utilized in one-way and mutual authentication protocols. We exploit their inner structure to discover hardware elements usable by both primitives, thus reducing the circuit’s size. The integrated versions demonstrate a 27% reduction in hardware area compared to the simple combination of the two primitives. The resulting solution is ported on a field-programmable gate array (FPGA) and a complete security application with input/output from a universal asynchronous receiver/transmitter (UART) gate is created. In comparison with similar implementations in hardware and software, the proposed scheme represents a better overall status.     

再入系统的热流分析

针对再入过程中返回舱体存在严重的气动热问题,提出一种新型再入系统.通过建立减速系统的阻力估算模型和求解动力学方程,分析再入过程的速度特性和驻点热流密度,计算结果与文献算例数据吻合,验证飞行器再入过程的热流特性.采用Euler数值计算与边界层内工程算法相结合的方法计算充气阻力罩表面热流密度,结果表明热流密度在驻点附近较大,远离驻点后迅速减小.     

基于最小空闲时间优先的片上总线仲裁算法

提出一种基于抢占阈值的最小空闲时间优先服务的总线仲裁算法。主设备总线服务请求的空闲时间越短,获得总线服务就越快,引入抢占阈值降低了总线服务频繁切换造成的颠簸现象。实验结果表明,该算法的MDP比常见的算法平均减少了43.8%,满足了各主设备总线服务请求的强实时要求。     

A complete strategy for testing an on-chip multiprocessorarchitecture

The article proposes an approach that divides testing into three phases: router testing, RAM block testing, and distributed processor testing. This test strategy was implemented for the on-chip multiprocessor architecture of a fine-grain, massively parallel machine developed in 1995 at the National Polytechnic Institute of Grenoble. The hierarchical strategy minimizes the entire architecture's test cost by avoiding unnecessary testing. For example, testing a processor that is inaccessible because its router is faulty or that has a faulty local RAM is useless. Furthermore, a fault-free RAM cannot be used if the corresponding node router is faulty     

Miniature on-chip band pass filter for RF applications

Multilayer on-chip inductor and capacitor are proposed in this paper. These passive on-chip components are combined to form series LC on-chip band pass filter and are designed based on VLSI multilayer design concepts to operate at high frequency range applications. Development in RF-VLSI circuits demanded low size on-chip filters to operate at higher order frequency range with better tuning response. Design and simulation of on-chip passive components is carried out in high frequency structural simulator to obtain scattering parameters required for analysis. The designed filter model has good compromise between S ₁₁ and S ₂₁ parameters against frequency satisfying basic conditions of on-chip band pass filter. Proposed filter circuit has centre frequency at 39.5 GHz, bandwidth of 3.17 GHz, loaded Q value of 12.5, fractional bandwidth of 8 % which is suitable for narrow band operations and occupies an on-chip area of 0.0256 mm². This miniature on-chip band pass filter reduces the size and cost of the chip significantly at radio frequencies when compared with existing models.

     

Non-destructive in situ test for anodic bonding

New test structures have been designed, fabricated and tested to monitor the quality of the anodic bonding between silicon and glass. The main advantage of the described test is that it is not destructive and allows the bond quality to be monitored in processed wafers. This test is very easy to implement in a chip or in a wafer because of its simplicity. Test structures consist of a matrix of circular and rectangular cavities defined by reactive ion etching (RIE) on the silicon wafer, with different sizes and depths. The bonding process and quality can be monitorized by the measurement of the size of the smallest bonded cavity and the distance between the bonded area and the cavity border. These structures give information about the level of electrostatic pressure that has been applied to pull together into intimate contact the surfaces of the two wafers. The higher the electrostatic pressure, the better the bond. We have applied these test structures to study the influence of the voltage and the temperature on the anodic bonding process. Results are in good agreement with finite-element method (FEM) simulations.     

Nonuniform cache architectures for wire-delay dominated on-chip caches

Nonuniform cache access designs solve the on-chip wire delay problem for future large integrated caches. By embedding a network in the cache, NUCA designs let data migrate within the cache, clustering the working set nearest the processor. The authors propose several designs that treat the cache as a network of banks and facilitate nonuniform accesses to different physical regions. NUCA architectures offer low-latency access, increased scalability, and greater performance stability than conventional uniform access cache architectures.