槽栅MOS控制的晶闸管

报道了一种新结构的功率栅控晶闸管,称其为槽栅MOS控制的晶闸管（TMCT）.在该器件结构中,采用UMOS控制晶闸管的开启和关闭.结构中不存在任何的寄生器件,因此,消除了在其它结构的栅控晶闸管中由寄生晶体管引起的各种问题,所以TMCT会有优良的电特性.实验结果表明,多元胞TMCT（600V,有源区面积0.2mm2）的开态压降在300A/cm2时为1.25V,最大可控电流在栅压为-20V和电感负载下达到了296A/cm2.     

新型双异质结双平面掺杂功率PHEMT

设计并制作了双异质结双平面掺杂的Al0 .2 4 Ga0 .76 As/ In0 .2 2 Ga0 .78As/ Al0 .2 4 Ga0 .76 As功率PHEMT器件,采用双选择腐蚀栅槽结构,有效提高了PHEMT器件的输出电流和击穿电压.对于1μm栅长的器件,最大输出电流为5 0 0 m A/ mm ,跨导为2 75 m S/ m m,阈值电压为- 1 .4 V,最大栅漏反向击穿电压达到了33V .研究结果表明,在栅源间距一定时,栅漏间距对于器件的输出电流、跨导和击穿电压有很大关系,是设计功率PHEMT的关键之一.     

100V高压pMOS器件研制

研制出适用于100V高压集成电路的厚栅氧高压pMOS器件. 在器件设计过程中利用TCAD软件对器件结构及性能进行了模拟和优化，开发出与0.8μm n阱标准CMOS工艺兼容的高压工艺流程，并试制成功. 实验结果表明，该器件关态击穿电压为-158V，栅压-100V时饱和驱动电流达17mA (W/L=100μm/2μm) ，可以在100V高压下安全工作.     

一种新型高速嵌入式动态随机存储器

基于二维器件模拟工具,研究了一种采用栅控二极管作为写操作单元的新型平面无电容动态随机存储器.该器件由一个n型浮栅MOSFET和一个栅控二极管组成.MOSFET的p型掺杂多晶硅浮栅作为栅控二极管的p型掺杂区,同时也是电荷存储单元.写“0”操作通过正向偏置二极管实现,而写“1”操作通过反向偏置二极管,同时在控制栅上加负电压使栅控二极管工作为隧穿场效应晶体管(Tunneling FET)来实现.由于正向偏置二极管和隧穿晶体管开启时接近1μA/μm的电流密度,实现了高速写操作过程,而且该器件的制造工艺与闪烁存储器和逻辑器件的制造兼容,因此适合在片上系统(SOC)中作为嵌入式动态随机存储器使用.     

全耗尽CMOS/SOI工艺

对全耗尽 CMOS/ SOI工艺进行了研究 ,成功地开发出成套全耗尽 CMOS/ SOI抗辐照工艺 .其关键工艺技术包括 :氮化 H2 - O2 合成薄栅氧、双栅和注 Ge硅化物等技术 .经过工艺投片 ,获得性能良好的抗辐照 CMOS/ SOI器件和电路 (包括 10 1级环振、2 0 0 0门门海阵列等 ) ,其中 ,n MOS:Vt=0 .7V,Vds=4 .5～ 5 .2 V,μeff=4 6 5 cm2 / (V· s) ,p MOS:Vt=- 0 .8V ,Vds=- 5～ - 6 .3V,μeff=2 6 4 cm2 / (V· s) .当工作电压为 5 V时 ,0 .8μm环振单级延迟为 4 5 ps     

1OOV高压pMOS器件研制

研制出适用于100V高压集成电路的厚栅氧高压pMOS器件.在器件设计过程中利用TCAD软件对器件结构及性能进行了模拟和优化,开发出与0.8μm n阱标准CMOS工艺兼容的高压工艺流程,并试制成功.实验结果表明,该器件关态击穿电压为-158V,栅压-100V时饱和驱动电流达17mA(W/L=100μm/2μm),可以在100V高压下安全工作.     

超薄Si3N4/SiO2(N/O) stack栅介质及器件

成功制备了EOT(equivalent oxide thickness)为2.1nm的Si3N4/SiO2(N/O) stack栅介质,并对其性质进行了研究.结果表明,同样EOT的Si3N4/SiO2 stack栅介质和纯SiO2栅介质比较,前者在栅隧穿漏电流、抗SILC性能、栅介质寿命等方面都远优于后者.在此基础上,采用Si3N4/SiO2 stack栅介质制备出性能优良的栅长为0.12μm的CMOS器件,器件很好地抑制了短沟道效应.在Vds=Vgs=±1.5V下,nMOSFET和pMOSFET对应的饱和电流Ion分别为584.3μA/μm和-281.3μA/μm,对应Ioff分别是8.3nA/μm和-1.3nA/μm.     

MBE生长的高质量AlGaAs/InGaAs双δ掺杂PHEMT结构的材料

用 MBE方法制备的 PHEMT微结构材料 ,其 2 DEG浓度随材料结构的不同在 2 .0— 4.0× 1 0 12 cm- 2 之间 ,室温霍耳迁移率在 50 0 0— 650 0 cm2 · V- 1· s- 1之间 .制备的 PHEMT器件 ,栅长为 0 .7μm的器件的直流特性 :Idss～ 2 80 m A/mm,Imax～ 52 0— 580 m A/mm,gm～ 32 0— 40 0 m S/mm,BVDS>1 5V( IDS=1 m A/mm) ,BVGS>1 0 V,微波特性 :P0 ～ 60 0— 90 0 m W/mm,G～ 6— 1 0 d B,ηadd～ 40— 60 % ;栅长为 0 .4μm的器件的直流特性 :Imax～ 80 0 m A/mm,gm>40 0 m S/mm.     

Ka波段GaN HEMT功率器件

设计了Ka波段GaN功率高电子迁移率晶体管(HEMT)外延材料及器件结构,采用AlN插入层提高了二维电子气(2DEG)浓度.采用场板结构提高了器件击穿电压.采用T型栅工艺实现了细栅制作,提高了器件高频输出功率增益.采用钝化工艺抑制了电流崩塌,提高了输出功率.采用通孔工艺减小源极寄生电阻,通过优化钝化层厚度减小了寄生电容,提高了器件增益.基于国产SiC外延材料及0.15 μm GaN HEMT工艺进行了器件流片,最终研制成功Ka波段GaN HEMT功率器件.对栅宽300 μm器件在29 GHz下进行了微波测试,工作栅源电压为-2.2V,源漏电压为20 V,输入功率为21 dBm时,器件输出功率为30 dBm,功率增益为9 dB,功率附加效率约为43％,功率密度达到3.3 W/mm.     

薄膜全耗尽SOICMOS器件和电路

对全耗尽 SOI(FD SOI) CMOS器件和电路进行了研究 ,硅膜厚度为 70 nm.器件采用双多晶硅栅结构 ,即NMOS器件采用 P+多晶硅栅 ,PMOS器件采用 N+多晶硅栅 ,在轻沟道掺杂条件下 ,得到器件的阈值电压接近0 .7V.为了减小源漏电阻以及防止在沟道边缘出现空洞 (V oids) ,采用了注 Ge硅化物工艺 ,源漏方块电阻约为5 .2Ω /□ .经过工艺流片 ,获得了性能良好的器件和电路 .其中当工作电压为 5 V时 ,0 .8μm 10 1级环振单级延迟为 45 ps     

Zero-voltage-zero-current switching in high-output-voltagefull-bridge PWM converters using the interwinding capacitance

A novel zero-voltage and zero-current-switching (ZVZCS) full-bridge (FB) pulsewidth-modulated (PWM) power converter is proposed. The new converter uses the interwinding capacitance and a small primary-side inductor to achieve a zero-current-zero-voltage turn off and a zero-current turn on of the passive-to-active leg transistors. The turn off of the active-to-passive leg transistors is with zero voltage, and the turn on is with zero voltage and zero current across them. The ringing caused by the parasitic interwinding capacitance and by the reverse recovery of the rectifiers is reduced. The new converter is attractive for high-output-voltage applications (600-1000 V), where the interwinding capacitance is sufficiently dominant. In addition, switches such as insulated gate bipolar transistors (IGBTs) and MCTs can be used at higher frequencies which is particularly desirable for high-power application (above 2 kW). The experimental results obtained from an IGBT-based 62.5-kHz DC/DC power converter with a rated output voltage of 600 V and a nominal power of 1.2 kW are presented     

Analysis of transit times and minority carrier mobility in n-p-n 4H-SiC bipolar junction transistors

An analysis of the transit times and minority carrier mobility in n-p-n 4H-SiC RF bipolar junction transistors is presented. These parameters were extracted from small signal RF measurements on 4H-SiC RF transistors with three different base thicknesses: 100, 140, and 200 nm. The study shows that the room temperature minority carrier electron mobility is 215 cm/sup 2//V/spl middot/s for a base Al doping of N/sub B/=4/spl times/10/sup 18/ cm/sup -3/. The analysis reveals that the collector charging time /spl tau//sub C/ and the parasitic charging time /spl tau//sub P/ from the capacitance between metal pads and the underlying collector region have a significant effect on the transistors RF performance. The calculated RF gain is in good agreement with the measured results.     

Engineering density of semiconductor-dielectric interface states to modulate threshold voltage in OFETs

Threshold-voltage control is critical to the further development of pentacene organic field-effect transistors (OFETs). In this paper, we demonstrate that the threshold voltage can be tuned through chemical treatment of the gate dielectric layer. We show that oxygen plasma treatment of an organic polymer gate dielectric, parylene, introduces traps at the semiconductor-dielectric interface that strongly affect the OFET performance. Atomic force microscopy, optical microscopy using crossed-polarizers, and current-voltage and capacitance-voltage characterization were performed on treated and untreated devices. A model is presented to account for the effects of trap-introduced charges, both 1) fixed charges (2.0/spl times/10/sup -6/ C/cm/sup 2/) that shift the threshold voltage from -17 to +116 V and 2) mobile charges (1.1/spl times/10/sup -6/ C/cm/sup 2/) that increase the parasitic bulk conductivity. This technique offers a potential method of tuning threshold voltage at the process level.     

A Monolithically Integrated 12V/5V Switch-Capacitor DC-DC Converter

Motivated by the battery-operated applications that demand compact,lightweight andefficient DC-DC converters,many kinds of converter circuits have been published.Amongthem,resonantconverters and the soft-switching convertershave greatl...     

Vertical scaling of 0.25-/spl mu/m emitter InP/InGaAs single heterojunction bipolar transistors with f/sub T/ of 452 GHz

Vertical scaling of the epitaxial structure has allowed submicron InP/InGaAs-based single heterojunction bipolar transistors (SHBTs) to achieve record high-frequency performance. The 0.25/spl times/16 /spl mu/m/sup 2/ transistors, featuring a 25-nm base and a 100-nm collector, display current gain cut-off frequencies f/sub T/ of 452 GHz. The devices operate at current densities above 1000 kA/cm/sup 2/ and have BV/sub CEO/ breakdowns of 2.1 V. A detailed analysis of device radio frequency (RF) parameters, and delay components with respect to scaling of the collector thickness is presented.     

A 50 dB variable gain amplifier using parasitic bipolar transistorsin CMOS

A variable-gain amplifier (VGA) with a gain range of 50 dB has been implemented in a standard 3 μm CMOS process using parasitic lateral and vertical bipolar transistors to form the core of the circuit. The bipolar transistors had been characterized extensively. The VGA has a bandwidth larger than 3 MHz over the whole gain range and operates on a single 5 V power supply. The active area is about 0.8×0.9 mm²     

Electrical characteristics of 8-/spl Aring/ EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown junctions

The authors demonstrate high-performing n-channel transistors with a HfO/sub 2//TaN gate stack and a low thermal-budget process using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an equivalent oxide thickness (EOT) of 8 /spl Aring/, a leakage current of 1.5 A/cm/sup 2/ at V/sub G/=1 V, a peak mobility of 190 cm/sup 2//V/spl middot/s, and a drive-current of 815 /spl mu/A//spl mu/m at an off-state current of 0.1 /spl mu/A//spl mu/m for V/sub DD/=1.2 V. Identical gate stacks processed with a 1000-/spl deg/C spike anneal have a higher peak mobility at 275 cm/sup 2//V/spl middot/s, but a 5-/spl Aring/ higher EOT and a reduced drive current at 610 /spl mu/A//spl mu/m. The observed performance improvement for the low thermal-budget devices is shown to be mostly related to the lower EOT. The time-to-breakdown measurements indicate a maximum operating voltage of 1.6 V (1.2 V at 125 /spl deg/C) for a ten-year lifetime, whereas positive-bias temperature-instability measurements indicate a sufficient lifetime for operating voltages below 0.75 V.     

Study of trapping phenomenon in 4H-SiC MESFETs: dependence on substrate purity

This work demonstrates that the "purity", meaning the low density of electron traps in a semi-insulating (SI) SiC substrate, can be crucial for the electrical characteristics of 4H-SiC MESFETs. Structures realized on two types of SI substrates have been investigated. The first kind is vanadium doped substrates grown by the classical Physical Vapor Transport (PVT) sublimation technique. The second kind are extremely low vanadium content SI substrates grown by the high temperature CVD (HTCVD) technique. For all the transistors, I/sub d/-V/sub ds/ measurements have been performed as a function of temperature. Different parasitic effects have been observed on the static output characteristics in the case of PVT substrates. Frequency dispersion measurements of the transconductance and drain-source output conductance, have next been realized. The results give clear evidence of the presence of deep traps in the transistors realized on PVT substrates. Those traps have an activation energy of 1.05 eV and a capture cross section between 10/sup -18/ cm/sup -2/ and 10/sup -19/ cm/sup -2/. They are most probably related to vanadium. The correlation between the presence of these traps and the parasitic effects on the output characteristics is discussed and the trap localization in the structure is established. In the case of HTCVD very low vanadium substrates, no parasitic effect have been observed and the presence of traps was not detected by the different characterization techniques.     

A novel high-performance asymmetric hetero-doped S/D high-voltage MOSFET

A novel high-voltage MOSFET structure, using a simple yet effective concept of an asymmetric hetero-doped source/drain (S/D) is proposed. The asymmetric hetero-doped S/D reduces the on-state resistance of the transistor due to the high doping used for device drain drift, provides excellent ruggedness for parasitic NPN turned-on due to a minimized n/sup +/ source spacer, and also raises the device breakdown voltage due to charge compensation in the composite drain drift region. Therefore, the asymmetric hetero-doped S/D structure allows the high voltage MOSFET to have a high current handling capability with a small device size. This in turn causes the R (sp, on) to be low, leading to high performance for the power device when used in a power integrated circuit. Measured results show that a 24-V breakdown voltage new device with a low-cost two-layer metal (Al) back-end achieves very low R (sp, on) of 0.166 m/spl Omega//spl middot/cm/sup 2/. Furthermore, the new device with a 65-V high-side capability achieves good isolation performance even when switching S/D to -20 V and also gets a cutoff frequency of 13 GHz at a gate voltage of 5.5 V.