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高速高性能数据采集系统的实现方法 总被引:3,自引:0,他引:3
介绍了AD9240和FPGA在高速、高性能数据采集系统中的应用方法,讨论了如何运用多片高速A/D变换器AD9240同时对多路模拟信号进行数据采集,以及使用现场可编程逻辑器件FPGA实现时序控制和实时数据存储的方法,给出了构成数据采集系统的基本原理框图和测试结果。介绍的数据采集系统具有极佳的性能和广泛的适用性。 相似文献
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基于DSP和CPLD的光纤陀螺信号采集系统设计 总被引:2,自引:1,他引:1
随着光纤陀螺在空空导弹中的广泛应用,为了对其特性进行深入研究,设计了一种光纤陀螺信号采集系统,硬件结构采用了DSP+CPLD的方式,控制AD芯片完成多路光纤陀螺数据的采集。为了降低干扰对采集精度的影响,在硬件以及软件方面进行了抗干扰设计。通过对该系统的测试验证,性能指标满足使用要求。本系统设计新颖、实用,操作简单快捷。 相似文献
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基于FPGA和AD1836的I2S接口设计 总被引:1,自引:0,他引:1
引言
AD1836是ADI公司新推出的一款高性能的单片声码器,适用于数字音频系统。它采用5V供电,数字接口输入输出电平为LVTTL电平,可以直接和一般的FPGA连接。AD1836集成了3路立体的D/A和两路立体的A/D,参考电压为2.25V,为了降低信号的干扰,模拟信号的输入输出均采用差分的形式,输入输出模拟信号的最大峰峰值为5.6V。系统时钟为12.288MHz,数据采样率最高为96kHz, 相似文献
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《Circuits and Systems II: Express Briefs, IEEE Transactions on》2009,56(5):344-348
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The histogram method is a very classical test technique for Analog to Digital Converters (ADCs), but only used for external testing because of the large amount of required hardware resources. This paper discusses the viability of a BIST implementation for this technique. An original approach is developed that permits to extract the ADC parameters with a reduced area overhead. This approach involves (i) the calculation of the parameters using approximations and (ii) the decomposition of the global test in a code-after-code test procedure. These two features allow a significant reduction of the required operative resources and memory dedicated to the storage of experimental data. In addition, the use of a piece-wise approximation for computing the ideal histogram also permits to minimize the memory dedicated to the storage of reference data. 相似文献
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为了实时采集各种电器设备的对地电阻数据,保证各设备良好的接地性,设计了一种很实用的基于FPGA和MCU的多路同步数据采集的方案,通过对多片ADC进行同步处理,有效地提高了系统运行速度。该方案的A/D转换芯片使用TI的TLV2543,FPGA使用Altera的EP1C6Q240C8。通过利用EDA工具和VHDL语言,在FPGA中设计和实现了ADC接口、数据存储模块以及MCU接口等,给出了系统设计框图,并说明了控制逻辑。 相似文献
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Dubois J. Ginhac D. Paindavoine M. Heyrman B. 《Solid-State Circuits, IEEE Journal of》2008,43(3):706-717
A high-speed analog VLSI image acquisition and pre-processing system has been designed and fabricated in a 0.35 mum standard CMOS process. The chip features a massively parallel architecture enabling the computation of programmable low-level image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel or Laplacian filters are implemented on the circuit. For this purpose, each 35 mum times 35 mum pixel includes a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. The retina provides address-event coded output on three asynchronous buses: one output dedicated to the gradient and the other two to the pixel values. A 64 times 64 pixel proof-of-concept chip was fabricated. A dedicated embedded platform including FPGA and ADCs has also been designed to evaluate the vision chip. Measured results show that the proposed sensor successfully captures raw images up to 10 000 frames per second and runs low-level image processing at a frame rate of 2000 to 5000 frames per second. 相似文献
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A family of 8- and 10-b analog/digital converters (ADCs) has been designed using a more efficient architecture. The 10-b ADC requires two 4-b (two 3-b for the 8-b converter) half-flash cycles and a self-corrected voltage estimator. While the speed is similar to that of conventional half-flash ADCs, power consumption and die size are lower due to reduced numbers of comparators and resistors. The flash steps can be reduced by 1 b each, for an overall reduction in comparator count by a factor of 2. This architecture can be used to reduce the comparator and resistor count of any existing half-flash ADCs, ultimately decreasing die area and power consumption. For the same process and resolution, this architecture reduces die size and power consumption by 50% 相似文献
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A theoretical analysis of the statistics of the quantization noise in split delta-sigma (DeltaSigma) analog-to-digital converters (ADCs) is presented. Sufficient conditions are derived that ensure that the quantization noise components of the constituent DeltaSigma modulators are asymptotically independent of each other, the input, delayed versions of themselves, and uniformly distributed. The application of the conditions is illustrated for two useful classes of split DeltaSigma ADCs. 相似文献
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本文研究了高速ADC及由其构成的并行/交替式数据采集系统的DNL(微分非线性)与INL(积分非线性)及有关测试理论与方法.根据统计学方法由单片ADC的DNL和INL导出了并行/交替式数据采集系统的DNL和INL的数学表达式;并且采用统计直方图方法分别对单片ADC和由双片ADC组成的并行/交替式数据采集系统进行了计算机仿真.结果表明,并行/交替式数据采集系统的DNL与INL小于每一通道单片ADC的DNL和INL. 相似文献
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《IEEE transactions on circuits and systems. I, Regular papers》2009,56(3):509-518
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