AD73360在多路通用数据采集卡中的应用

AD73360是AnalogDevice公司推出的 6路独立通道带有模拟前端的 16位 Δ型ADC ,在多通道同步测试系统中具有比较大的优势。特别在多数据融合技术中 ,数据的获取需要严格的同步性 ,利用AD73360各独立通道群延时小的特性可以很好的满足这一要求。在作者研制的MCC I型多功能测试系统中 ,利用ADSP2 181和三片级联的AD73360可以构成群延时很小的 18路通用数据采集模块     

两线串口(I~2C兼容)10位ADC的特点是带片上温度传感器

AD7417和AD7418分别为4通道和单通道10位逐次逼近式ADC。这两种ADC的每通道转换时间均为15μs,内部带有时钟振荡器、跟踪／保持器、基准电压源和5通道（AD7417）或2通道（AD7418）多路转换器。片上温度传感器在－55～＋125℃温度范围内,工作电压为2．7－5．5V,并区采用16脚TSSOP和8脚μSOIC封装。·四通道和单通道IZC串口ADC·片上温度传感器惜机方式应用·数据采集,电池供电仪器,测试仪器两线串口(I~2C兼容)10位ADC的特点是带片上温度传感器     

高速高性能数据采集系统的实现方法

介绍了AD9240和FPGA在高速、高性能数据采集系统中的应用方法,讨论了如何运用多片高速A/D变换器AD9240同时对多路模拟信号进行数据采集,以及使用现场可编程逻辑器件FPGA实现时序控制和实时数据存储的方法,给出了构成数据采集系统的基本原理框图和测试结果。介绍的数据采集系统具有极佳的性能和广泛的适用性。     

基于DSP和CPLD的光纤陀螺信号采集系统设计

随着光纤陀螺在空空导弹中的广泛应用,为了对其特性进行深入研究,设计了一种光纤陀螺信号采集系统,硬件结构采用了DSP＋CPLD的方式,控制AD芯片完成多路光纤陀螺数据的采集。为了降低干扰对采集精度的影响,在硬件以及软件方面进行了抗干扰设计。通过对该系统的测试验证,性能指标满足使用要求。本系统设计新颖、实用,操作简单快捷。     

基于AD9244和PCI总线的数据采集方案

介绍在虚拟接收机的研究背景下，基于AD9244和PCI总线实现的数据采集系统。AD9244．是黄国ADI公司推出的一种14住、低功耗A／D转换芯片。整个系统采用CPLD作为逻辑控制，两片IDT7204芯片构成14位4kbit容量的缓存器。     

基于FPGA和AD1836的I2S接口设计

引言 AD1836是ADI公司新推出的一款高性能的单片声码器,适用于数字音频系统。它采用5V供电,数字接口输入输出电平为LVTTL电平,可以直接和一般的FPGA连接。AD1836集成了3路立体的D／A和两路立体的A／D,参考电压为2．25V,为了降低信号的干扰,模拟信号的输入输出均采用差分的形式,输入输出模拟信号的最大峰峰值为5．6V。系统时钟为12．288MHz,数据采样率最高为96kHz,     

宽频带幅度比和相位差测量系统的设计

AD8302是一款集测量幅度和相位于一体的单款集成电路,且测量精度高,测量频带范围宽。适用于移动通信及接收系统。介绍AD8302结构原理及工作模式,并结合C8051F单片机对AD8302测得的2路信号的幅度比和相位差值进行模数转换,构建一个基于C8051F单片机的片上数据采集系统,并利用VB语言编写单片机与PC机的串口通信,可将实时采集到的数据送到PC机中。     

基于AD7891的车辆称重采集系统设计

介绍AD7891和DSP结合的车辆称重采集系统的设计方案,选用AD7891实现多路数据的高速采集．根据AD7891的工作时序图,采用TMS320LF2407实现时序控制,介绍系统软件和硬件设计。结果表明该系统设计满足要求,且硬件电路易于实现。     

多路射频信号相位差现场测量系统设计与实现

设计并实现了四路射频信号相位差测量系统,采用模拟乘法器芯片AD8302测量二路射频信号的相位差。设计了特殊的电路,将基于AD8302的相位差测量系统的测量范围从180°扩展到360°。采用基于CAN总线的数据采集系统实现相位差的现场测量。该系统的相位差测量范围为0°～360°,相位差测量精度为0．1°,误差约为±1°。该系统工作频带宽、电路简单、易于实现,可用于需要实现远距离测量多路射频信号间的相位差的场合。     

宽频带幅度比和相位差测量系统的设计

AD8302是一款集测量幅度和相位于一体的单款集成电路,且测量精度高,测量频带范围宽.适用于移动通信及接收系统.介绍AD8302结构原理及工作模式,并结合C8051F单片机对AD8302测得的2路信号的幅度比和相位差值进行模数转换,构建一个基于C8051F单片机的片上数据采集系统,并利用VB语言编写单片机与PC机的串口通信,可将实时采集到的数据送到PC机中.     

“Split ADC” Calibration for All-Digital Correction of Time-Interleaved ADC Errors

The “split analog-to-digital converter (ADC)” architecture enables fully digital calibration and correction of offset, gain, and aperture-delay mismatch errors in time-interleaved ADCs. The calibration of $M$ interleaved ADCs requires $2M + 1$ half-sized ADCs, a minimal increase in analog complexity. Each conversion is performed by a pair of half-sized ADCs, generating two independent outputs that are digitally corrected using estimates of offset, gain, and aperture-delay errors. The ADC outputs are averaged to produce the ADC output code. The difference of the outputs is used in a calibration algorithm that estimates the error in the correction parameters. Any nonzero difference drives a least-mean-square feedback loop toward zero difference, which can only occur when the average error in each correction parameter is zero. A simulation of a 4 : 1-time-interleaved 16-bit 12-MSps successive-approximation-register ADC shows calibration convergence within 400 000 samples.      

Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST

The histogram method is a very classical test technique for Analog to Digital Converters (ADCs), but only used for external testing because of the large amount of required hardware resources. This paper discusses the viability of a BIST implementation for this technique. An original approach is developed that permits to extract the ADC parameters with a reduced area overhead. This approach involves (i) the calculation of the parameters using approximations and (ii) the decomposition of the global test in a code-after-code test procedure. These two features allow a significant reduction of the required operative resources and memory dedicated to the storage of experimental data. In addition, the use of a piece-wise approximation for computing the ideal histogram also permits to minimize the memory dedicated to the storage of reference data.     

基于FPGA和MCU的多路对地电阻数据采集系统的设计

为了实时采集各种电器设备的对地电阻数据,保证各设备良好的接地性,设计了一种很实用的基于FPGA和MCU的多路同步数据采集的方案,通过对多片ADC进行同步处理,有效地提高了系统运行速度。该方案的A/D转换芯片使用TI的TLV2543,FPGA使用Altera的EP1C6Q240C8。通过利用EDA工具和VHDL语言,在FPGA中设计和实现了ADC接口、数据存储模块以及MCU接口等,给出了系统设计框图,并说明了控制逻辑。     

A 10 000 fps CMOS Sensor With Massively Parallel Image Processing

A high-speed analog VLSI image acquisition and pre-processing system has been designed and fabricated in a 0.35 mum standard CMOS process. The chip features a massively parallel architecture enabling the computation of programmable low-level image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel or Laplacian filters are implemented on the circuit. For this purpose, each 35 mum times 35 mum pixel includes a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. The retina provides address-event coded output on three asynchronous buses: one output dedicated to the gradient and the other two to the pixel values. A 64 times 64 pixel proof-of-concept chip was fabricated. A dedicated embedded platform including FPGA and ADCs has also been designed to evaluate the vision chip. Measured results show that the proposed sensor successfully captures raw images up to 10 000 frames per second and runs low-level image processing at a frame rate of 2000 to 5000 frames per second.     

A multistep A/D converter family with efficient architecture

A family of 8- and 10-b analog/digital converters (ADCs) has been designed using a more efficient architecture. The 10-b ADC requires two 4-b (two 3-b for the 8-b converter) half-flash cycles and a self-corrected voltage estimator. While the speed is similar to that of conventional half-flash ADCs, power consumption and die size are lower due to reduced numbers of comparators and resistors. The flash steps can be reduced by 1 b each, for an overall reduction in comparator count by a factor of 2. This architecture can be used to reduce the comparator and resistor count of any existing half-flash ADCs, ultimately decreasing die area and power consumption. For the same process and resolution, this architecture reduces die size and power consumption by 50%     

A Theoretical Study of the Quantization Noise in Split Delta–Sigma ADCs

A theoretical analysis of the statistics of the quantization noise in split delta-sigma (DeltaSigma) analog-to-digital converters (ADCs) is presented. Sufficient conditions are derived that ensure that the quantization noise components of the constituent DeltaSigma modulators are asymptotically independent of each other, the input, delayed versions of themselves, and uniformly distributed. The application of the conditions is illustrated for two useful classes of split DeltaSigma ADCs.     

高速ADC及由其构成的并行/交替式数据采集系统的非线性研究

本文研究了高速ADC及由其构成的并行/交替式数据采集系统的DNL(微分非线性)与INL(积分非线性)及有关测试理论与方法.根据统计学方法由单片ADC的DNL和INL导出了并行/交替式数据采集系统的DNL和INL的数学表达式;并且采用统计直方图方法分别对单片ADC和由双片ADC组成的并行/交替式数据采集系统进行了计算机仿真.结果表明,并行/交替式数据采集系统的DNL与INL小于每一通道单片ADC的DNL和INL.     

Power Dissipation Bounds for High-Speed Nyquist Analog-to-Digital Converters

A very important limitation of high-speed analog-to-digital converters (ADCs) is their power dissipation. ADC power dissipation has been examined several times, mostly empirically. In this paper, we present an attempt to estimate a lower bound for the power of ADCs, based on first principles and using pipeline and flash architectures as examples. We find that power dissipation of high-resolution ADCs is bound by noise, whereas technology is the limiting factor for low-resolution devices. Our model assumes the use of digital error correction, but we also study an example on the power penalty due to matching requirements. A comparison with published experimental data indicates that the best ADCs use about 50 times the estimated minimum power. Two published ADCs are used for a more detailed comparison between the minimum bound and today's designs.      

两种流水折叠分级式ADC及其结构比较

 本文利用模拟余量和模拟余差研制出两种流水折叠分级式ADC,提出了两种电路改进结构——有余差转换和无余差转换,并通过动态性能的测试来对比分析两结构的优缺点.无余差转换的ADC+和由其复合构成的ADC的测试表明,性能分别达到2bits@40MSPS ADC+和2+8bits@40MSPS ADC.对于实际制作的ADC电路,具体给出了结构图以及动态性能测试图.     

基于阵列域大尺度衰落模型的1-bit大规模MIMO系统性能的分析

该文研究在阵列域大尺度衰落模型下,基站端天线仅仅配备了1-bit精度的模数转换器时大规模MIMO系统的性能。首先给出了系统采用最大比合并接收机时,用户上行可达速率的闭式表达式。然后分析了1-bit系统的功率效率性能,并将该1-bit系统与传统的具有无穷精度模数转换器的系统性能相比较。通过计算机仿真验证了该文的分析结果。该文指出基站端可以安装更多的天线来弥补1-bit精度的模数转换器所造成的性能损失。