Gasping the impact of on-chip inductance

The rapid advancements in process technology and heightening market pressures for functional integration are resulting in large VLSI chips operating at steadily increasing frequencies. The number of long global wires per chip has been continuously increasing with time. These wires carry high-frequency currents and have low resistance. This low resistance is due to the use of thick and wide interconnects at higher metal layers. Additionally, superior conducting materials such as copper have been introduced in order to keep the resistance and the RC delay of global lines small. These factors have led to a continuous increase in the importance of inductance, which has emerged as a standard factor that designers must take into consideration when designing high-performance chips in deep-submicron technologies. In this paper, the authors briefly discuss the importance, physical nature, effects, and extraction issues of on-chip inductance. Understanding the effects of on-chip inductance in high-speed integrated circuits is crucial to high-performance design     

Scaling trends of on-chip power distribution noise

The design of power distribution networks in high-performance integrated circuits has become significantly more challenging with recent advances in process technologies. As on-chip currents exceed tens of amperes and circuit clock periods are reduced well below a nanosecond, the signal integrity of on-chip power supply has become a primary concern in the integrated circuit design. The scaling behavior of the inductive and resistance voltage drops across the on-chip power distribution networks is the subject of this paper. The existing work on power distribution noise scaling is reviewed and extended to include the scaling behavior of the inductance of the on-chip global power distribution networks in high-performance flip-chip packaged integrated circuits. As the dimensions of the on-chip devices are scaled by S, where S>1, the resistive voltage drop across the power grids remains constant and the inductive voltage drop increases by S, if the metal thickness is maintained constant. Consequently, the signal-to-noise ratio decreases by S in the case of resistive noise and by S/sup 2/ in the case of inductive noise. As compared to the constant metal thickness scenario, ideal interconnect scaling of the global power grid mitigates the unfavorable scaling of the inductive noise but exacerbates the scaling of resistive noise by a factor of S. On-chip inductive noise will, therefore, become of greater significance with technology scaling. Careful tradeoffs between the resistance and inductance of the power distribution networks will be necessary in nanometer technologies to achieve minimum power supply noise.     

Statistical analysis of large on-chip power grid networks by variational reduction scheme

One of the most critical challenges in today's CMOS VLSI design is the lack of predictability in chip performance at design stage. One of the process variabilities comes from the voltage drop variations in on-chip power distribution networks. In this paper, we present a novel analysis approach for computing voltage drops of large power grid networks under process variations. The new algorithm is very efficient and scalable for huge networks with a large number of variational variables. This approach, called variational extended truncated balanced realization (varETBR), is based on model order reduction techniques to reduce the circuit matrices before the variational simulation. It performs the parameterized reduction on the original system using variation-bearing subspaces. After the reduction, Monte Carlo based statistical simulation is performed on the reduced system and the statistical responses of the original system are obtained thereafter. varETBR calculates variational response Grammians by Monte Carlo based numerical integration considering both system and input source variations in generating the projection subspace. varETBR is very scalable for the number of variables and flexible for different variational distributions and ranges as demonstrated in experimental results. Experimental results, on a number of IBM benchmark circuits up to 1.6 million nodes, show that the varETBR can be 1900X faster than the Monte Carlo method and is much more scalable than one of the recently proposed approaches.     

Circuits and techniques for high-resolution measurement of on-chip power supply noise

This paper presents a technique for characterizing the statistical properties and spectrum of power supply noise using only two on-chip low-throughput samplers. The samplers utilize a voltage-controlled oscillator to perform high-resolution analog-to-digital conversion with minimal hardware. The measurement system is implemented in a 0.13-/spl mu/m process along with a high-speed link transceiver. Measured results from this chip validate the accuracy of the measurement system and elucidate several aspects of power supply noise, including its cyclostationary nature.     

电网谐波环境下低压断路器运作影响量分析

电网谐波环境下,当低压断路器电流超过预设电流值,断路器会瞬时闭合,保护整个电网情况下会产生误操作,不仅对断路器机械结构造成损伤,且对分析精度有一定影响.提出构建热路数学模型,利用滑动时间窗口检测输入电流信号,分析电流并设置自适应电流值,计算各运作状态下的电力参数,实现电网谐波环境下低压断路器运作影响量的分析.实验结果表...     

电力设计与电网规划对电网安全的影响探究

当前市场经济得到了蓬勃发展,在新的发展环境下,对电力领域的改革也显得比较关键,这是满足人们日常生产生活需求的重要举措.在对电力的设计以及电网的规划环节要加强重视,这对电网的安全稳定运行也有着直接影响,基于此,本文主要就电力设计和电网规划对电网安全产生的影响详细分析,然后对电力设计和电网规划的原则以及要点详细探究,希望能通过此次理论研究,预祝与保障电网的安全.     

Nonlinear characteristics of on-chip spiral inductors under high RF power

This paper explores silicon CMOS on-chip spiral inductors performance degradation under high RF power. A novel methodology to calibrate and characterize on-chip spiral inductor with large signal inputs (high/medium power) is presented. Experiments showed 12% degradation of quality factor in a particular inductor design when 34 dBm RF power was applied. The degradation of quality factor of inductor can be attributed to a local self heating effect. Thermal imaging of such an inductor under high RF power validates the hypothesis.     

On grating lobes of uniformly spaced arrays under a double-sideband noise signal

The communication studies the attenuation on grating lobes of uniformly spaced arrays under a double-sideband noise signal. With a narrow signal bandwidth the envelope of the lobe attenuation is approximately a second-order equation     

电动汽车对电网的影响及有序充电研究

文章首先介绍了电动汽车规模化充电对电网的影响,进而提出了电动汽车有序充电的控制策略,希望能对相关研究者提供有益借鉴。     

On the signal dependence of avalanche noise generation

The influence of ionization in the drift space of an IMPATT diode on the noise generation in the avalanche process is studied. It is found that carrier generation by ionization in the drift space increases the current minima between the current pulses as generated in the avalanche region. The build-up of new avalanche current pulses therefore starts from a higher current level and consequently the behavior is less noisy. The effect of this decrease in noise on the IMPATT-diode oscillator FM noise is estimated.     

随机噪声信号的功率谱估计的仿真

在通讯与电子信息工程行业及领域中,大部分问题的解决需要进行估计一个随机信号在频率域上的功率谱分布,诸如此类的问题有很多,比如：设计滤波器消除噪声信号,振动随机信号的回波抵消,随机信号的特征抽取与表示等等。功率谱估计的分类：一般分为两大类,一类是参数法功率谱估计,一类是非参数法功率谱估计。参数法功率谱估计通常对数据进行一种建模,比如把数据建模成滑动平均模型（Moving Average）,或者自回归（Autoregressive）模型,而非参数法功率谱估计。除了要求信号满足广义平稳之外,不需要其它的统计假设。与非参数法相比较,参数法的优点是在一个给定的数据集合上能够有较少的误差、偏差与方差。     

一种强噪声背景下微弱信号检测方法研究

针对常规单混沌振子微弱信号检测方法存在检测过程不稳定的现象,将混沌吸引子与双振子差分检测技术相结合,提出一种通过调整系统稳定混沌态来检测微弱信号的改进方法,同时利用双差分振子来判别系统混沌态向周期状态转变的临界值。通过仿真分析,该方法可有效防止误判且实时性较好,有利于在强噪声背景下的微弱信号检测,为工程实际应用提供了一种可借鉴的方法。     

On the impact of the impulse noise on the WHT-OFDM transmission

Performance of the multicarrier spread-spectrum transmission in the presence of the impulse noise is studied. In the scheme considered, signal spreading is implemented by the Walsh-Hadamard transform, while multicarrier modulation is based on the orthogonal frequency division multiplexing. The formula for the symbol-error probability for such a transmission system with the QAM signaling is evaluated. Theoretical and simulation results show, that the impulse noise has significantly different effect on individual symbols in a sequence of simultaneously transmitted data. This effect depends on the Walsh spreading code assigned to the symbol and should be taken into account in the adopted noise mitigation strategy.     

On the detection of a signal in colored noise

A modeling approach is used in the detection of a random signal in colored noise. The received sequence is modeled as a regressive/autoregressive time series, and the presence or absence of the desired signal is determined through a hypothesis testing procedure. The test is based on the construction of anF-statistic using likelihood functions. The statistic can be easily incorporated into the computation of the probability of a false alarm, such as required in the processing of radar signals. Results based on simulated data and actual radar data are presented.This research was supported by NSERC Grant No. A3635.     

On the autocorrelation function of quantized signal plus noise

We derive, in this paper, an exact formula for the autocorrelation function of a quantized sum of a deterministic signal and Gaussian noise. This result shows that if the voltage between quantizing levels is small compared to the rms noise voltage, the quantized autocorrelation function differs from the unquantized autocorrelation function by an error term of simple form. An example is included to illustrate the analysis.     

宽带高斯型功率谱噪声信号相关特性分析

宽带噪声雷达具有良好的抗干扰和低截获性能.传统的窄带相关函数由于忽略了运动目标的多普勒色散效应而无法准确分析宽带信号的相关特性.本文以宽带噪声调频雷达测量高速目标为研究背景,推导了宽带相关函数均值的解析表达式,并对其进行了仿真验证.在此基础上分析得出,当多普勒色散积较大时宽带相关函数具有双峰特性,并揭示了其产生原因,指出了双峰位置与多普勒色散积及相对带宽之间的关系.为宽带高斯谱噪声雷达的分辨力和检测性能分析以及系统的参数设计提供了理论基础.     

Nonlinear algorithms for measuring the noise signal power against the background of interferences

Algorithms for measuring the power of mixture components of the noise signal and interferences by using functional transformations of the input mixture in the section of postdetection processing have been considered. The cases of narrowband and pulse interferences were investigated. The performance analysis of the algorithms was performed at different values of interference-to-signal ratio. The results of numerical experiments made it possible to find out the performance peculiarities of algorithms under different conditions.     

Quantifying the effect of local interconnects on on-chip power distribution

Existing methods to analyze and optimize on-chip power distribution networks typically focus only on global power network modeled as a two-dimensional mesh. In practice, current is supplied to switching transistors through a local power network at the lower metal layers. The local power network is connected to a global network through a stack of vias. The effect of these vias and the resistance of the local power network are typically ignored when optimizing a power network and placing decoupling capacitors. By modeling the power distribution network as a three-dimensional mesh, the error due to ignoring via and local interconnect resistances is quantified. It is demonstrated that ignoring the local power network and vias can both underestimate (by up to 45%) or overestimate (by up to 50%) the effective resistance of a power distribution network. The error depends upon multiple parameters such as the width of local and global power lines and via resistance. A design space is also generated to indicate the valid width of local and global power lines where the target resistance is satisfied. It is shown that a wider global network can be used to obtain a narrower local network, providing additional flexibility in the physical design process since routability is an important concern at lower metal layers. At high via resistances, however, this approach causes significant increase in the width of a global power network, indicating the growing significance of local power network and vias.     

On power allocation strategies for maximum signal to noise and interference ratio in an OFDM-MIMO system

Orthogonal frequency division multiplexing (OFDM) has been recently established for several systems such as HiperLAN/2 and Digital video/audio broadcasting, due the easy implementation of the modulator/demodulator and the equalizer. Moreover, also increasing interest is currently being put on multiple-input multiple-output (MIMO) channels, based on the use of antenna arrays at both the transmitter and the receiver. Here, we propose two joint beamforming strategies of low computational load for systems combining OFDM and MIMO. The ultimate objective is the maximization of the signal-to-noise and interference ratio (SNIR) over the carriers subject to a total transmit power constraint. Specifically, the maximization of the harmonic SNIR mean and the minimum SNIR over the subcarriers are proposed. The asymptotic behavior of the proposed methods is analyzed to provide a complete comparative and general view of the most relevant and already known transmit power allocation strategies. Finally, a theoretical analysis of the performance degradation of these techniques is carried out for the case in which the channel state information (CSI) is not perfect. Monte Carlo simulation results for the system bit-error rate and performance degradation with imperfect CSI are provided.     

Effect of source lead inductance on the noise figure of a GaAs FET

The noise performance of a GaAs FET (series Gat. 1, Plessey, England), operating in the pinchoff mode and in the common-source configuration, is examined neglecting thermal effects due to the velocity saturation. The complete equivalent circuit of the transistor including all extrinsic and package elements is used to obtain the noise figure of the transistor in the frequency region between 0.5 and 4 GHz. All computations of the noise figure are made using the noise model of van der Ziel.