AAC编码算法的快速实现

Advanced Audio Coding(AAC)是一种高质量的音频编码标准,其编码算法的运算复杂度很高。本文针对AAC的心理声学模型谱估计采用SDFT'谱代替标准建议的DFI'谱,对其比特分配模块则提出了一种自适应的最佳全局量化阶搜索方法,此外,还采用基于FFT的MDC'I'快速算法,大大降低了AAC编码算法的运算复杂度。     

基于AAC音频编码与混沌加密的语音加密技术实现

为了减少语音的加密数据量,在此提出一种基于压缩编码和混沌加密的语音加密方案。采用先编码后加密的实现方法,语音编码算法采用AAC低复杂度编码算法,加密算法采用二维猫映射算法,在ARM9硬件平台下的实现结果表明AAC编码压缩比为18∶1,猫映射加解密算法执行效率快,解密后无失真,实验结论证实该方案是可行的。在此将音频压缩算法与混沌加密结合起来,在不影响语音音质和加密效果的前提下减少了加密运算的数据量以及最终加密文件的大小,缩短了加解密语音数据所花费的时间,减少了语音保密通信所需要的带宽。     

MPEG-4 AAC解码器在NIOS Ⅱ平台上的实现和优化

给出了MEPG-4AAC实时解码器在NIOSⅡ平台的实现方案，介绍了MPEG-4AAC—LC解码算法及各关键模块优化算法。在完成实时解码要求下，结合NIOSⅡ平台特性，对解码器在软件代码与处理器上进行优化。实验结果表明CPU时钟为80MHz时能达到实时解码要求。     

基于XScale平台的MPEG-4 AAC解码器Huffman算法优化

Huffman算法的实现是MPEG-4 AAC解码的一个关键部分,它在整个解码算法中占有很大的运算比重和内存开销。讨论了不同的Huffman解码算法及其改进,结合AAC解码器不同码表的特点,针对XScale处理器选择了其合适的Huffman解码算法,并对每种选择的算法从提高解码效率、减少内存开销的角度进行了优化．达到了理想的效果。     

MPEG-4 AAC解码器在TMS320C6416上的实现

结合定点DSP芯片TMS320C6416，给出了MPEG-4AAC(LC)音频解码器在其测试评估平台(TEB)上的实现方案，并从多方面对AAC(LC)解码器进行了优化设计。实验结果表明，在确保音频解码质量的同时，算法的运行速度和存储器占用情况都有了较大的改善，为视频及其它应用留下了充足的处理空间。     

基于软硬件协同的AAC和AVS音频可重构解码器

在分析AAC和AVS音频特点的基础上提出了1种软硬件协同的AAC和AVS音频可重构解码器设计方案,这种方案能以很少资源以及较低的运行频率来实现2种压缩标准的解码。     

AAC音频解码器中TNS模块的设计及其ASIC实现

时域噪声整形(TNS)是AAC音频解码器中较为重要的一部分。文章介绍了时域噪声整形的作用、基本原理、算法设计以及硬件设计思路,并且给出了该滤波器的ASIC实现。在设计中,我们采用时分复用技术,既TNS滤波器和AAC解码器的其它硬件部分时分复用一个乘法器,从而大大节省了硬件开销。在TNS滤波器中,所有的乘法运算采用24×18的定点乘法运算,和原来我们在软件中采用的32×32的浮点运算相比,计算精度有所降低,但通过人耳的主观测试,并未发现音质有明显的降低。     

卫星数字声广播信源编码CMP3和AAC的比较

最近10余年基于感知音频编码的高质量Hi-Fi音频压缩方法已取得突破，本文简要介绍感知音频编码原理，然后分别叙述MP3和MPEG－2 AAC的算法，并对高质量音频编码的主观评价方法作了介绍，给出了MP3和AAC的主观评价结果，在128kbps/2-channel时AAC的重建音质明显高于MP3，最后给出了AAC的其它特点。     

高频重建技术SBR的研究与实现

AAC是MPEG-4标准的音频编码规范，为了提高音频数据的压缩率，往往忽略了音频中所包含的高频成分，只对低频部分进行编码，因此AAC解码器设计中高频重建技术对提高音频质量起着非常重要的作用．本文论述了高频重建技术的原理，并采用SBR技术，实现了AAC音频编码的高频重建，同时性能评测结果表明所实现的AAC SBR系统满足实际应用的要求．     

基于微处理器核的媒体系统芯片结构设计

围绕基于微处理器核的AAC解码器结构设计展开讨论，对IP定制、数据通路及存储设计进行了研究，并成功开发了一个基于微处理器核的MPEG-4AAC解码系统芯片。     

MPEG-2 AAC解码器的优化算法

作为新一代的音频编码国际标准,先进音频编码(AAC)提供了良好的压缩性能,具有广阔的发展和应用前景。但是由于AAC标准给出的算法比较复杂,按照标准算法进行测试时发现其并不能满足实时解码的要求,因此,必须对标准算法进行优化以达到实时解码的要求。在叙述了MPEG-2 AAC解码器的模块组成和原理的基础上,针对各个模块的特点采用优化算法,对MPEG-2 AAC解码器的部分模块进行了优化设计,较大程度地提高了解码速度。     

简述AAC快速算法实现的几种途径

高级音频编码目前被广泛应用,但其算法复杂度高、速度慢,无法满足实时性要求。从不同模块方面简要总结了几种高级音频编码的快速算法,为从事相关研究的工作者提供参考。     

MPEG-2／4AAC音频编码器的低复杂度优化

优化了MPEG-2／4AAC编码器的复杂度,并在定点数字信号处理器（DSP）上实现了相应的优化编码器。提出了一种迭代求解非线性频谱量化比例因子的方法及一种不需要再量化的比特率控制方法。与定点DSP实现技术相结合,这两种方法可将编码器的运行效率相对参考代码提高30倍,而音质只有轻微下降。这使得移动设备上的高质量音频应用成为可能。     

Low-Power System Design for MPEG-2/4 AAC Audio Decoder Using Pure ASIC Approach

This paper presents an implementation of a low-power and pure-hardware advanced-audio-coding (AAC) audio decoder system. Based on the characteristics of each decoding block, the AAC system is partitioned into four separate modules. For low-power and low-complexity considerations, architectural- and algorithmic-level approaches are adopted in both individual modules and whole system. In parallel PLA-based codeword decoder, we achieve a constant output rate of Huffman decoding in 2.5 cycles for the worst case, and memory usage is decreased compared to that in the binary-tree memory-based method. In reduced lookup table inverse quantizer, a table lookup with interpolation scheme is adopted which reduces the size of the lookup table from 8192 to 256. In hardware-shared signal processor, we use a hardware-sharing technique which integrates several similar blocks into a common hardware to reduce cost and enhance hardware utilization. In fully pipelined filterbank, a fast algorithm decreases the numbers of multiplication and addition largely to factors of 24 and 144 for the short and long blocks, respectively. A corresponding hardware for filterbank processing is proposed with fully pipelined architecture. Referring to stereo processing, a single hardware is shared for the channel pairs with low-cost consideration. The hardware operations of each module are well scheduled with high utilization of pipeline, and furthermore, the parallel processing among blocks is joined to increase efficiency. A 48% power savings can be reached by using the pipeline and parallel techniques of the channel pair. The proposed AAC decoder is realized in UMC 0.18-${rm mu}hbox{m}$ 1P6M technology and is operated at only 3 MHz in the worst case. The power dissipation is only 2.45 mW at the sampling frequency of 44.1 kHz.      

MPEG-4 AAC解码器在NIOS II平台上的实现和优化

给出了MEPG-4AAC实时解码器在NIOSII平台的实现方案,介绍了MPEG-4AAC-LC解码算法及各关键模块优化算法。在完成实时解码要求下,结合NIOSII平台特性,对解码器在软件代码与处理器上进行优化。实验结果表明CPU时钟为80MHz时能达到实时解码要求。     

高效实时MPEG-2/4 AAC编码器的实现

介绍了一种高效的MPEG-2/4AAC低复杂度编码器的实现。由于MPEG-2/4AAC算法计算量相当大,为了达到实时性,对窗切换方法、心理声学模型、比特分配、滤波器等模块进行了优化,使其在Pentium41.8GHz处理器上达到比实时编码快4倍的编码速度。而且利用M/S编码和Huffman码表的有效选择,提高了声音质量。     

MP3／AAC解码器中Huffman硬件加速器设计与实现

Huffman解码是感知音频解码过程的重要部分。软件实现Huffman解码运算,计算速度慢、功耗高,采用硬件实现的方法,设计并实现了一个兼容MP3与AAC标准的Huffman解码硬件加速器。采用十六叉树搜索算法．在存储空间增加不大的情况下,有效减少了Huffman码字的搜索深度,简化寻址操作,加快了搜索速度。通过直接外设访问的接口设计,该硬件加速器还可快速进行音频码流的数据读取。在XilinixFPGA上的功能和性能验证表明。该Huffman硬件加速器可成功应用于MP3和AAC解码器。     

Joint optimization of scale factors and Huffman code books for MPEG-4 AAC

This paper addresses the optimization problem of minimizing the distortion subject to a rate constraint for an MPEG-4 Advanced Audio Coding (AAC) encoder. We first develop a mathematical model of the AAC encoding process. In previous work, the joint optimization problem is modeled as a Viterbi search for a cheapest path through a trellis. This method involves an iteration over a Lagrangian multiplier. We improve on this method by deriving a very accurate guess for the value of the final Lagrangian multiplier of the iteration as a function of the Perceptual Entropy of the signal and the given rate constraint. This reduces the complexity of the Trellis Search significantly. Whereas previous methods including the Trellis Search did not provide optimal solutions to the problem of minimizing the distortion subject to a rate constraint, we establish two methods that for the first time solve this problem optimally. Our first method is based on the formulation and solution of a Mixed Integer Linear Program, whereas our second method uses a Dynamic Programming solution that does not rely on the iteration over a Lagrangian multiplier. Based on our optimal methods, we evaluate the performance of the heuristic Two Loop Search (TLS), which is used in most commercial AAC implementations to solve the problem under consideration, and the performance of the Trellis Search.     

Common Architecture Design of Novel Recursive MDCT and IMDCT Algorithms for Application to AAC, AAC in DRM, and MP3 Codecs

This paper presents a novel recursive algorithm to compute the modified discrete cosine transform (MDCT) and the inverse MDCT (IMDCT) based on type IV of the discrete cosine transform (DCT-IV) algorithm. The proposed algorithm has the following advantages: In contrast with parallel designs, the input sequence fed by serial in/serial out (SISO) can dynamically be switched with the variable window length. The data throughput per transformation for the MDCT and IMDCT algorithms is four times higher than that of the previous algorithms, and the ROM size can be reduced by 50%-79%. Less memory is required for accessing; thus, it can reduce the chip area in hardware implementation. The chip efficiency is also increased, and the proposed architecture makes a feasible design to integrate several audio standards [i.e., advanced audio coding (AAC)/AAC in digital radio mondiale (DRM/MPEG-1 Audio Layer 3 (MP3)] into one portable media player. The proposed algorithm is designed and fabricated by using 0.18-mum 1P6M complimentary metal-oxide-semiconductor (CMOS) process. The core area is 441 times 437 mum², including the MDCT, IMDCT, and DCT-IV modules. For modern audio applications, i.e., AAC/AAC in DRM/MP3, this processor only consumes 14.077/3.482/0.3138 mW at 50/12.5/1 MHz. Furthermore, the proposed algorithm can calculate the 2048/1920/256/240/36/12-point MDCT and the 1024/960/128/120/18/6-point IMDCT.