An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation

A distributed DLL (DDLL) with low jitter and high phase accuracy is proposed for the multiphase clock generator. The high-speed multiphase clock generator produces a five-phase clock at a frequency range of 8 to 10 GHz. Additionally, the discrete-time model for the distributed DLL and the analysis about stability and noise are proposed in this work. The measured rms jitter is 293.3 fs and the maximum phase mismatch is 1.4 ps. The proposed architecture can suppress the jitter by 58%. The distributed DLL occupies 0.03 ${hbox{mm}}^{2}$ active area in a 90-nm CMOS technology and consumes 15 mA from a 1.0-V supply.      

CMOS Oscillators for Clock Distribution and Injection-Locked Deskew

The distribution and alignment of high-frequency clocks across a wide bus of links is a significant challenge in modern computing systems. A low power clock source is demonstrated by incorporating a buffer into a cross-coupled oscillator. Because the load is isolated from the tank, the oscillator can directly drive 50-Ohm impedances or large capacitive loads with no additional buffering. Using this topology, a quadrature VCO (QVCO) is implemented in 0.13 $mu hbox{m}$ digital CMOS. The QVCO oscillates at 20 GHz, consumes 20 mW and provides 12% tuning range. The measured phase noise is $-101~hbox{dBc}/hbox{Hz}$ @ 1 MHz frequency offset. A clock alignment technique based upon injection-locked quadrature-LC or ring oscillators is then proposed. Although injection-locked oscillators (ILOs) are known to be capable of deskewing and jitter filtering clocks, a study of both LC and ring ILOs indicates significant variation in their jitter tracking bandwidth when used to provide large phase shifts. By selectively injecting different phases of a quadrature-LC or ring VCO, this problem is obviated resulting in reduced phase noise. The technique is demonstrated using a LC QVCO at 20 GHz while burning only 20 mW of power and providing an 8 dB improvement in phase noise. A ring oscillator deskews a 2 to 7 $~$GHz clock while consuming 14 mW in 90 nm CMOS.      

Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops

This brief analyzes the jitter as well as the power dissipation of phase-locked loops (PLLs). It aims at defining a benchmark figure-of-merit (FOM) that is compatible with the well-known FOM for oscillators but now extended to an entire PLL. The phase noise that is generated by the thermal noise in the oscillator and loop components is calculated. The power dissipation is estimated, focusing on the required dynamic power. The absolute PLL output jitter is calculated, and the optimum PLL bandwidth that gives minimum jitter is derived. It is shown that, with a steep enough input reference clock, this minimum jitter is independent of the reference frequency and output frequency for a given PLL power budget. Based on these insights, a benchmark FOM for PLL designs is proposed.      

A 2.5-GHz Built-in Jitter Measurement System in a Serial-Link Transceiver

A 2.5-GHz built-in jitter measurement (BIJM) system is adopted to measure the clock jitter on a transmitter and receiver. The proposed Vernier caliper and autofocus approaches reduce the area cost of delay cells by 48.78% relative to pure Vernier delay line structure with a wide measurement range. The counter circuit occupies an area of 19 $mu$ m $times$ 61 $mu$ m in the traditional stepping scan approach. The proposed equivalent-signal sampling technique removes the input jitter transfer path from the sampling clock. The power supply rejection design is incorporated into the delay cell and the judge circuit. The layout implementation, calibration, and test time of the proposed BIJM system are all improved. The core circuit occupies an area of only 0.5 mm $times$ 0.15 mm with the 90-nm CMOS process. The Gaussian and uniform distributions jitter is verified at a 5-ps timing resolution and a 2.5-GHz input clock frequency .      

A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop

This paper introduces a pulse injection-locked oscillator (PILO) that provides low jitter clock multiplication of a clean input reference clock. A mostly-digital feedback circuit provides continuous tuning of the oscillator such that its natural frequency is locked to the injected frequency. The proposed system is demonstrated with a prototype consisting of a custom 0.13 $mu$m integrated circuit with active area of 0.4 mm$^{2}$ and core power of 28.6 mW, along with an FPGA, a discrete DAC and a simple RC filter. Using a low jitter 50 MHz reference input, the PILO prototype generates a 3.2 GHz output with integrated phase noise, reference spur, and estimated deterministic jitter of 130 fs (rms), ${-}$ 63.9 dBc, and 200$~$ fs (peak-to-peak), respectively.      

An FIR-Embedded Noise Filtering Method for $Delta Sigma$ Fractional-N PLL Clock Generators

This paper describes a noise filtering method for $Delta Sigma$ fractional- $N$ PLL clock generators to reduce out-of-band phase noise and improve short-term jitter performance. Use of a low-cost ring VCO mandates a wideband PLL design and complicates filtering out high-frequency quantization noise from the $Delta Sigma$ modulator. A hybrid finite impulse response (FIR) filtering technique based on a semidigital approach enables low-OSR $Delta Sigma$ modulation with robust quantization noise reduction despite circuit mismatch and nonlinearity. A prototype 1-GHz $Delta Sigma$ fractional-$N$ PLL is implemented in 0.18 $muhbox{m}$ CMOS. Experimental results show that the proposed semidigital method effectively suppresses the out-of-band quantization noise, resulting in nearly 30% reduction in short-term jitter.      

Characterizing the effects of the PLL jitter due to substrate noise in discrete-time delta-sigma modulators

This paper investigates the impact of clock jitter induced by substrate noise on the performance of the oversampling /spl Delta//spl Sigma/ modulators. First, a new stochastic model for substrate noise is proposed. This model is then utilized to study the clock jitter in clock generators incorporating phase-locked loops (PLLs). Next, the effect of the clock jitter on the performance of the /spl Delta//spl Sigma/ modulator is studied. It will be shown that substrate noise degrades the signal-to-noise ratio of the /spl Delta//spl Sigma/ modulator while the noise shaping does not have any effect on clock jitter induced by substrate noise. To verify the analysis experimentally, a circuit consisting of a second-order /spl Delta//spl Sigma/ modulator, a charge-pump PLL, and forty multistage digital tapered inverters driving 1-pF capacitors is designed in a 0.25-/spl mu/m standard CMOS process. Several experiments on the designed circuit demonstrate the high accuracy of the proposed analytical models.     

A Low-Power and High-Precision Spread Spectrum Clock Generator for Serial Advanced Technology Attachment Applications Using Two-Point Modulation

A new technique utilizing two-point (TP) modulation for a spread spectrum clock generator (SSCG) for serial advanced technology attachment is presented in which the divider ratio is varied by a digital ${Sigma}{Delta}$ modulator, and the voltage-controlled oscillator is modulated analogically. With this technique, the modulation bandwidth is enhanced in order that the modulation profile accuracy and jitter performance caused by the ${Sigma}{Delta}$ modulator can be improved at the same time. The order of the ${Sigma}{Delta}$ modulator and the loop filter can be reduced to save power and area, while the electromagnetic interference (EMI) suppression still satisfies specifications. The dual-path loop filter (DL) reduces the size of the loop capacitor and enables full integration. The proposed TPDL-SSCG has been fabricated in a 0.18- $mu$m CMOS process. The size of the chip area is $hbox{0.44} times hbox{0.48 mm}^{2}$. The circuit produces a clock of 1.5 GHz with a down-modulation ratio of 0.5%, 10.14 dB EMI of reduction, 5.485 ps rms jitter, and 35 ps peak-to-peak jitter. The power consumption, excluding an output buffer, is only 15.3 mW.      

A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces

A DLL featuring jitter reduction techniques for a noisy environment is described. It controls a loop response mode by monitoring the magnitude of input jitter caused by supply noise. This technique varies the probability of phase error tracking. It reduces the output jitter of the DLL due to a low effective variance of input phase error and a narrow effective loop bandwidth. The DLL is implemented in a 0.13 $muhbox{m}$ CMOS process. Under noisy environments, the output clock of 1 GHz has 4.58 ps RMS and 29 ps peak-to-peak jitter.      

A Single-Stage Direct Interpolation Multiphase Clock Generator with Phase Error Averaging

Multiphase clock generators are conventionally implemented with a feedback loop. This paper presents a non-feedback approach to generate multiphase clocks. A simple architecture of direct phase interpolation is proposed, in which the edges of two phase-adjacent signals are used to control the discharge (or charge) of two capacitors respectively, producing time-overlapped slopes. A resistor chain connected to the two capacitors is used to interpolate a number of new slopes in between. The generated phase resolution depends on the number and ratios of resistors thus is not limited by an inverter delay. Based on this architecture, a multiphase clock generator is developed. In addition, a phase error averaging circuit is used to correct interphase errors. The multiphase clock generator has been fabricated in a 0.35 m, 3.3 V CMOS process. The measured performance shows it can produce 8 evenly spaced clock signals in one input clock period and work in an input clock range from 300 MHz to 600 MHz. The measured maximum jitter performance is rms 6.8 ps and peak-to-peak 47 ps, respectively.     

A Three-Dimensional Stacked-Chip Star-Wiring Interconnection for a Digital Noise-Free and Low-Jitter I/O Clock Distribution Network

Cascaded repeaters are indispensable circuit elements in conventional on-chip clock distribution networks due to heavy loss characteristics of on-chip global interconnections. However, cascaded repeaters cause significant jitter and skew problems in clock distribution networks when they are affected by power supply switching noise generated by digital logic blocks located on the same die. In this letter, we present a new three-dimensional (3-D) stacked-chip star-wiring interconnection scheme to make a clock distribution network free from both on-chip and package-level power supply noise coupling. The proposed clock distribution scheme provides an extremely low-jitter and low-skew clock signal by replacing the cascaded repeaters with lossless star-wiring interconnections on a 3-D stacked-chip package. We have demonstrated a 500-MHz input/output (I/O) clock delivery with 34-ps peak-to-peak jitter and a skew of 11ps, while a conventional I/O clock scheme exhibited a 146-ps peak-to-peak jitter and a 177-ps skew in the same power supply noise environment     

A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology

A 33.6–33.8 Gb/s burst-mode clock/data recovery circuit (BMCDR) is presented in this paper. To reduce the data jitter and generate the high-frequency output clock, the LC gated voltage-controlled oscillator is presented. To receive and transmit the broadband data, a wideband input matching circuit and a wideband data buffer are presented, respectively. The phase selector is proposed to overcome the false phase lock due to the full-rate operation. This proposed BMCDR has been fabricated in a 90 nm CMOS process. The measured peak-to-peak and rms jitters for the recovered data are 7.56 ps and 1.15 ps, respectively, for a 33.72 Gb/s, 2 $^{11} -$1 PRBS. The measured bit error rate is less than $10^{-8}$ for a 33.72 Gb/s, 2$^{7} -$1 PRBS. It consumes 73 mW without buffers from a 1.2 V supply.      

Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-Performance Microprocessors

We propose injection-locked clocking (ILC) to combat deteriorating clock skew and jitter, and reduce power consumption in high-performance microprocessors. In the new clocking scheme, injection-locked oscillators are used as local clock receivers. Compared to conventional clocking with buffered trees or grids, ILC can achieve better power efficiency, lower jitter, and much simpler skew compensation thanks to its built-in deskewing capability. Unlike other alternatives, ILC is fully compatible with conventional clock distribution networks. In this paper, a quantitative study based on circuit and microarchitectural-level simulations is performed. Alpha21264 is used as the baseline processor, and is scaled to 0.13 $mu$ m and 3 GHz. Simulations show 20- and 23-ps jitter reduction, 10.1% and 17% power savings in two ILC configurations. A test chip distributing 5-GHz clock is implemented in a standard 0.18- $mu$m CMOS technology and achieved excellent jitter performance and a deskew range up to 80 ps.      

An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics

This paper describes an area-effective 1.5-Gb/s transceiver core with spread spectrum clocking (SSC) capability that is suitable for integration into large system-on-chips (SoCs) for consumer electronics applications such as audio and video stream data transmission. To achieve a good balance between SSC performance and the core area, a novel SSC scheme using a multi-level (hierarchical) phase-interpolator technique has been developed. This technique achieves a very fine clock phase shift of about 0.1 ps for precise and smooth frequency modulation. The SSC scheme is based on a digital feed-forward operation and leads to a small area and good noise robustness for SoC integration. This core also has digital clock data recovery (CDR) with jitter tolerance enhancement and a simple adaptive data equalizer (AEQ). These functions are also on a digital operation and controlled by digital codes, and the core presupposes a multiphase clock for the digital SSC, CDR, and AEQ with shared phase-locked loop (PLL) topology. A test chip including two of these cores was fabricated using shared PLL. The core showed significant peak power reduction ($-$19 dB to the non-SSC situation) and a small core area of 0.25 mm $^{2}$ in 0.13- $mu$m CMOS process. This core achieved a remarkable ratio of peak power reduction to area of 76 dB/mm $^{2}$. Moreover, it achieved good jitter tolerance (flat 0.8 UI at $> $1 MHz) and stable data communication over an STP (shielded twist pair) cable ranging in length from 1 m to over 22 m.      

An Infinite Phase Shift Delay-Locked Loop With Voltage-Controlled Sawtooth Delay Line

A wide-range delay-locked loop (DLL) with infinite phase shift and digital-controlled duty cycle is presented. By changing the polarity of the input clock of the voltage-controlled sawtooth delay, this proposed DLL achieves infinite phase shift by only a single loop. The proposed DLL has been fabricated in a 0.18$ mu$m CMOS process and the core area is $hbox{0.45}times {hbox{0.3 mm}}^{2}$. The measurement results show the proposed DLL operates from 50 to 500 MHz. The duty cycle of the output clock can be adjusted from 30% to 60% in the step of 5%. At 500 MHz, the measured rms jitter and peak-to-peak jitter is 1.43 and 11.1 ps, respectively. Its power consumption is 6 mW for a supply of 1.5 V.      

Analysis of Clock-Jitter Effects in Continuous-Time $Delta Sigma $ Modulators Using Discrete-Time Models

This paper proposes a simple discrete-time (DT) modeling technique for the rapid, yet accurate, simulation of the effect of clock jitter on the performance of continuous-time (CT) $Delta Sigma $ modulators. The proposed DT modeling technique is derived from the impulse-invariant transform and is applicable to arbitrary-order lowpass and bandpass CT $Delta Sigma $ modulators, with single-bit or multibit feedback digital-to-analog converters (DACs) employing delayed return-to-zero (RZ) or non-return-to-zero (NRZ) rectangular pulses. Its accuracy is independent of both the power spectrum of the clock jitter and the loop transfer function of the $Delta Sigma $ modulator.      

A CMOS Low Noise, Chopper Stabilized Low-Dropout Regulator With Current-Mode Feedback Error Amplifier

Low $1/f$ noise, low-dropout (LDO) regulators are becoming critical for the supply regulation of deep-submicron analog baseband and RF system-on-chip designs. A low-noise, high accuracy LDO regulator (LN-LDO) utilizing a chopper stabilized error amplifier is presented. In order to achieve fast response during load transients, a current-mode feedback amplifier (CFA) is designed as a second stage driving the regulation FET. In order to reduce clock feed-through and $1/f$ noise accumulation at the chopping frequency, a first-order digital ${Sigma}{Delta}$ noise-shaper is used for chopping clock spectral spreading. With up to 1 MHz noise-shaped modulation clock, the LN-LDO achieves a noise spectral density of 32 ${hbox{nV}}/{surd}{hbox{Hz}}$ and a PSR of 38 dB at 100 kHz. The proposed LDO is shown to reduce the phase noise of an integrated 32 MHz temperature compensated crystal oscillator (TCXO) at 10 kHz offset by 15 dB. Due to reduced $1/f$ noise requirements, the error amplifier silicon area is reduced by 75%, and the overall regulator area is reduced by 50% with respect to an equivalent noise static regulator. The current-mode feedback second stage buffer reduces regulator settling time by 60% in comparison to an equivalent power consumption voltage mode buffer, achieving 0.6 $mu{hbox{s}}$ settling time for a 25-mA load step. The LN-LDO is designed and fabricated on a 0.25 $mu{hbox{m}}$ CMOS process with five layers of metal, occupying 0.88 ${hbox{mm}}^{2}$.      

Clock jitter impact on the performance of general charge sampling amplifiers

In this paper we present the detailed performance analysis of general charge sampling amplifiers (CSAs) due to clock jitter impact. A simple analytical model for quick estimation of the signal-to-noise ratio by considering clock jitter alone as a noise source is proposed for a general CSA. The proposed analytical model is compared with a previously published more complex model and also with the well known voltage sampling. Simulation results showing the performance due to clock jitter impact of CSAs are also presented here to confirm the proposed analytical model. The potential advantages of clock jitter tolerances in charge sampling are discussed in detail.     

A Mixed-Mode Synchronous Mirror Delay Insensitive to Supply and Load Variations

A digital synchronous mirror delay combined with an analog delay-locked loop (DLL) is introduced. Under the influence of process, voltage, temperature, and load variations, the conventional digital synchronous mirror delay could not compensate the static phase error because of its digital type and open loop by nature. The proposed circuit can compensate the delay mismatch between the output buffer and the inner stage, which is caused by the different loading conditions. It can improve the noise immunity from supply variations. Moreover, because of the tracking property of the DLL, the static phase error and jitter could also be reduced. The proposed circuit has been fabricated by a CMOS 0.35-m one-poly four-metal process and the whole chip area is 1.47 × 1.07 mm² including I/O pad peripherals. The measured peak-to-peak jitter is 16.4 ps at supply voltage of 3.3 V and frequency of 300 MHz. The power consumption of the entire chip is 16.5 mW for analog part and 84 mW for digital part. The comparisons between the proposed circuit and the conventional digital synchronous mirror delay are also demonstrated.     

A 2.5 Gb/s Run-Length-Tolerant Burst-Mode CDR Based on a 1/8th-Rate Dual Pulse Ring Oscillator

A 2.5 Gb/s burst-mode clock and data recovery (CDR) circuit is presented that uses a 1/8th-rate ring oscillator with two pulses running simultaneously that are phase independent. One “tune” pulse sets the delay of the ring by phase locking it to a reference. The other “clock” pulse tracks the phase of the incoming data by a process of pulse removal and reinsertion. Because both pulses share the same ring, there is no frequency mismatch between the incoming data stream and the recovered clock in frequency synchronous systems, allowing for large data run lengths. A 1:8 data-demux clock is naturally generated by tapping the clock pulse along the ring. Phase acquisition is instantaneous from a single data edge. Run length tolerance is larger than 72 bits. The 0.6 mm$^{2}$ 0.13 $mu$m CMOS chip includes a CML-to-CMOS input buffer, PLL with on-chip loop filter, PRBS checker, 1:8 data demux, and eight output buffers. It has 2.7 ${rm UI}_{rm pp}$ measured jitter tolerance at 100 kHz and consumes 42 mW from a single 1.2 V supply.