Electrostatics of coaxial Schottky-barrier nanotube field-effect transistors

Analytical and numerical methods are used to solve Poisson's equation for carbon nanotube field-effect transistors (FETs) with a cylindrical surrounding gate and Schottky-barrier contacts to the source and drain. The effect on the nanotube potential profile of varying the work functions of all the electrodes, and the thickness and permittivity of the gate dielectric, is investigated. From these results, the general trends to be expected in the above-threshold drain current-voltage characteristics of Schottky-barrier nanotube FETs are predicted. The unusual possibility of simultaneous electron and hole contributions to the drain current is revealed. The subthreshold characteristics are computed from a solution to Laplace's equation, and the subthreshold slope is found to depend on gate dielectric thickness in a different manner from that in other FETs.     

Reconfigurable silicon nanowire transistors

Over the past 30 years electronic applications have been dominated by complementary metal oxide semiconductor (CMOS) devices. These combine p- and n-type field effect transistors (FETs) to reduce static power consumption. However, CMOS transistors are limited to static electrical functions, i.e., electrical characteristics that cannot be changed. Here we present the concept and a demonstrator of a universal transistor that can be reversely configured as p-FET or n-FET simply by the application of an electric signal. This concept is enabled by employing an axial nanowire heterostructure (metal/intrinsic-silicon/metal) with independent gating of the Schottky junctions. In contrast to conventional FETs, charge carrier polarity and concentration are determined by selective and sensitive control of charge carrier injections at each Schottky junction, explicitly avoiding the use of dopants as shown by measurements and calculations. Besides the additional functionality, the fabricated nanoscale devices exhibit enhanced electrical characteristics, e.g., record on/off ratio of up to 1 × 10(9) for Schottky transistors. This novel nanotransistor technology makes way for a simple and compact hardware platform that can be flexibly reconfigured during operation to perform different logic computations yielding unprecedented circuit design flexibility.     

Polymer nanowire vertical transistors

By utilizing poly（3-hexylthiophene） （P3HT） polymer nanowires with diameters of -15 nm as the vertical channel material, a polymer nanowire vertical transistor has been demonstrated for the first time. The P3HT nanowires were characterized by absorption spectroscopy and scanning electron microscopy. A saturated output current was created by increasing the thickness of the polymer layers between the electrodes through several spin-coating cycles of the polymer nanowires prepared in a marginal solvent. The carrier mobility was also increased through utilization of polymer nanowires with strong interchain interactions. By introducing a small hole injection barrier between the emitter and semiconducting polymer, an on/off current ratio of 1,500 was obtained. The operating voltage is less than 2 V.     

SiGe nanowire field effect transistors

Si0.5Geo0.5 nanowires have been utilized to fabricate source-drain channels of p-type field effect transistors (p-FETs). These transistors were fabricated using two methods, focused ion beam (FIB) and electron beam lithography (EBL). The electrical analyses of these devices show field effect transistor characteristics. The boron-doped SiGe p-FETs with a high-k (HfO2) insulator and Pt electrodes, made via FIB produced devices with effective hole mobilities of about 50 cm2V(-1)s(-1). Similar transistors with Ti/Au electrodes made via EBL had effective hole mobilities of about 350 cm2V(-1)s(-1).     

High electron mobility InAs nanowire field-effect transistors

Single-crystal InAs nanowires (NWs) are synthesized using metal-organic chemical vapor deposition (MOCVD) and fabricated into NW field-effect transistors (NWFETs) on a SiO(2)/n(+)-Si substrate with a global n(+)-Si back-gate and sputtered SiO(x)/Au underlap top-gate. For top-gate NWFETs, we have developed a model that allows accurate estimation of characteristic NW parameters, including carrier field-effect mobility and carrier concentration by taking into account series and leakage resistances, interface state capacitance, and top-gate geometry. Both the back-gate and the top-gate NWFETs exhibit room-temperature field-effect mobility as high as 6580 cm(2) V(-1) s(-1), which is the lower-bound value without interface-capacitance correction, and is the highest mobility reported to date in any semiconductor NW.     

High performance horizontal gate-all-around silicon nanowire field-effect transistors

Semiconducting nanowires have been pointed out as one of the most promising building blocks for submicron electrical applications. These nanometer materials open new opportunities in the area of post-planar traditional metal-oxide-semiconductor devices. Herein, we demonstrate a new technique to fabricate horizontally suspended silicon nanowires with gate-all-around field-effect transistors. We present the design, fabrication and electrical measurements of a high performance transistor with high on current density (～150?μA?μm(-1)), high on/off current ratio (10(6)), low threshold voltage (～?-?0.4?V), low subthreshold slope (～100?mV /dec) and high transconductance (g(m)?～?9.5?μS). These high performance characteristics were possible due to the tight electrostatic coupling of the surrounding gate, which significantly reduced the Schottky-barrier effective height, as was confirmed experimentally in this study.     

Electrically excited infrared emission from InN nanowire transistors

We report electrically excited infrared emission from a single InN nanowire transistor. We report on: (1) the generation of IR emission by impact excitation of carriers under a high electrical field, (2) the size of the fundamental band gap of InN NW by measuring its emission spectra, (3) the observation of interband and conduction-band to conduction-band hot-carrier emission, and the carrier relaxation rate, and finally, (4) we present evidence that suggests that the electron accumulation layer at the InN NW surface forms a surface plasmon that couples to and enhances radiative electron-hole pair recombination.     

Enhanced channel modulation in dual-gated silicon nanowire transistors

Dual-gated silicon nanowire (SiNW) field-effect transistors (FETs) have been fabricated by using electron-beam lithography. SiNW devices (W approximately 60 nm) exhibit an on/off current ratio greater than 10(6), which is more than 3 orders of magnitude higher than that of control devices prepared simultaneously having a large channel width (approximately 5 microm). In addition, by changing the local energy-band profile of the SiNW channel, the top gate is found to suppress ambipolar conduction effectively, which is one of the factors limiting the use of nanotube or nanowire FETs for complimentary logic applications. Two-dimensional numerical simulations show that the gate-induced electrostatic control is improved as the channel width of the FETs decreases. Therefore, enhanced channel modulations can be achieved in these dual-gated SiNW devices.     

Optical switching of porphyrin-coated silicon nanowire field effect transistors

We study porphyrin derivative coated silicon nanowire field effect transistors (SiNW-FETs), which display a large, stable, and reproducible conductance increase upon illumination. The efficiency and the kinetics of the optical switching are studied as a function of gate voltage, illumination wavelength, and temperature. The decay kinetics from the high- to the low-conductance state is governed by charge recombination via tunneling, with a rate depending on the state of the SiNW-FET. The comparison to porphyrin-sensitized carbon nanotube FETs allows the environment- and molecule-dependent photoconversion process to be distinguished from the charge-to-current transducing effect of the semiconducting channel.     

Room-temperature terahertz detectors based on semiconductor nanowire field-effect transistors

The growth of semiconductor nanowires (NWs) has recently opened new paths to silicon integration of device families such as light-emitting diodes, high-efficiency photovoltaics, or high-responsivity photodetectors. It is also offering a wealth of new approaches for the development of a future generation of nanoelectronic devices. Here we demonstrate that semiconductor nanowires can also be used as building blocks for the realization of high-sensitivity terahertz detectors based on a 1D field-effect transistor configuration. In order to take advantage of the low effective mass and high mobilities achievable in III-V compounds, we have used InAs nanowires, grown by vapor-phase epitaxy, and properly doped with selenium to control the charge density and to optimize source-drain and contact resistance. The detection mechanism exploits the nonlinearity of the transfer characteristics: the terahertz radiation field is fed at the gate-source electrodes with wide band antennas, and the rectified signal is then read at the output in the form of a DC drain voltage. Significant responsivity values (>1 V/W) at 0.3 THz have been obtained with noise equivalent powers (NEP) < 2 × 10(-9) W/(Hz)(1/2) at room temperature. The large existing margins for technology improvements, the scalability to higher frequencies, and the possibility of realizing multipixel arrays, make these devices highly competitive as a future solution for terahertz detection.     

Experimental study on the subthreshold swing of silicon nanowire transistors

SOI based wrap-gate silicon nanowire FETs are fabricated through electron beam lithography and wet etching. Dry thermal oxidation is used to further reduce the patterned fins cross section and transfer them into nanowires. Silicon nanowire FETs with different nanowire widths varying from 60 nm to 200 nm are fabricated and the number of the nanowires contained in a channel is also varied. The on-current (I(ON)) and off-current (I(OFF)) of the fabricated silicon nanowire FET are 0.59 microA and 0.19 nA respectively. The subthreshold swing (SS) and the drain induced barrier lowering are 580 mV/dec and 149 mV/V respectively due to the 30 nm thick gate oxide and 10(15) cm(-3) lightly doped silicon nanowire channel. The nanowire width dependence of SS is shown and attributed to the fact that the side-gate parts of a wrap gate play a more effectual role as the nanowires in a channel get narrower. It seems the nanowire number in a channel has no effect on SS because the side-gate parts fill in the space between two adjacent nanowires.     

Polarity control of carrier injection for nanowire feedback field-effect transistors

Nano Research - We present polarity control of the carrier injection for a feedback field-effect transistor (FBFET) with a selectively thinned p+-i-n+ Si nanowire (SiNW) channel and two separate...     

Fabrication and device characterization of omega-shaped-gate ZnO nanowire field-effect transistors

Omega-shaped-gate (OSG) nanowire-based field effect transistors (FETs) have attracted a great deal of attention recently, because theoretical simulations predicted that they should have a higher device performance than nanowire-based FETs with other gate geometries. OSG FETs with channels composed of ZnO nanowires were successfully fabricated in this study using photolithographic processes. In the OSG FETs fabricated on oxidized Si substrates, the channels composed of ZnO nanowires with diameters of about 110 nm are coated with Al(2)O(3) using atomic layer deposition, which surrounds the channels and acts as a gate dielectric. About 80% of the surfaces of the nanowires coated with Al(2)O(3) are covered with the gate metal to form OSG FETs. A representative OSG FET fabricated in this study exhibits a mobility of 30.2 cm(2)/ (V s), a peak transconductance of 0.4 muS (V(g) = -2.2 V), and an I(on)/I(off) ratio of 10(7). To the best of our knowledge, the value of the I(on)/I(off) ratio obtained from this OSG FET is higher than that of any of the previously reported nanowire-based FETs. Its mobility, peak transconductance, and I(on)/I(off) ratio are remarkably enhanced by 3.5, 32, and 10(6) times, respectively, compared with a back-gate FET with the same ZnO nanowire channel as utilized in the OSG FET.     

Field dependent transport properties in InAs nanowire field effect transistors

We present detailed studies of the field dependent transport properties of InAs nanowire field-effect transistors. Transconductance dependence on both vertical and lateral fields is discussed. Velocity-field plots are constructed from a large set of output and transfer curves that show negative differential conductance behavior and marked mobility degradation at high injection fields. Two dimensional electrothermal simulations at current densities similar to those measured in the InAs NWFET devices indicate that a significant temperature rise occurs in the channel due to enhanced phonon scattering that leads to the observed mobility degradation. Scanning transmission electron microscopy measurements on devices operated at high current densities reveal arsenic vaporization and crystal deformation in the subject nanowires.     

Gate coupling and charge distribution in nanowire field effect transistors

We have modeled the field and space charge distributions in back-gate and top-gate nanowire field effect transistors by solving the three-dimensional Poisson's equation numerically. It is found that the geometry of the gate oxide, the semiconductivity of the nanowire, and the finite length of the device profoundly affect both the total amount and the spatial distribution of induced charges in the nanowire, in stark contrast to the commonly accepted picture where metallic dielectric properties and infinite length are assumed for the nanowire and the specific geometry of the gate oxide is neglected. We provide a comprehensive set of numerical correction factors to the analytical capacitance formulas, as well as to numerical calculations that neglect the semiconductivity and finite length of the nanowire, that are frequently used for quantifying carrier transport in nanowire field effect transistors.     

Degradation pattern of SnO(2) nanowire field effect transistors

The degradation pattern of SnO(2) nanowire field effect transistors (FETs) was investigated by using an individual SnO(2) nanowire that was passivated in sections by either a PMMA (polymethylmethacrylate) or an Al(2)O(3) layer. The PMMA passivated section showed the best mobility performance with a significant positive shift in the threshold voltage. The distinctive two-dimensional R(s)-μ diagram based on a serial resistor connected FET model suggested that this would be a useful tool for evaluating the efficiency for post-treatments that would improve the device performance of a single nanowire transistor.     

Tunable electronic transport characteristics of surface-architecture-controlled ZnO nanowire field effect transistors

Surface-architecture-controlled ZnO nanowires were grown using a vapor transport method on various ZnO buffer film coated c-plane sapphire substrates with or without Au catalysts. The ZnO nanowires that were grown showed two different types of geometric properties: corrugated ZnO nanowires having a relatively smaller diameter and a strong deep-level emission photoluminescence (PL) peak and smooth ZnO nanowires having a relatively larger diameter and a weak deep-level emission PL peak. The surface morphology and size-dependent tunable electronic transport properties of the ZnO nanowires were characterized using a nanowire field effect transistor (FET) device structure. The FETs made from smooth ZnO nanowires with a larger diameter exhibited negative threshold voltages, indicating n-channel depletion-mode behavior, whereas those made from corrugated ZnO nanowires with a smaller diameter had positive threshold voltages, indicating n-channel enhancement-mode behavior.     

Fabrication of fully transparent nanowire transistors for transparent and flexible electronics

The development of optically transparent and mechanically flexible electronic circuitry is an essential step in the effort to develop next-generation display technologies, including 'see-through' and conformable products. Nanowire transistors (NWTs) are of particular interest for future display devices because of their high carrier mobilities compared with bulk or thin-film transistors made from the same materials, the prospect of processing at low temperatures compatible with plastic substrates, as well as their optical transparency and inherent mechanical flexibility. Here we report fully transparent In(2)O(3) and ZnO NWTs fabricated on both glass and flexible plastic substrates, exhibiting high-performance n-type transistor characteristics with approximately 82% optical transparency. These NWTs should be attractive as pixel-switching and driving transistors in active-matrix organic light-emitting diode (AMOLED) displays. The transparency of the entire pixel area should significantly enhance aperture ratio efficiency in active-matrix arrays and thus substantially decrease power consumption.     

Effects of device and peripheral parameters on transconductance of silicon nanowire transistors

This paper presents a general analysis over the transconductance function in silicon nanowire transistors (SNWTs). The transconductance function in SNWTs has been well-discussed and the relation between this function and the physical and peripheral parameters of the SNWT has been precisely investigated. The transconductance expression has been derived as a function of device parameters (e.g., oxide capacitor, electron effective-mass) and applied voltage biases, which helps to understand the essential physics of one-dimensional (1D) nanowire FETs and to interpret numerical simulation results. These simulations demonstrate the transconductance formulation as a function of environmental temperature, voltage biases and oxide layer thickness.     

Improved performance of ZnO nanowire field-effect transistors via focused ion beam treatment

A seven orders of magnitude increase in the current on/off ratio of ZnO nanowire field-effect transistors (FETs) after Ga( + ) irradiation was observed. Transmission electron microscopy characterization revealed that the surface crystal quality of the ZnO nanowire was improved via the Ga( + ) treatment. The Ga( + ) irradiation efficiently reduces chemisorption effects and decreases oxygen vacancies in the surface layer. The enhanced performance of the nanowire FET was attributed to the decrease of surface trapped electrons and the decrease in carrier concentration.