Effects of NH3 plasma passivation on N-channelpolycrystalline silicon thin-film transistors

The NH₃-plasma passivation has been performed on polycrystalline silicon (poly-Si) thin-film transistors (TFT's), It is found that the TFT's after the NH₃-plasma passivation achieve better device performance, including the off-current below 0.1 pA/μm and the on/off current ratio higher than 10⁸, and also better hot-carrier reliability than the H₂-plasma devices. Based on optical emission spectroscopy (OES) and secondary ion mass spectroscopy (SIMS) analysis, these improvements were attributed to not only the hydrogen passivation of the defect states, but also the nitrogen pile-up at SiO₂/poly-Si interface and the strong Si-N bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films. Furthermore, the gate-oxide leakage current significantly decreases and the oxide breakdown voltage slightly increases after applying NH₃-plasma treatment. This novel process is of potential use for the fabrication of TFT/LCD's and TFT/SRAM's     

The effects of H2-O2-plasma treatment on thecharacteristics of polysilicon thin-film transistors

The effects of H₂-plasma followed by O₂-plasma treatment on n-channel polysilicon thin-film transistors (TFTs) were investigated. It was found that the H₂-O₂-plasma treatment is more effective in passivating the trap states of polysilicon films than the H₂-plasma or O₂-plasma treatment only. Hence, it is more effective in improving the device performance with regard to subthreshold swing, carrier mobility, and the current ON/OFF ratio. It is also found that thermal annealing of plasma-treated devices increases the deep states but has no effect on the tail states of the devices     

The effects of NH3 plasma passivation on polysiliconthin-film transistors

The NH₃ plasma passivation has been performed for the first time on the polycrystalline silicon (poly-Si) thin-film transistors (TFT's). It is found that the TFT's after the NH₃ plasma passivation achieve better device performances, including the off-current below 0.1 pA/μm and the on/off current ratio higher than 10⁸, and also better hot-carrier reliability as well as thermal stability than the H₂-plasma devices. These improvements were attributed to not only the hydrogen passivation of the grain-boundary dangling bonds, but also the nitrogen pile-up at SiO₂/poly-Si interface and the strong Si-N bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films     

Characteristics of top-gate thin-film transistors fabricated onnitrogen-implanted polysilicon films

The electrical characteristics of top-gate thin-film transistors (TFT's) fabricated on the nitrogen-implanted polysilicon of the doses ranging from 2×10¹²-2×10¹⁴ ions/cm² were investigated in this work. The experimental results showed that nitrogen implanted into polysilicon followed by an 850°C 1 h annealing step had some passivation effect and this effect was much enhanced by a following H₂-plasma treatment. The threshold voltages, subthreshold swings, ON-OFF current ratios, and field effect mobilities of both n-channel and p-channel TFT's were all improved. Moreover, the hot-carrier reliability was also improved. A donor effect of the nitrogen in polysilicon was also found which affected the overall passivation effect on the p-channel TFT's     

Enhanced H2-plasma effects on polysilicon thin-filmtransistors with thin ONO gate-dielectrics

This letter reports that passivation effects of the H₂-plasma on the polysilicon thin-film transistors (TFT's) were greatly enhanced if the TFT's have a thin Si₃N₄ film on their gate-dielectrics. Compared to the conventional devices with only the SiO₂ gate dielectric, the TFT's with Si ₃N₄ have much more improvement on their subthreshold swing and field-effect mobility after H₂-plasma treatment     

The combined effects of low pressure NH3-annealing and H2 plasma hydrogenation on polysilicon thin-film transistors

The low pressure NH₃-annealing and the H₂ plasma hydrogenation were jointly used to improve the characteristics of polysilicon thin-film transistors (TFT's). It was found that the TFT's after applying the above treatments achieved better subthreshold swings, threshold voltages, field effect mobilities, off currents, and reliability. It is believed that the improvement was due to the gate oxynitride formation and the H₂-plasma had a better passivation effect on the oxynitride     

Effects of hydrogenation on the performance and hot-carrierendurance of polysilicon thin-film transistors

Statistical analysis was performed to investigate the performance and reliability of hydrogenated polysilicon thin-film transistors (TFTs) in relation to the hydrogenation process. The hydrogenation was performed in pure H₂ plasma and in plasma of 4% H₂ diluted in Ar or He gas. TFTs hydrogenated in H₂/Ar or H₂/He plasma have lower on-voltage and better uniformity compared to the nonhydrogenated devices due to passivation of grain boundary dangling bonds. Hot-carrier experiments demonstrate that electron trapping is the dominant mechanism at the early stages of the degradation process and generation of interface and grain boundary traps as the stress proceeds further. The overall results indicate that devices hydrogenated in H₂/He plasma are the most reliable in terms of uniformity and hot-carrier stress     

Characterizing Fluorine-Ion Implant Effects on Poly-Si Thin-Film Transistors With ${hbox{Pr}}_{2}{hbox{O}}_{3}$ Gate Dielectric

The fluorine ion implantation applied to the polycrystalline silicon thin-film transistors (poly-Si TFTs) with high-k Pr₂O₃ as gate dielectric is investigated for the first time. Using the Pr₂O₃ gate dielectric can obtain a high gate capacitance density and thin equivalent-oxide thickness, exhibiting a greatly enhancement in the driving capability of TFT device. Introducing fluorine ions into the poly-Si film by fluorine ion implantation technique can effectively passivate the trap states in the poly-Si film and at the Pr₂O₃/poly-Si interface to improve the device electrical properties. The Pr₂O₃ TFTs fabricated on fluorine-implanted poly-Si film exhibit significantly improved electrical performances, including lower threshold voltage, steeper subthreshold swing, higher field-effect mobility, lower off-state leakage current, and higher on/off current ratio, as compared with the control poly-Si Pr₂O₃ TFTs. Also, the incorporation of fluorine ions also improves the reliability of poly-Si Pr₂O₃ TFTs against hot-carrier stressing, which is attributed to the formation of stronger Si-F bonds. Furthermore, superior threshold-voltage rolloff characteristic is also demonstrated in the fluorine-implanted poly-Si Pr₂O₃ TFTs. Therefore, the proposed scheme is a promising technology for high-performance and high-reliability solid-phase crystallized poly-Si TFT.     

The benefits of fluorine in pnp polysilicon emitter bipolartransistors

BF₂ implantation into polysilicon and its subsequent rapid thermal diffusion into single crystal silicon is commonly used for the fabrication of pnp polysilicon emitter bipolar transistors. In this paper the effect of the fluorine, which is introduced into the polysilicon during the BF₂ implant, is investigated. Pnp polysilicon emitter bipolar transistors are fabricated in which the boron and fluorine are implanted separately, with the fluorine only going into one half of each wafer. Electrical results show that fluorine has two interrelated effects. In devices given a low thermal budget emitter drive-in, a drop in base current by a factor of approximately 3.2 is observed when the fluorine is present, together with an improvement in the ideality of the base characteristics. This is explained by the passivation of trapping states at the polysilicon/silicon interface by the fluorine. In contrast, in devices-given a higher thermal budget emitter drive-in, an increase in base current by a factor of approximately 2.5 is observed, when fluorine is present. This is explained by the action of the fluorine in accelerating the breakup of the interfacial layer. A model is proposed to explain this behavior     

Poly-Si TFT fabricated by laser-induced in-situ fluorinepassivation and laser doping

A new poly-Si TFT has been fabricated by employing laser-induced in-situ fluorine passivation and a laser-doping method. With only one excimer laser annealing, we have successfully fabricated the device using one step to crystallize, passivate and dope simultaneously. Although no additional plasma post-passivation was performed, the on-state and the off-state leakage properties of TFTs with fluorine passivation were improved compared with those without fluorine passivation. The device with in-situ fluorine passivation has the maximum transconductance of 13.3 μA/V for a C₂F₆ flow rate of 100 sccm, whilst that for a device without fluorine passivation is 8.4 μA/V. The device reliability under electrical stress was remarkably improved in the in-situ fluorine-passivated devices due to the fluorine passivation of trap states in the poly-Si channel and at the SiO₂/poly-Si interface     

A novel process-compatible fluorination technique with electrical characteristic improvements of poly-Si TFTs

A process-compatible fluorine passivation technique of poly-Si thin-film transistors (TFTs) was demonstrated by employing a novel CF/sub 4/ plasma treatment. Introducing fluorine atoms into poly-Si films can effectively passivate the trap states near the SiO/sub 2//poly-Si interface. With fluorine incorporation, the electrical characteristics of poly-Si TFTs can be significantly improved including a steeper subthreshold slope, smaller threshold voltage, lower leakage current, higher field-effect mobility, and better on/off current ratio. Furthermore, the CF/sub 4/ plasma treatment also improves the reliability of poly-Si TFTs with respect to hot-carrier stress, which is due to the formation of strong Si-F bonds.     

The effects of fluorine on parametrics and reliability in a0.18-μm 3.5/6.8 nm dual gate oxide CMOS technology

Fluorine was introduced into the gate oxide by implantation at various doses into the gate polysilicon. After complete processing, the fluorine remaining in the system was characterized by secondary ion mass spectroscopy (SIMS) and then correlated to a number of important technological device parameters. The threshold voltages of thin (3.5 nm) and thick (6.8 nm) field-effect transistors (FETs) were measured, and an increase in interface trap density with increasing fluorine content was identified. An increase in oxide thickness and improvement in hot-carrier immunity were observed. Little change to oxide dielectric integrity was noted, but the negative bias threshold instability (NBTI) shift was improved with the introduction of fluorine. These data indicate that benefits may be obtained by introducing fluorine into the p-type FET (PFET), but that the increase in interface traps makes fluorine in the n-type FET (NFET) less attractive from a technological perspective. These data are in agreement with a previously proposed mechanism whereby fluorine removes hydrogen-related sites from the oxide     

A comprehensive study on p+ polysilicon-gate MOSFET'sinstability with fluorine incorporation

It is reported that fluorine can jeopardize p⁺-gate devices under moderate annealing temperatures. MOSFETs with BF₂ or boron-implanted polysilicon gates were processed identically except at gate implantation. Evidence of boron penetration through 12.5-nm oxide and a large quantity of negative charge penetration (10 ¹² cm^-2) by fluorine even at moderate annealing conditions is reported. The degree of degradation is aggravated as fluorine dose increases. A detailed examination of the I-V characteristics of PMOSFET with fluorine incorporated p⁺-gate revealed that the long gate-length device had abnormal abrupt turn-on I_d-V_g characteristics, while the submicrometer-gate-length devices appeared to be normal. The abnormal turn-on I_d-V_g characteristics associated with long-gate-length p⁺-gate devices vanished when the device was subjected to X-ray irradiation and/or to a high-voltage DC stressing at the source/drain. The C-V characteristics of MOS structures of various gate dopants, processing ambients, doping concentrations, and annealing conditions were studied. Based on all experimental results, the degradation model of p⁺-gate devices is presented. The incorporation of fluorine in the p⁺ gate enhances boron penetration through the thin gate oxide into the silicon substrate and creates negative-charge interface states. The addition of H/OH species into F-rich gate oxide will further aggravate the extent of F-enhanced boron penetration by annealing out the negative-charge interface states     

Performance and reliability improvements in poly-Si TFT's byfluorine implantation into gate poly-Si

High-performance and high-reliability TFT's have been obtained using a fluorine ion implantation technique. The fluorine implantation into the gate poly-Si of TFT caused a positive Vth shift, increased the ON current, and decreased the leakage current significantly. Our investigation indicates that the Vth shift originates from negative charges generated in the gate oxide by the fluorine implantation. The improvement of drain current is attributed to fluorine passivation of trap states in the poly-Si and to a modulation of offset potential due to the same negative charges under the offset region. Furthermore, high immunity against the -BT stress and TDDB of the gate oxide was achieved by the fluorine implantation. It is considered that the strong Si-F bonds created by the fluorine implantation raise the stress immunity     

两种注F层面的PMOSFET电离辐射响应特性

报道了栅氧化淀积多晶硅前后分别注入43keVF离子的Si栅P沟MOSFET电离辐射响应关系。结果发现,多晶硅面注F具有较强的抑制辐射感生阈电压漂移,控制氧化物电荷和界面态生长的能力。用多晶硅面注F带入栅介质较少注入缺陷和较多替代辐射敏感应力键的F离子模型对实验结果进行了讨论。     

Improved hot-carrier immunity in CMOS analog device with N2O-nitrided gate oxides

The authors report on the hot-carrier effects on analog device performance parameters in CMOS devices with N₂O-nitrided gate oxides. The hot-carrier-induced degradation has been studied in terms of drain output resistance, voltage gain, differential offset voltage, and voltage swings. Results show that, N₂O nitridation significantly improves the hot-carrier immunity in these aspects, especially for n-channel MOSFETs. Analog and digital device performance degradations have been compared     

An ITLDD CMOS process with self-aligned reverse-sequenceLDD/channel implantation

An advanced inverse-T LDD (ITLDD) CMOS process has been developed. This process features self-aligned lightly-doped-drain/channel implantation for improved hot-carrier protection. Selective polysilicon deposition is used to define the thick polysilicon gate regions with a thin polysilicon gate regions overlying the lightly doped n^- and p⁺ regions. Since the thick poly gate regions are defined by nitride sidewall spacers, optical lithography can be used to define sub-half-micrometer gate length MOSFETs. The LDD implants are performed after the n⁺ and p⁺ implants are annealed, resulting in MOSFET's with improved short-channel behavior due to the smaller lateral source/drain diffusion     

Effect of F2 Postmetallization Annealing on the Electrical and Reliability Characteristics of HfSiO Gate Dielectric

The effects of fluorine (F₂) annealing on the electrical and reliability characteristics of HfSiO MOSFETs were investigated. Compared with a control sample annealed in conventional forming gas (H₂/N₂=4%/96%), additional annealing in a fluorine ambient (F₂/Ar=0.3%/99.7%) at 400 degC for 20 min improved the electrical characteristics such as lower interface trap density and higher transconductance. In addition, MOSFET samples annealed in a F₂ ambient exhibited less degradation under hot-carrier stress and positive bias temperature stress. These improvements can be explained by fluorine incorporation at the high-k/Si interface, which was confirmed by an X-ray photoelectron spectroscopy analysis     

Fluorine effects in n-p-n double-diffused polysilicon emitterbipolar transistors

We demonstrate that fluorine incorporation in the polysilicon emitter of n-p-n double-diffused bipolar transistors during BF₂ implantation at a dose of 1×10¹⁵ cm^-2 significantly alters the device electrical characteristics. In particular, tunneling emitter/base currents are observed at both forward and reverse voltages, due to excessive base dopant concentration at the junction. Fluorine-enhanced interfacial oxide break-up and epitaxial realignment of the poly-Si emitter are shown to be responsible for these results     

H2/O2 plasma on polysilicon thin-filmtransistor

It is reported for that H₂ plasma followed by O₂ plasma is more effective for passivating grain boundary states in polysilicon thin film. Polysilicon thin-film transistors (TFTs) made after H₂/O₂ plasma treatment can exhibit a turn-on threshold voltage of -0.1 V, a subthreshold swing of 0.154 V/decade, an ON/OFF current ratio I_on/I_off over 1×10⁸, and an electron mobility of 40.2 cm² /V-s