一种4-Mb高速低功耗CMOS SRAM的设计

高性能的系统芯片对数据存取速度有了更严格的要求,同时低功耗设计已成为VLSI的研究热点和挑战.本文设计了一款4-Mb(512K×8bit)的高速、低功耗静态存储器(SRAM).它采用0.25μm CMOS标准工艺和传统的六管单元.文章分析了影响存储器速度和功耗的原因,重点讨论了存储器的总体结构、灵敏放大器及位线电路.通过系统优化,达到15ns的存取时间.     

高速低功耗SRAM中灵敏放大器的设计

本文对比分析了运放型、交叉耦合型和锁存器型灵敏放大器三种不同的SRAM灵敏放大器的基本结构并通过仿真比较了它们的优缺点,在此基础上设计了读出放大时间在最坏情况下需0.5 ns,静态维持功耗约为0.1 mW的SRAM灵敏放大器.     

一种阵列布局优化的256 kb SRAM

介绍了一种阵列布局优化的256 kb(8 k×32位)低功耗SRAM。通过采用分级位线和局部灵敏放大器结构,减少位线上的负载电容;通过电压产生电路,获得写操作所需的参考电压,降低写操作时的位线电压摆动幅度,有效地减少了SRAM读写操作时的动态功耗。与传统结构的SRAM相比,该256 kb SRAM的写功耗可减少37.70 mW。     

一种低压低功耗Flash BiCMOS SRAM的设计

设计了一种静态随机读写存储器(SRAM)的BiCMOS存储单元及其外围电路。HSpice仿真结果表明，所设计的SRAM电路的电源电压可低于3V以下，它既保留了CMOS SRAM低功耗、高集成度的特征，又获得了双极型电路快速、大电流驱动能力的长处，因而特别适用于高速缓冲静态存储器和便携式数字电子设备的存储系统中。     

一款SRAM芯片的设计与测试

基于Chartered 0.35μm EEPROM CMOS工艺,采用全定制方法设计了一款应用于低功耗和低成本电子设备的8×8 bit SRAM芯片。测试结果表明,在电源电压为3.3 V,时钟频率为20MHz的条件下,芯片功能正确、性能稳定、达到设计要求,存取时间约为6.2 ns,最大功耗约为6.12 mW。     

一款异步256kB SRAM的设计

在集成电路设计制造水平不断提高的今天,SRAM存储器不断朝着大容量、高速度、低功耗的方向发展。文章提出了一款异步256kB(256k×1)SRAM的设计,该存储器采用了六管CMOS存储单元、锁存器型灵敏放大器、ATD电路,采用0.5μm体硅CMOS工艺,数据存取时间为12ns。     

基于SRAM高速灵敏放大器的分析与设计

在SOC系统级芯片中,存储器占有很重要的地位。随着电路频率的提高,存储器的读写操作速度也要求相应的加快。SRAM中的灵敏放大器通过检测位线上的微小变化并放大到较大的信号摆幅以减少延时,降低功耗。本文提出了一种两级串联结构的SRAM高性能灵敏放大器的设计方法,降低了对信号的反应时间,提高了抗干扰能力,适应高频电路的读写操作。     

一种深亚微米SRAM6T存储单元的设计方法

文章首先分析了静态随机存储器（SRAM）6T存储单元结构的基本工作原理,总结了6T存储单元的优缺点并介绍了存储单元的重要参数静态噪声容限（SNM）。在此基础上给出了一种基于实际深亚微米CMOS工艺的存储单元的设计方法,该方法的优势在于首先考虑单个读、写操作的限制,然后将多个限制因素综合在一起考虑,并通过三维曲线图形为仿真提供指导,以提高设计效率,缩短设计周期。最后给出了存储单元的晶体管参数并采用Hspice进行验证,仿真结果表明,采用这种方法设计出来的单元是稳定可靠的。     

一种新型灵敏放大器的设计

文章分析了基本锁存器型灵敏放大器结构,总结了其优缺点,在此基础上设计出一种高速低功耗的SRAM灵敏放大器,在输入差分信号建立之后,读出放大时间在最坏情况下需0.5ns。利用两级敏感放大器的层次式结构,一方面使第一级放大的信号成为真正的数字信号,另一方面增加了电路的驱动能力。     

容量可变的嵌入式同步SRAM电路的设计与实现

提出了一种容量可变的嵌入式同步ＳＲＡＭ。通过采用存储阵列的分块,敏感放大器的分级等技术,对电路的结构进行了优化。着重讨论了存储阵列的分块原则,分析了分块的字长,字数对电路的面积,速度,功耗等因素的影响。     

高性能SRAM的低功耗设计

采用0.13 μm标准CMOS工艺,全定制设计实现了一款8 kB(8 k*8 bit)的高速低功耗静态随机存取存储器(SRAM).分析了影响存储器性能和功耗的原因,并在电路布局上做了改进,将两个3-8译码器进行拆分与重组,降低了互连线的延迟和耦合作用;同时,对灵敏放大器也做了改进.版图后仿真表明,在电源电压为1.2 V、温度为25 ℃的典型条件下,读1延时为766.37 ps,最大功耗为11.29 mW,功耗延时积PDP为8.65 pJ,实现了很好的性能.     

Design and analysis of noise margin,write ability and read stability of organic and hybrid 6-T SRAM cell

This paper analyzes SRAM cell designs based on organic and inorganic thin film transistors (TFTs). The performance in terms of static noise margin (SNM), read stability and write ability for all-p organic (Pentacene–Pentacene), organic complementary (Pentacene–C₆₀) and hybrid complementary (Pentacene–ZnO) configurations of SRAM cell is evaluated using benchmarked industry standard Atlas 2-D numerical device simulator. Moreover, the cell behaviour is analyzed at different cell and pull-up ratios. The electrical characteristics and performance parameters of individual TFT used in SRAM cell is verified with reported experimental results. Furthermore, the analytical result for SNM of all-p organic SRAM cell is validated with respect to the simulated result. Besides this, the cell and pull-up ratios of the hybrid and organic SRAM cells are optimized for achieving best performance of read and write operations and thereafter, the results are verified analytically also. The SNM of hybrid cell is almost two times higher than the all-p SRAM, whereas this improvement is just 18% in comparison to the organic memory cell. On the other hand, the organic complementary SRAM cell shows an improvement of 26% and 22% for the read stability in comparison to the all-p organic and hybrid SRAM cells, respectively. Contrastingly, this organic cell demonstrates a reduction of 16% in the SNM and an increment of 76% in write access time in comparison to the hybrid cell. To achieve an overall improved performance, the organic complementary SRAM cell is designed such that the access transistors are pentacene based p-type instead of often used n-type transistor. Favorably, this organic SRAM design shows reasonably lower write access time in comparison to the cell with n-type access OTFTs. Moreover, this cell shows adequate SNM and read stability that too at substantially lower width of p-type access OTFTs.     

An auto-calibrated,dual-mode SRAM macro using a hybrid offset-cancelled sense amplifier

A dual-mode power and performance optimized SRAM is presented. Given the fact that the power and speed associated with the cell access time are directly related to the sense amplifier offset a new optimization platform based on the hybrid offset-cancelled current sense amplifier (OCCSA) [1] is presented. It is shown that the speed and power overhead of the offset cancellation can be optimized in a multi-variable auto-calibration loop to achieve the lowest power or the highest performance mode. The flexibility of having two degrees of freedom in OCCSA offers a significant bitline delay reduction with minimum power sacrifice in the high performance mode. The proposed scheme is verified using a macro cell implemented in a 0.18 μm CMOS technology. In the Power Optimized mode, a wide range of offset is applied to a single column test structure and 25% energy consumption reduction is measured compared to the conventional case. For a 32 kb SRAM array, compared to a conventional sense amplification, a 2X reduction in energy consumption is achieved in the Energy Optimized mode. Thanks to the offset cancelling nature of the proposed scheme, a 2X improvement in cell access time is achieved in the Speed Optimized mode.     

一种高可靠电流灵敏放大器设计

提出了一种带反馈放大器的电流灵敏放大器 ,将用于放大的 NMOS管同时作为位线多路选择器( MU X) ,与一般的电流灵敏放大器相比 ,延迟时间更短 ,而且更适于低电源电压工作。同时分析了阈值电压失配对电流灵敏放大器的影响 ,结果表明 ,失配不仅可能增大灵敏放大器时延 ,甚至造成误放大 ;带反馈放大器的电流灵敏放大器能够有效地抑制阈值失配的影响 ,其性能和可靠性良好。     

基于DICE结构的抗辐射SRAM设计

空间应用的SRAM必须具备抗辐射加固能力.介绍了SRAM工作原理与双互锁存储单元(DICE)技术,给出了基于DICE结构的SRAM存储单元的电路设计、版图设计及其功能仿真.在SMIC 0.13μm工艺下,应用HSPICE进行单粒子效应模拟,与传统6T CMOS SRAM相比,基于DICE结构的SRAM在相同工艺条件下抗辐照能力有显著的提高.