A proposed planar junction structure with near-ideal breakdown characteristics

Addition of a low-concentration p-type pocket around the edge region of p⁺-n type planar junction improves the electric-field distribution to such an extent that near-ideal breakdown characteristics can be obtained. This has been observed in 2-dimensional computer simulation studies. This is based on the fact that for a specific combination of width and depth of the pocket, the region in which maximum avalanche multiplication occurs, changes from the edge to the plane. Worst-case analysis taking constant impurity profiles in all the regions and rectangular junctions has been presented to know the influence of the edge region. The present structure, if realized by the methods indicated, would result in the highest breakdown voltage of a planar junction     

A polysilicon—Silicon n-p junction

Phosphorus-doped polycrystalline silicon is grown in an epitaxial reactor by the reduction of a hydrogen-diluted silane-phosphine mixture passing over a substrate heated to 800°C. The influence of the phosphine-silane ratio on growth rate, electrical resistivity, active donor concentration, and Hall mobility is examined. It is found that phosphine inhibits growth rate at 800°C to a lesser degree than it does at lower growth temperatures. Growth rate progressively drops to 0.6 of the undoped value as the phosphine-silane ratio is increased to 10^-1. Resistivity drops from 1 to 10^-3Ω. cm as active phosphorus concentration varies between 10¹⁸and 4 × 10²⁰cm^-3, while Hall mobility rises from 4 to 30 cm²/ V.s. Diodes are formed between the grown polysilicon layers and the single-crystal p-type silicon substrates. They are found to have recombination currents critically dependent on the phosphine/ silane ratio during growth of the polysilicon. As this ratio increases above 10^-5, recombination decreases, while mobility in the polysilicon increases. These results support the "dopant segregation" theory of conduction in polysilicon. For ratios of 10^-3to 10^-2the diodes obtained showed a recombination factor approaching those of diffused diodes and are useful devices, for example, as the emitter-base junction of a shallow-base high-frequency, bipolar transistor.     

A simple edge termination for silicon carbide devices with nearlyideal breakdown voltage

In this paper, a simple edge termination is described which can achieve near ideal parallel plane breakdown for silicon carbide devices. This novel edge termination involves self aligned implantation of a neutral species on the edges of devices to form an amorphous layer. With this termination formed using argon implantation, the breakdown voltage of Schottky barrier diodes was measured to be very close to ideal plane parallel breakdown voltage     

Increased avalanche breakdown voltage and controlled surface electric fields using a junction termination extension (JTE) technique

Extremely high breakdown voltages with very low leakage current have been achieved in plane and planar p-n junctions by using an ion-implemented junction extension for precise control of the depletion region charge in the junction termination. A theory is presented which shows a greatly improved control of both the peak surface and bulk electric fields in reverse biased p-n junctions. Experimental results show breakdown voltages greater than 95 percent of the ideal breakdown voltage with lower leakage currents than corresponding unimplanted devices. As an example, diodes with a normal breakdown voltage of 1050 V and a 0.5 mA leakage current become 1400 V (1450 ideal) devices with a 5 µA leakage current. Applications of the junction termination technique is feasible in MOS technology, but is more attractive in power devices where reduced surface fields are as important as the extremely high breakdown voltages. Reduced surface fields allow more flexibility in passivation techniques, two of which we have used to date. Our results also show that the implant can be activated at a variety of temperatures with a good degree of success; process flexibility being the goal of these tests.     

A transient component in the breakdown voltage of silicon p-n junction rectifiers

A transient component in the breakdown voltage of silicon n⁺-p junctions, at the onset of breakdown in the region of intermittent microplasma conduction, has been studied. The rates of transition from initial to final values of VBhave been found to be proportional to the relative on-time of the microplasma pulses, and the magnitude of the change in VBreaches a maximum at the temperature at which the position of the equilibrium Fermi level coincides with the energy level of the trapping centers. The effect is explained on the basis of the filling of traps during microplasma conduction, thus changing the net ionized impurity concentration and hence the breakdown voltage.     

A fast method of calculating avalanche breakdown voltage of semiconductor p-n junction

A fast method of calculating the avalanche breakdown voltage of semiconductor p-n junction is described. A simple technique of calculating the integral from the stored values of the integrand is illustrated for Silicon step junctions. This results in considerable saving of computational time.     

A substrate etch geometry for near ideal breakdown voltage in p-n junction devices

A new junction-termination geometry is proposed which can be achieved by a simple etch. This etch effectively lowers peak surface fields in both plane and planar p-n junction devices without increasing peak bulk electric fields. This insures an ideal, or near-ideal, avalanche breakdown voltage. The further advantages of the proposed technique lie in a relative insensitivity to etch depth, a minimal loss in device area, and compatibility with planar technology. Theoretical and experimental results are given to illustrate the substrate-etch technique.     

Status of the GaAs metal—oxide—semiconductor technology

A review of recent and current work on GaAs insulated-gate technology is presented. First, various techniques for the formation of heteromorphic and homomorphic dielectrics are outlined and some important aspects of properties of these dielectrics are reviewed. Second, MOSFET structures, fabrication procedures, and microwave performance are described. Third, the application of GaAs MOSFET's to digital integrated circuits is summarized.     

圆柱突变结击穿电压及电场沿结边的分布

基于横向侧扩散与纵向体扩散结深构成椭圆形冶金结外形这一与工艺实际相符合的假设 ,通过圆柱对称解的归一化 ,提出了平面结击穿电场沿结边分布的解析解。理论结果阐述了不同结深及结边形状对边缘区击穿电压的影响规律 ,说明了表面击穿电压总是小于体内击穿电压的原因。     

A high-yield, 3—7-GHz, 0.5-W push-pull GaAs MMIC amplifier

A high-yield, 3-7-GHz, 0.5-W MMIC GaAs amplifier has been successfully designed and tested. The amplifier features small chip size (1.2 mm sq.), high gain (12 ± 1.5 dB), high power-added efficiency (20 percent), good RF yield (57 percent, and high tolerance to process variations. Packaged amplifiers were built with this chip for both the 2-6-GHz and the 5.9-6.4-GHz bands. Saturated output power of 25 dBm was achieved in the 2-6-GHZ band, and 27 dBm in the 5.9-6.4-GHz band. Infrared measurements show that the device has low FET channel temperatures when operated at full bias power over the full range of military ambient temperatures.     

The differential voltage pen for plasma panels—A light pen substitute

A new hand-held interactive pen for ac plasma panels is described. The pen uses multiple metal plates to detect positional information generated by the regular write/erase voltages in the panel. No optical detector is used. Closed-form field potential equations of a panel line outside the panel are derived. These equations enable the resolution of the pen to be optimized; they are also helpful in pointing out some avoidable troublesome secondary effects. It is shown that a multiple plated probe's resolution is seven times better than that of a single-plate probe. This new pen can achieve resolutions to within 1 cell on panel artworks as dense as 50 lines/cm. Worst case detect time is 100 ms for a one million cell panel. Difficulties and special panel requirement when applied to a panel display product are discussed.     

Peripheral emitter—Base junction capacitance in bipolar transistors

The emitter-base peripheral (sidewall) capacitance of double-diffused silicon bipolar transistors is computed at zero bias. Results are presented in such a way as to provide useful design data.     

COMPOSITE—A complete modeling program of silicon technology

A new two-dimensional process modeling program written in Fortran is described. For the first time, this program allows the simulation of all important processing steps occuring in typical sequences involved in the fabrication of integrated circuits such as doping, oxidation, lithography, etching, and layer deposition. The program possesses a modular structure to allow for easy changing and improvement of process models as well as of mathematical procedures. The program is menu driven to make it easy to use for non-experts and it is readily usable with different computer systems.     

Optimization of junction termination extension for ultrahigh voltage 4H-SiC planar power devices

Numerical simulations on the optimization of junction termination extension (JTE) have been performed. Various termination techniques have been applied and simulated in this paper, such as single-zone JTE (S-JTE), multi-zone JTE (M-JTE), and space-modulated JTE (SM-JTE). A completely novel and efficient method is demonstrated in this paper to determine total length of SM-JTE, and it is verified through simulation results. The simulation results show that the SM-JTE could provide a protection efficiency (defined in Section 2) of 95.2%, which is much higher than that of M-JTE (82.4%) and S-JTE (64.7%). Based on the fabricated MOSFETs, the interface charge density is extracted and the approximate range of charge density has been determined. The influences of different interface charge densities have been investigated for the three termination techniques respectively. According to the previous reports, the JTE is quite sensitive to the implanted dose, so the blocking capability of each termination structure with different implanted doses is also simulated. The results show that when interface charge is considered, the SM-JTE always shows an enormous advantage over the other two junction termination structures, however the interface charge densities varied. The space-modulated JTE is also applicable to the power planar devices such as MOSFETs and IGBTs, which would provide a very promising lower fabrication cost.     

Adjustable speed AC drives—A technology status review

The technology of solid-state adjustable speed ac drives was launched in the 1960's. Since then many innovations in devices, circuits, control theory, and signal electronics have made a considerable contribution to this technology. With the heritage of past experience, and the projection of present trends, an almost certain prediction can be made that adjustable speed ac drives will find widespread applications in industry before the end of this decade. The paper reviews the present status of ac drives technology in which the salient technical features of ac machines, converters, controls, and performances of the integrated drive systems have been discussed, and wherever possible, the appropriate trend of the technology has been indicated.     

CMOS on buried nitride—A VLSI SOI technology

A CMOS technology in silicon on insulator (SOI) for VLSI applications is presented. The insulator is a buried silicon nitride formed by nitrogen implantation and annealing. The CMOS devices are fabricated in the superficial monocrystalline silicon layer without an epitaxial process, 1-µm PMOS and 2-µm NMOS transistors have been realized, which have been used to built inverters, ring Oscillators, and other circuits. With 40-nm gate oxide the transistors withstand gate and drain voltages of 10 V. Mobilities, subthreshold behavior, and leakage currents are nearly the same as in bulk-CMOS devices. Ring-oscillator measurements yield inverter delay times of 230 ps and power delay products of 14 fJ.     

Techniques and technology for high-speed D—A conversion

A family of 8-, 10- and 12-bit monolithic digital-to-analog converters (DAC's) have been developed which represent the state of the art in high-speed data conversion. Total through-delay plus settling times have been measured at 5 ns for the 8-bit device, 12 ns for the 10-bit, and 45 ns for the 12-bit, which is still at an experimental stage. All devices are produced on a standard high-speed digital bipolar process without the need for post-process trimming.