A model-driven engineering framework for embedded systems design

This work presents a Model-Driven Engineering (MDE) framework to improve embedded system design. The framework adopts concepts from MDE for the automatic generation of a control and data flow internal representation, starting from the functional specification of an embedded application described using UML class and sequence diagrams. By means of transformations rules applied on the UML model of the embedded system, an MOF-based (Meta Object Facility is a standard representation for meta-models and models proposed by OMG) internal representation is automatically obtained, which is iteratively mapped into a hardware/software implementation by means of model transformations. This mapping is optimized by a design space exploration (DSE) method based on a categorical graph product. The model transformations have also as input a platform model, which specifies the available hardware, software and interface resources, and produce an implementation model, on which software synthesis, communication synthesis and high-level synthesis algorithms are applied to generate the final implementation. A case study is described to illustrate the application of the framework.     

Generating Synthetic Space Allocation Probability Layouts Based on Trained Conditional-GANs

In this paper, a data-driven generative method is applied to generate synthetic space allocation probability layout. This generated layout could be helpful in the early stage of an architectural design. For this task, a specific training dataset is generated which is used to train the cGAN model. The training dataset consists of 300 existing apartment layouts which are coloured in a set of low feature representation. The cGAN model is trained with this dataset and the trained model is evaluated based on the quality of its generated layouts regarding the five pre-defined topological and geometrical benchmarks.     

Automatic mapping of C to FPGAs with the DEFACTO compilation and synthesis system

The DEFACTO compilation and synthesis system is capable of automatically mapping computations expressed in high-level imperative programming languages as C to FPGA-based systems. DEFACTO combines parallelizing compiler technology with behavioral VHDI, synthesis tools to guide the application of high-level compiler transformations in the search of high-quality hardware designs. In this article we illustrate the effectiveness of this approach in automatically mapping several kernel codes to an FPGA quickly and correctly. We also present a detailed example of the comparison of the performance of an automatically generated design against a manually generated implementation of the same computation. The design-space-exploration component of DEFACTO is able to explore a large number of designs for a particular computation that would otherwise be impractical for any designers.     

软硬件协同设计中模型表示与映射

目前的软硬件协同设计方法都有其局限性,主要表现在：缺乏必要的模型映射机制、不同语言描述的软硬件设计容易造成不一致现象。经过分析和研究,该文提出了一个软硬件协同设计流程,它基于CDM模型,支持从系统需求描述出发、通过设置各描述组件的参数,自动产生CDM模型。利用SystemC的软硬件描述功能,对CDM模型进行映射和绑定操作,自动生成SystemC可执行程序,使软硬件代码无缝联接。模型经过多次细化和验证,从而提高设计质量和缩短设计周期。最后通过一个实例说明该方法的设计特点。     

Energy-driven design space exploration of tiling-based accelerators for heterogeneous multiprocessor architectures

Programming heterogeneous multiprocessor architectures combining multiple processor cores and hardware accelerators is a real challenge. Computer-aided design and development tools try to reduce the large design space by simplifying hardware-software mapping mechanisms. However, energy consumption is not well supported in most of design space exploration methodologies due to the difficulty to estimate energy consumption fast and accurately. To this aim, this paper proposes and validates an exploration method for partitioning tilling-based parallel applications on software cores and hardware accelerators under energy-efficiency constraints. The methodology is based on energy and performance measurement of a tiny subset of the design space and an analytical formulation of the performance and energy of an application kernel mapped onto a heterogeneous architecture. This closed-form expression is captured and solved using Mixed Integer Linear Programming, which allows for very fast exploration and results in the best hardware and software partitioning under energy constraint. The approach is validated on two application kernels using a Zynq-based architecture showing more than 12% acceleration speed-up and energy saving compared to standard approaches. Results also show that the most energy-efficient solution is application- and platform-dependent and moreover hardly predictable, which highlights the need for fast exploration tools as in this paper.     

A simple method to design dielectric resonator‐based filters and diplexers using implicit space mapping technique

We present the design of a six pole Chebyshev filter and a cascaded quadruple dielectric resonator (DR) filter using space mapping technique. Implicit space mapping technique is used throughout and the design emerges within few iterations in both the cases. Finite element method based HFSS is used in constructing the fine model and Agilent ADS is used in constructing the coarse model. Fine details such as tuning screws are included in the fine model. The same technique is also applied to a DR‐based diplexer and is explained. In all the cases, the results obtained with the hardware match well with the analyzed results. The same procedure can be applied in designing much more complex structures such as multiplexers. © 2013 Wiley Periodicals, Inc. Int J RF and Microwave CAE 24:204–216, 2014.     

Shape indexing using self-organizing maps

In this paper, we propose a novel approach to generate the topology-preserving mapping of structural shapes using self-organizing maps (SOMs). The structural information of the geometrical shapes is captured by relational attribute vectors. These vectors are quantised using an SOM. Using this SOM, a histogram is generated for every shape. These histograms are treated as inputs to train another SOM which yields a topology-preserving mapping of the geometric shapes. By appropriately choosing the relational vectors, it is possible to generate a mapping that is invariant to some chosen transformations, such as rotation, translation, scale, affine, or perspective transformations. Experimental results using trademark objects are presented to demonstrate the performance of the proposed methodology.     

The mapping method as a toolbox to analyze,design, and optimize micromixers

The mapping method is employed as an efficient toolbox to analyze, design, and optimize micromixers. A new and simplified formulation of this technique is introduced here and applied to three micromixers: the staggered herringbone micromixer (SHM), the barrier-embedded micromixer (BEM), and the three-dimensional serpentine channel (3D-SC). The mapping method computes a distribution matrix that maps the color concentration distribution from inlet to outlet of a micromixer to characterize mixing in a quantitative way. Once the necessary distribution matrices are obtained, computations are fast and numerous layouts of the mixer are easily evaluated, resulting in an optimal design. This approach is demonstrated using the SHM and the BEM as typical examples. Mixing analysis in the 3D-SC illustrates that also complex flows, for example in the presence of back-flows, can be efficiently dealt with by using the new formulation of the mapping method.     

面向配置设计的产品功构建模方法

针对产品配置设计过程中存在的客户和设计者之间交互语义一致性以及功能域与结构域之间映射等问题,鉴于事物特性表技术,通过规定产品信息的数据格式使产品数据能在不同系统之间进行交流,提出了基于事物特性表的产品需求信息元方法,构造了面向配置设计的功构模型;着重探讨了模型的优化算法及基于功构模型的产品配置设计流程;最后给出了面向配置设计的产品功构建模应用实例．     

HPP:一种支持高性能和效用计算的体系结构

为了同时做到应对千万亿次高性能计算的技术挑战和满足数据中心(data center)未来的主要应用模式效用计算(utility computing)的需求,提出了一种称为HPP(Hyper Parallel Processing)的高性能计算机体系结构.HPP的主要特征是全局地址空间(global address space)和单一操作系统映像的超节点(hyper node).HPP结合了MPP的可扩展性,DSM的高效通信和机群的普及化的优点,为高性能计算和效用计算都提供了许多创新研究的机会.基于HPP体系结构,实现了一个曙光5000高性能计算机的原型系统,初步验证了它的可行性.     

Tied factor analysis for face recognition across large pose differences

Face recognition algorithms perform very unreliably when the pose of the probe face is different from the gallery face: typical feature vectors vary more with pose than with identity. We propose a generative model that creates a one-to-many mapping from an idealized "identity" space to the observed data space. In identity space, the representation for each individual does not vary with pose. We model the measured feature vector as being generated by a pose-contingent linear transformation of the identity variable in the presence of Gaussian noise. We term this model "tied" factor analysis. The choice of linear transformation (factors) depends on the pose, but the loadings are constant (tied) for a given individual. We use the EM algorithm to estimate the linear transformations and the noise parameters from training data. We propose a probabilistic distance metric which allows a full posterior over possible matches to be established. We introduce a novel feature extraction process and investigate recognition performance using the FERET, XM2VTS and PIE databases. Recognition performance compares favourably to contemporary approaches.     

The development of generic definitions of hyperslice packages in Hyper/J

In this paper we investigate the notion of reusability of aspect definitions. We discuss the development of generic aspects in Hyper/J and compare it with the AspectJ approach. In doing that, we follow the design principle of “developing with hyperslice packages” and we show that hyperspace structure, concern mapping, hyperslice definitions and merging stategies exhibit well-defined patterns. An approach to constructing and merging generic aspects with base core concerns in Hyper/J is presented.     

过程性纹理映射的FPGA动态生成

在FPGA可编程硬件平台上设计实现了基于珀林噪声函数的过程性纹理生成算法.该算法充分利用了FPGA硬件设计的优势,针对这一算法基于像素密集求解的特点,更快、更好地进行设计实现.利用该算法可以实时地生成许多不同的自然材质或现象的纹理,如木料、云石、云朵等,其纹理可以随时间动态变换,以产生真实的运动效果.文中采用了一种新的珀林（Perlin）噪声函数,以充分应用硬件电路的结构特点,耗费较少的硬件资源,达到各种运算单元（如加法和乘法）模块的组合和高度复用.     

Higher-level techniques for hardware description and synthesis

The FLaSH (Functional Languages for Synthesising Hardware) system allows a designer to map a high-level functional language, SAFL, and its more expressive extension, SAFL+, into hardware. The system has two phases: first we perform architectural exploration by applying a series of semantics-preserving transformations to SAFL specifications; then the resulting specification is compiled into hardware in a resource-aware manner – that is, we map separate functions to separate hardware functional units (functions which are called multiple times become shared functional units). This article introduces the SAFL language and shows how program transformations on it can explore area-time trade-offs. We then show how the FLaSH compiler compiles SAFL to synchronous hardware and how SAFL transformations can also express hardware/software co-design. As a case study we demonstrate how SAFL transformations allow us to refine a simple specification of a MIPS-style processor into pipelined and superscalar implementations. The superset language SAFL+ (adding process calculi features but retaining many of the design aims) is then described and given semantics both as hardware and as a programming language. Published online: 17 December 2002     

Genetic algorithms for hardware–software partitioning and optimal resource allocation

A scheme for time and power efficient embedded system design, using hardware and software components, is presented. Our objective is to reduce the execution time and the power consumed by the system, leading to the simultaneous multi-objective minimization of time and power. The goal of suitably partitioning the system into hardware and software components is achieved using Genetic Algorithms (GA). Multiple tests were conducted to confirm the consistency of the results obtained and the versatile nature of the objective functions. An enhanced resource constrained scheduling algorithm is used to determine the system performance. To emulate the characteristics of practical systems, the influence of inter-processor communication is examined. The suitability of introducing a reconfigurable hardware resource over pre-configured hardware is explored for the same objectives. The distinct difference in the task to resource mapping with the variation in design objective is studied. Further, the procedure to allocate optimal number of resources based on the design objective is proposed. The implementation is constrained for power and time individually, with GA being used to arrive at the resource count to suit the objective. The results obtained are compared by varying the time and power constraints. The test environment is developed using randomly generated task graphs. Exhaustive sets of tests are performed on the set design objectives to validate the proposed solution.     

Configuring of Algorithms in Mapping into Hardware

The growing need for high-performance embedded processors on the reconfigurable computing platform increases the pressure for developing design methods and tools. One important issue in mapping algorithms into hardware is the configuring of algorithms to fit the particular hardware structure, the available area and configuration, together with time parameters. This paper presents an overview of a new synthesis method—the Iso-plane method—on the polytope model of algorithm to increase the parallelism and facilitate the configurability in regular array design via algebraic transformations as associativity and commutativity. The paper presents a variety of new regular and scalable array solutions with improved performance and better layout including motherboards with daughter boards.     

A linear algebra framework for automatic determination of optimaldata layouts

This paper presents a data layout optimization technique for sequential and parallel programs based on the theory of hyperplanes from linear algebra. Given a program, our framework automatically determines suitable memory layouts that can be expressed by hyperplanes for each array that is referenced. We discuss the cases where data transformations are preferable to loop transformations and show that under certain conditions a loop nest can be optimized for perfect spatial locality by using data transformations. We argue that data transformations can also optimize spatial locality for some arrays without distorting temporal/spatial locality exhibited by others. We divide the problem of optimizing data layout into two independent subproblems: 1) determining optimal static data layouts, and 2) determining data transformation matrices to implement the optimal layouts. By postponing the determination of the transformation matrix to the last stage, our method can be adapted to compilers with different default layouts. We then present an algorithm that considers optimizing parallelism and spatial locality simultaneously. Our results on eight programs on two distributed shared-memory multiprocessors, the Convex Exemplar SPP-2000 and the SGI Origin 2000, show that the layout optimizations are effective in optimizing spatial locality and parallelism     

Using affine closure to find legal reordering transformations

We present a unified framework for applying iteration reordering transformations. This framework is able to represent traditional transformations such as loop interchange, loop skewing and loop distribution as well as compositions of these transformations. Using a unified framework rather than a sequence of ad-hoc transformations makes it easier to analyze and predict the effects of these transformations. Our framework is based on the idea that all reordering transformations can be represented as a mapping from the original iteration space to a new iteration space. An optimizing compiler would use our framework by finding a mapping that both corresponds to a legal transformation and produces efficient code. We present the mapping selection problem as a search problem by decomposing it into a sequence of smaller choices. We then characterize the set of all legal mappings by defining a search tree. As part of this process we use a new operation called affine closure.     

An 8-bit systolic AES architecture for moderate data rate applications

The complexity involved in mapping an algorithm to hardware is a function of the controller logic and data path. Minimizing data path size can lead to significant savings in hardware area and power dissipation. This paper presents an implementation of a novel architectural transformation technique for mapping a word bit wide algorithm to byte vector serial architecture. The technique divides the input word to several bytes and then traces each byte for extracting architectural transformation. The technique is applied on Advanced Encryption Standard (AES) algorithm which is non-linear in nature. Using this technique, the 32-bit AES algorithm is transformed into a byte-systolic architecture. The novelty of the technique is more pronounced around the mix column design which is the most complex part of the AES algorithm. The complex matrix multiplication component and standard transformations of the 32-bit AES algorithm are transformed to support 8-bit operations. The resulted AES architectures reuse same logic resources for key expansion and encryption/decryption. The proposed design offers moderate data rates in the range of 41 Mbps for encryption and 37 Mbps for decryption while utilizing 236 and 280 slices, respectively, on Xilinx Virtex II xc2v1000-6 FPGA. Comparison results show significant gain in throughput when compared with other 8-bit designs. This makes it a viable data/communication security solution for a variety of embedded and consumer electronics.