Electromigration characteristics of tungsten plug vias under pulseand bidirectional current stressing

Using Kelvin test structures, electromigration performances of selective CVD tungsten filled vias under DC, pulsed DC, and AC current signals have been studied. The metallization consists of Al-Cu/TiW multilevel metals. The via electromigration lifetime exhibits a current polarity dependence. The via AC lifetimes are found to be much longer (more than 1000×) than DC lifetimes under the same peak stressing current density. The via lifetimes under pulsed DC stress of 50% duty factor are twice the DC lifetimes at low-frequency regions (<200 Hz) and 4-5 times the DC lifetimes at high-frequency regions (>10 kHz). The results are in agreement with the vacancy relation model     

Electromigration reliability of tungsten and aluminum vias andimprovements under AC current stress

The reliability with respect to electromigration failure of tungsten and aluminum vias under DC, pulse-DC, and AC stressing has been studied using Kelvin test structures. The results indicate that although W-plug vias can eliminate the step coverage problem, this metallization system is not ideal because the intermetallic contact represents an undesirable flux divergence location for electromigration. Al vias are more reliable than W-plug vias with respect to electromigration failure. The unidirectional 50% duty factor pulse-DC lifetime is found to be twice the DC lifetime in the low-frequency region (<200 Hz) and four times the DC lifetime in the normal frequency region (> 10 kHz). The via lifetimes under bidirectional stressing current are found to be orders of magnitude longer than DC lifetimes under the same stressing current density for both W and Al vias. All the observations are in agreement with a vacancy relaxation model     

Unframed contacts using refractory metals

Unframed contacts are extremely useful for high density integrated circuits because they decrease the metal interconnection line pitch in contrast to framed vias where the metal frames around the vias or contact openings require a minimum design rule spacing between the frame edges and adjacent lines. A method is described for making unframed or nonoverlapping metal contacts to silicon junction regions using selective CVD tungsten films for contacts and molybdenum for interconnections.     

Laser-assisted via hole metallization in PCB materials

A novel via hole metallization method is presented, where the vias are drilled in polyimide/copper (PI/Cu) flexible printed circuit boards (PCBs) using KrF excimer pulses, and then pre-metallized using a scanned Ar⁺ laser. In the premetallization step, a thin (20–50 nm) and narrow (2–10 μm) palladium layer is deposited on the polyimide-covered side of the PCB and on the wall of the vias using the laser-induced chemical liquid-phase deposition method. After the pretreatment, the Pd covered holes are immersed into a Cu electroless plating bath. Plated copper vertical and horizontal interconnects are analyzed by optical microscopy, focused ion beam, profilometry and resistivity measurements. The results show that the copper deposits formed on the pre-metallized surface of PCBs have high chemical purity, excellent adhesion and almost bulk conductivity, but, so far, due to unclear reasons, high through hole resistance.     

Mo/Al metallization for VLSI applications

We have investigated the ohmic contact properties of a metallization system made of a thin ( < 50-nm) film of aluminum covered by a thick (≈ 0.4-µm) layer of molybdenum. The thin aluminum film provides good contact characteristics to shallow n⁺-p and p⁺-n junctions in silicon, and good adherence. The thick molybdenum overlayer, which is the primary current carrier, contributes good thermal and metallurgical reliability features. Results of the present study show that the combined Mo/Al metallization system is suitable for use in very large scale integrated circuits, as the first-level metallization in a multilevel interconnect scheme.     

Finite element investigations of mechanical stress in metallization structures

For different double layer metallization structures the thermal-electrical-mechanical stress due to the mismatch of thermal expansion coefficients and elastic moduli was calculated by finite element analysis. A quantitative comparison between a conventional structure with small aluminum step coverage as well as an aluminum plug, a tungsten filled via structure and a structure with a barrier layer was done. The influence of applied current density, metallization length and passivation thickness and material was investigated for the tungsten filled via structure.     

Origin and prevention of high contact resistance in multilevel metal-polyimide structures

When polyimide is used as the insulating dielectric in multilevel-metal structures, a high contact resistance can result within the interconnecting vias. This paper examines the particular case of oxygen plasma patterning of the polyimide using a photoresist mask. Auger analysis in combination with compositional depth profiling was employed on a series of samples to measure surface composition of etched vias in polyimide. Results show two effects which, together, can account for high contact resistance: first, there is a thicker than normal aluminum oxide layer on the first level metal surface (due to exposure to the oxygen plasma); second, there is a thin, etch-resistant carbonaceous film (due to redeposition of organic material during plasma etching) that prevents oxide thinning through chemical means. It was found that by lowering the plasma pressure to 50 mTorr near the end of the etch, the organic film can be removed. In the absence of the carbonaceous layer, the oxide can then be chemically thinned to produce clean aluminum surfaces within the vias.     

Plating of small blind vias [multilayer PCBs]

Metallization of laminates with blind vias on the dielectric side was performed by electroless copper plating with subsequent copper electroplating. The vertical cross section of blind vias with diameters between 125 and 75 μm were analyzed by reflective microscopy. Results indicate that ultrasonic vibration during the pretreatment processes of metallization enables complete electroless copper deposition of the inside wall of the small blind vias without any voids. Furthermore, the introduction of periodic pulse reversal current for the subsequent copper electroplating process resulted in high throwing power deposition. By employing these two protocols, it has been demonstrated that high throwing power deposition can be readily achieved for blind vias as small as 75 μm in diameter with an aspect ratio of 3:1     

A MBE-grown high-efficiency GaAs solar cell with a directlydeposited aluminum front contact

A novel metallization scheme for GaAs p-n solar cells grown by molecular beam epitaxy (MBE) is described. A p⁺-GaAs contact layer was grown on top of the AlGaAs window layer, followed by a pure aluminum layer. This MBE-grown aluminum layer serves both as metallization and as self-aligned mask for selective etching down to the AlGaAs window. The solar cell showed an efficiency of about 20%; the I-V characteristics revealed that negligible series resistance was present in the structure. To test the novel p-contact a second sample was grown. Using a transmission-line model (TLM) structure, a metal-semiconductor contact resistance of 1.5×10^-2 Ω-cm² was found     

Reliability evaluation of tungsten donut-via as an element of the highly robust metallization

The typical via layout in CMOS technology with AlCu-metallizations and tungsten via is cylindrical. Common vias have a size as small as possible in the related process. More challenging application, temperature and mission profiles require higher robustness of a metallization [1,2]. Via arrays of small common vias are in use to the transfer of higher currents [3]. But the typical via array layout is not the best layout for applications which are faced to high mechanical stress because via arrays metal layer connections make these parts in the stack inflexible.The developed so called highly robust metallization is optimized for applications with extended operating conditions regarding higher currents and temperatures as well as mechanical stress [4]. Donut-Vias are elements of the highly robust metallization for the interconnection of highly robust metal lines. The paper shows the layout of a Donut-Via and explains the benefits and limits of the new layout by simulation and test results.     

Planarization of gold and aluminum thin films using a pulsed laser

Micrometer-thick gold and aluminum films have been planarized by momentarily melting them with optical pulses from a dye laser. Submicrosecond pulses were used in order to minimize the temperature rise in the substrate, reduce the energy required for melting, and prevent undesirable metallurgical reactions. Planarization of two-level gold metallization structures insulated by SiO2(including interlevel vias) has been achieved. Aluminum metallization on integrated circuits (IC's) has also been planarized. The use of a thin (<200 Å) silicon overcoating greatly aids the aluminum planarization process by passivating the aluminum and increasing its initial optical absorbance.     

Electrical characterization and reliability of submicron SOI CMOS technology in the extended temperature range (to 300 °C)

I-V characteristics and reliability parameters for the set of hardened SOI MOSFET's with special layouts and tungsten metallization to provide additional thermal tolerance for high-temperature SOI CMOS IC's are investigated in the temperature range up to 300 °C. The reliability aspects under test for MOSFET's are threshold voltage shift, subthreshold slope and mobility degradation, gate leakage current rise; for tungsten metallization (contacts, conductor lines and vias) I-T and R-T characteristics, failure time. The SOI MOSFET standard compact SPICE model BSIMSOI with traditional temperature limit of 150 °C is modified to be used for CMOS IC simulation in the extended temperature range up to 300 °C. The results indicate that the 0.5–0.18 μm SOI MOSFET's with tungsten metallization have stable electrical behavior that makes them possible to be used during implementation of HT CMOS IC's (to 300 °C).     

Rapid low-resistance interconnects by selective tungsten deposition on laser-direct-written polysilicon

Polysilicon interconnections were locally deposited on oxide-covered silicon wafers by pyrolysis of silane using a scanned Ar+-laser spot. The 2-µm-wide interconnects, written at scan speeds of 2.5 mm/s, have a 500-µΩ.cm resistivity and exhibit low contact resistance to underlying Al and Al/Si structures. These films were subsequently reacted with WF6vapor to form a tungsten-silicon composite interconnect by the silicon reduction of WF6. Electrical tests show that the conductivity of 0.4-µm-thick conductors is enhanced up to 20-fold, by formation of a surface metallic layer having conductivity characteristic of pure thin-film tungsten. Auger and Rutherford backscattering spectra (RBS) confirm the purity and selectivity of the surface tungsten layer formed at temperatures compatible with preexisting aluminum metallization. The tungsten-polysilicon composite interconnects have applications as rapidly written discretionary metallization for prototyping and in situ analysis of integrated circuits.     

A study of the effect of post-metal etch wet cleaning processes and silicon oxynitride film on charge induced corrosion of tungsten vias

We report the experimental study of prevention of charge induced corrosion of tungsten vias after metal etch using wet chemical solutions and silicon oxynitride (SiON) shielding film. It was found that one of the solutions could effectively prevent corrosion of tungsten vias and leave essentially no polymer residue on metal lines. The performance of other solutions is poor due to the formation of polymer residues or sidewall erosion on metal lines. We have demonstrated that the combination of wet chemical treatment with SiON as the dielectric charge shielding film was as effective as other standard methods for preventing corrosion of tungsten vias. It was also found that SiON has strong impacts on chamber wall conditions and metal line profile.     

Selective CVD tungsten via plugs for multilevel metallization

Use of selective-metal CVD tungsten is shown to be a viable method of filling small via holes in multilevel metal integrated circuits. The method specifically described utilizes Mo/TiW as the first-level interconnection/contacting metallization (M1), a planarized interlevel dielectric, straight via holes filled with tungsten, and AL second-level metal (M2). This methodology solves the problems of variable via depth encountered in integrated circuits especially when interlevel dielectrics are planarized and whenever design rules are utilized which allow for stacked and unstacked via connections to underlying features at widely varying topological height. The method also provides a means of greatly reducing metal interconnection pitch.     

A comparison of two micromachined inductors (bar- and meander-type)for fully integrated boost DC/DC power converters

Two micromachined integrated inductors (bar- and meander-type) are realized on a silicon wafer by using modified, IC-compatible, multilevel metallization techniques. Efforts are made to minimize both the coil resistance and the magnetic reluctance by using thick electroplated conductors, cores, and vias. In the bar-type inductor, a 25-μm thick nickel-iron permalloy magnetic core bar is wrapped with 30-μm thick multilevel copper conductor lines. For an inductor size of 4 mm×1.0 mm×110 μm thickness having 33 turns of multilevel coils, the achieved specific inductance is approximately 30 nH/mm² at 1 MHz. In the meander-type inductor, the roles of conductor wire and magnetic core are switched, i.e., a magnetic core is wrapped around a conductor wire. This inductor size is 4 mm×1.0 mm×130 μm and consists of 30 turns of a 35-μm thick nickel-iron permalloy magnetic core around a 10-μm thick sputtered aluminum conductor lines. A specific inductance of 35 nH/mm² is achieved at a frequency of 1 MHz. Using these two inductors, switched DC/DC boost converters are demonstrated in a hybrid fashion. The obtained maximum output voltage is approximately double an input voltage of 3 V at switching frequencies of 300 kHz and a duty cycle of 50% for both inductors, demonstrating the usefulness of these integrated planar inductors     

Reliability challenges for copper interconnects

In the past few years, copper has been widely used as interconnect metallization for advanced ultralarge-scale integration (ULSI) circuits. Due to the unique chemical properties of copper compared to its predecessor, aluminum, different integration processes must be used for circuit fabrication, that is, the damascene versus reactive ion etch (RIE) process. This difference in integration processes introduces a series of reliability concerns for copper interconnects. After a brief comparison of copper and aluminum interconnects, this article discusses the impact of the differences in the material properties and integration process on reliability. Details are provided on two advanced metallization reliability failure mechanisms: electromigration and stress migration. For copper interconnects, the interface between the cap and the copper metal serves as the fast diffusion path. To improve copper interconnect reliability, development efforts have focused on suppressing copper or copper vacancy diffusion along the interface. Two copper interfaces, the copper/cap interface and the copper/liner (or diffusion barrier) interface, are critical for copper reliability. For commonly used liners, such as Ta/TaN, the copper/liner interface is relatively easy to control compared to the copper/cap interface. For dual-damascene copper lines, a copper via is used to connect the lower level to the upper level. Unlike the robust tungsten stud used in aluminum interconnects, the copper via has been identified as a weak link in dual-damascene copper connections; the majority of early reliability failures can be attributed to the copper vias. The three most critical process factors and elements affecting copper interconnect reliability are copper vias and interfaces and the liner coverage. Using a low-k dielectric with a copper interconnect introduces several new challenges to reliability, including dielectric breakdown, temperature cycle, and stability within packages. Extensive knowledge is urgently needed to understand these issues.     

Selectively deposited nickel film for via filling

A selective deposition process is used to fill vias in VLSI multilevel interconnection. Ni film is chosen as the via-filling material because of its compatibility with the underlying Al film. The vias are filled with a thin Pd film first and a thick Ni film. The deposited Ni film is uniform and smooth in the via regions. This film is not attacked by the plasma etch used in subsequent Al patterning; therefore, the design rule of overlapping the second metal on vias can be relaxed. The specific via resistance of this process is 4×10 ^-9Ω-cm². The via resistance increases about 30% after an exposure to 450°C for 8 h     

Annealed AuGe based Ohmic contacts on InP with ion milling prior to metallization

Ohmic contacts have been fabricated onn-type InP with an alloyed AuGe based metallurgy that involved ion milling prior to metallization. Minimum values for contact resistance and specific resistance of 0.015Ω-mm and 3.2 × 10⁻⁸ Ω-cm², respectively, were found with an annealing temperature in the range, 440–480° C. Addition of Ni to the contact metallurgy improves the wetting characteristics of the AuGe and lowers the contact resistance. It is proposed that ion milling prior to metallization results in a reactive metal-semiconductor interface and low contact resistance values for samples with and without Ni.     

Study of the step coverage and contact resistance by using two-step TiN barrier and evolve simulation

Device aspect ratios and dimensions at the contact and via levels for old and new technologies are driving PVD/WCVD-based metallization to its full limit at integrated circuits (ICs) fabrication sites (Wilson et al., 1993). Contact and via This work describes the work performed at ST Microelectronics regarding the TiN barrier film properties with respect to process variables. Single-step and dual-step TiN barrier processes were studied for contact and via step coverage profiles used for aluminum and tungsten plug technologies. Electrical contact resistance values were evaluated using single and dual step TiN barrier processes. EVOLVE, a topography simulation program was used to study the step coverages and deposited film profiles for single and dual steps TiN barrier processes. In this work we prove that dual step TiN barrier process is superior to single step TiN barrier process in terms of step coverage, current leakage, film stress and contact resistance values.