A novel high-speed sense-amplifier-based flip-flop

A new sense-amplifier-based flip-flop is presented. The output latch of the proposed circuit can be considered as an hybrid solution between the standard NAND-based set/reset latch and the NC-/sup 2/MOS approach. The proposed flip-flop provides ratioless design, reduced short-circuit power dissipation, and glitch-free operation. The simulation results, obtained for a 0.25-/spl mu/m technology, show improvements in the clock-to-output delay and the power dissipation with respect to the recently proposed high-speed flip-flops. The new circuit has been successfully employed in a high-speed direct digital frequency synthesizer chip, highlighting the effectiveness of the proposed flip-flop in high-speed standard cell-based applications.     

Novel design and simulation of microthyristor-based flip-flop circuits

This paper describes the development of new configurations for flip-flops which are based on a microthyristor as a storage element, the NMOS transistor as a series switch or a driver and a high pull-up resistor. The performance of these flip-flops is analysed, using a PSPICE simulator. These devices perform well with regard to speed and power consumption and are more compact because of the use of the microthyrister.     

时钟低摆幅双边沿低功耗触发器的设计

传统的时钟低摆幅触发器由于工作方式和电路结构不够合理,使得电路的结点电容和开关活动性较大,增加了电路的开关功耗.本文通过改进传统的时钟低摆幅触发器的工作方式和电路结构,设计了一种新型的时钟低摆幅双边沿触发器--反馈保持型时钟低摆幅双边沿触发器(Feedback Keeper Low-swing Clock Double-edge-triggered Flip-flop-FK-LSCDFF).模拟结果表明所设计的触发器具有正确的逻辑功能,跟传统的时钟低摆幅双边沿触发器相比,降低近17%的功耗.     

A novel low power flip-flop design using footless scheme

A highly compact source follower coupling based low-pass filter (LPF) topology is proposed that synthesizes a 3rd-order low-pass transfer function in a single stage with no use of operational amplifiers. Chopper stabilization technique is utilized to reduce 1/f noise for minimizing the in-band integrated noise. Implemented and simulated in a 0.18 μm CMOS process, the 3rd-order LPF achieves a ??3 dB bandwidth of 20 MHz with a 280 μA total current from a 1.4 V supply voltage, defining a power-per-pole/bandwidth efficiency of 6.5 μW/MHz. The output noise density at low frequencies is largely reduced with chopper stabilization technique. The integrated output noise from 10 kHz to 2 MHz is minimized from 22.47 to 7.04 μV_rms, with a 10.1 dB improvement. The averaged output noise density over the filter bandwidth is 9.4 nV/√Hz, which is mostly contributed by thermal noise of transistors.     

基于去抖动的JK触发器实验设计

JK触发器是一种功能完善且应用很广泛的触发器。在实验中,JK触发器实验虽然用Protues软件仿真能顺利完成,但是在实验箱上连接电路却不能得到预期的正确结果,这是开关抖动造成的。在此引入一种改进的电路:在时钟信号产生电路中引入由基本RS锁存器构成的去抖动电路,其可以有效地消除触点抖动造成的实验结果错误和误触发,得到与理论完全一致的结果。     

基于门控时钟技术的低功耗三值D型触发器设计

本文在三值D型触发器的基础上提出了一种低功耗三值门控时钟D型触发器的设计.该设计通过抑制触发器的冗余触发来降低功耗,PSPICE模拟验证了该触发器具有正确的逻辑功能.与三值D触发器相比,该触发器在输入信号开关活动性较低的情况下具有更低的功耗.同时该电路结构可以推广到基值更高的低功耗多值触发器的设计中.     

Optical flip-flop

The operation of a clocked optical S-R flip-flop, based on a polarisation-bistable semiconductor laser, is demonstrated.     

Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead

Fine-grained power gating is the rigorous application of sleep transistor scheme to reduce stand-by power consumption in idle circuit blocks. Small circuit blocks are suspended for a short time while they are temporarily not needed. A sense-amplifier-based state retention flip-flop is proposed, that preserves the logical state of the circuit during these short idle periods. This dynamic state retention flip-flop requires neither additional control signals nor an additional power supply for its state retention functionality. An integration into a standard design flow is possible without any modifications. The tradeoff between propagation delay and retention time is derived analytically. Retention times in the range of milliseconds can be achieved with D-to-Q delays of 100 ps to 200 ps.     

Complementary Josephson-junction circuit: a fast flip-flop and logic gate

A logic circuit with Josephson junctions has been developed that operates as logic gate or as a flip-flop. Despite the latching-type characteristic of the Josephson tunnel junction, the complementary logic circuit is nonlatching. The test circuit has a power dissipation of 16.4 ?W and a signal risetime of approximately 60 ps has been measured.     

High-performance and low-power conditional discharge flip-flop

In this paper, high-performance flip-flops are analyzed and classified into two categories: the conditional precharge and the conditional capture technologies. This classification is based on how to prevent or reduce the redundant internal switching activities. A new flip-flop is introduced: the conditional discharge flip-flop (CDFF). It is based on a new technology, known as the conditional discharge technology. This CDFF not only reduces the internal switching activities, but also generates less glitches at the output, while maintaining the negative setup time and small D-to-Q delay characteristics. With a data-switching activity of 37.5%, the proposed flip-flop can save up to 39% of the energy with the same speed as that for the fastest pulsed flip-flops.     

Improved polarization measurements using a modified three-antennatechnique

An improved three-antenna measurement of polarization that greatly reduces the uncertainty due to phase measurement errors is described. This technique is used to calibrate polarization standards and probes used in near-field antenna measurements     

Improved beat-to-beat timing measurements of His-bundle signal

A simplified bioelectric model of the atrioventricular (AV) junction is proposed to better understand the underlying biophysical generation of intracardiac His-bundle signal and to analyze the effects of electrocatheter displacements on waveform morphology and estimation of AV node conduction time (AVCT). Based on this model, an inverse problem approach has been developed to estimate electrode displacements occurring in real recordings. A measurement correction method is proposed to improve estimation of AVCT. Results illustrate autonomic influences on AVCT, a phenomenon hardly measured with common techniques     

Packaged and hybrid integrated all-optical flip-flop memory

A fully-packaged hybrid-integrated all-optical flip-flop, where InP-based semiconductor optical amplifiers are assembled onto a planar silica waveguide board, is demonstrated. It is shown experimentally that the flip-flop can dynamically toggle between its two states by injecting 150 ps optical pulses with 6 dBm peak power via its set and reset port     

All-optical flip-flop operation of VCSOA

An all-optical flip-flop, the memory of which is based on dispersive bistability in a single vertical cavity semiconductor optical amplifier, is demonstrated experimentally. Flip-flop control is achieved using two mechanisms: cross-phase modulation to set the flip-flop and cross-gain modulation of the holding beam within a remote SOA to reset it. Optical control signals are sub-milliwatt in power and derived from a single 5 ns, 1539 nm initial pulse. Flip-flop operation at 1542 nm is polarisation insensitive to control signals and achieved with an on-off contrast greater than 3 dB.     

改进型激光三角测头设计

设计了一种改进型激光三角测头,在传统直射式激光三角测距方法的基础上,提出了一种新型单透镜设计理念。以普通直射式激光三角法为基础,对该光路进行改进,在光学系统中使用一个分束镜来取代传统激光三角测头的聚焦透镜和成像透镜,令其与聚光透镜和光电探测器共轴,使系统的结构更加紧凑,并推导了满足该结构的Scheimpflug条件。同时利用Zemax光学设计软件仿真光学系统,系统入瞳直径4 mm,焦距20 mm,总长20.5 mm,满足测量系统的小型化。当与合适的光源和探测器配合使用时,能够在保证较高测量精度的前提下获得更大的工作范围,提高测量系统的环境适应性,可广泛应用于工业实时在线检测以及军事领域。     

一种攻丝丝锥的改进设计及试验

本文叙述了普通标准丝锥攻丝高韧性金属材料的困难性和存在的问题,针对该种金属材料的机加工特性,对丝锥材料的选择及其结构形式进行了改进设计和试验,并提出了攻丝加工的工艺参数和相应措施.     

改进的Bayer插值算法及其硬件实现

为了改善彩色恢复效果,降低硬件设计的复杂度 ,提出了一种基于Bayer格式图像彩色插值改进算法。首先,对Bayer格式原图进行二阶 拉普拉斯修正,获取水平方向和垂直方向的绿色分量 V;然 后,计算红色通道和蓝色通道分别与绿色分量的水平色差R－H、B－ H和垂 直色差R－V, 再对色差方向插值,得到水平和垂直方向的梯度并进行比较,根据比较结果选择V作为选定像素处 的绿色分量;当整幅图像的绿色分量得到后,利用给定像素周围的4个色差进 行插值计算,分别得到红 色分量,从而完成彩色图像的恢复。试验结果表明, 改进的算法在峰值信噪比(PSNR)上相 比双线性插值(BI)算法,R、G、B三通道均提高15 dB左右,且图像目视细节 丰富,伪彩色得到有效抑制,特 别是硬件实现难度方面和线性算法相当,能够做到硬件实时处理。目前,算法已经在Xilinx FPGA上实现,并工程应用,满足了项目实际需要。     

Improved resolution backscatter measurements with the SeaWindspencil-beam scatterometer

The SeaWinds scatterometer was launched on the NASA QuikSCAT spacecraft in June 1999 and is planned for the Japanese ADEOS-II mission in 2000. In addition to generating a global Ku-band backscatter data set useful for a variety of climate studies, these flights will provide ocean-surface wind estimates for use in operational weather forecasting. SeaWinds employs a compact “pencil-beam” design rather than the “fan-beam” approach previously used with SASS on Seasat, NSCAT on ADEOS-I, and the AMI scatterometer on ERS-1, 2. As originally envisioned and reported, the resolution of the SeaWinds backscatter measurements were to be antenna-beamwidth limited. In order to satisfy an emerging demand for higher resolution backscatter data, however, the SeaWinds signal-processing design has been significantly modified. Here, the various options considered for improving the resolution of the SeaWinds measurements are discussed, and the selected hardware modification (the addition of deramp processing for range discrimination) is described. The radar equation specific to a rotating pencil-beam scatterometer with digital range filtering is developed, and the new challenges associated with calibrating the resulting improved resolution measurements are discussed. A formulation for assessing the variance of the measurements due to fading and thermal noise is presented. Finally, the utility of improved resolution SeaWinds measurements for land and ice studies is demonstrated by simulated enhanced-resolution imaging of a synthetic Earth backscatter scene     

Improved MOS capacitor measurements using the Q-C method

We describe a method for determining band bending vs gate bias, doping profile and oxide charge density by simultaneous measurement of charge and high frequency MOS capacitance as a function of applied voltage. This charge-capacitance or Q-C method is compared with the usual MOS measurements for the same properties. We find the Q-C method is more accurate and more routine than methods presently in use.In addition, accurate and systematic procedures are introduced for (1) finding the additive constant in the band bending vs gate bias relation, (2) eliminating interface trap error in the doping profile, (3) extrapolation of the doping profile to the interface in the region inaccessible to measurement, (4) correction of oxide charge and work-function determination for interface trap errors and effects of nonuniform doping profiles.     

Improved six-port circuit for complex reflection coefficient measurements

A new improved six-port circuit for complex reflection coefficient measurements is presented. It consists of two six-port directional couplers. Assuming the components to be ideal, it is shown that the described six-port circuit has optimal properties for accurate determination of complex reflection coefficients. A six-port branchline coupler is briefly described.