基于LTCC微波多层基板的双面微组装技术研究

传统的微波组件通常在低温共烧陶瓷(LTCC)微波多层基板上单面组装裸芯片和片式元器件,组装密度难以进一步提高.文中采用了LTCC微波多层基板双面微组装技术以提高组装密度,重点研究了高精度芯片贴装技术和芯片金丝键合技术,实现了LTCC微波多层基板双面高精度芯片贴装和金丝键合,大大提高了微波组件组装密度.实验结果表明:裸芯片的双面贴装精度均达到了±20 μm;双面金丝键合强度(破坏性拉力)均大于5 g,满足国军标要求.     

应用于雷达TR组件微组装中的气相清洗技术

随着相控阵雷达技术的发展,大规模应用了裸芯片等能够减小组件体积、减轻组件重量的精密元器件。然而这些元器件在基板贴装元器件的微组装过程中,容易在采用常规清洗手段产生的机械力作用下损伤,需要寻找无损的清洗手段。而气相清洗以其无机械力作用、无振动的特点正在受到越来越多的关注。文中以实际生产中组件内常见污染物为例进行气相清洗,并对清洗效果进行了评价和分析。     

面向便携化电子产品的封装技术

随着人们对便携式的和手持设备的市场需求不断增加,为了能够在具有较高功能的前提下,拥有小型化、轻型化和高性能的器件,使用裸管芯产品的多芯片封装的益处就非常明显。于是开发设计和组装技术面临着新的挑战,人们关注采用比传统的表面贴装器件更低的成本,来获取比芯片上系统解决方案更快的进入市场的时间。使这些先进的封装技术得以实现的因素是依赖芯籽产品。     

应用于裸芯片去污的气相清洗技术

军用和民用微型电子产品的MCM、HIC等复杂混合电路正在越来越多地采用裸芯片,然而,裸芯片由于尺寸小、电路密集、焊盘间距小等原因,在进行组装的过程中一旦有微量的污染物出现,就会对裸芯片的应用造成较大影响。气相清洗通过清洗溶剂蒸汽在组件表面冷凝,形成液体滴下带走污染物,避免了传统的通过机械力、超声振动等清洗方式对裸芯片造成的不可修复的损伤。对限幅二极管砷化镓裸芯片、硅基裸芯片进行气相清洗,有效除去裸芯片表面的污染物,具有无损高效的特点。     

浅析贴片设备

由于表面组装技术不断地朝着小型化的方向发展 ,特别是在细间距、小直径的凸点和使用的焊剂等诸多因素的推动下 ,促使设备供应商根据倒装芯片技术的需求而研制新一代的贴装机。介绍了设备的制造厂家根据倒装芯片的特点 ,采用柔性 (软件 )方法和视觉系统等方案对现有的设备进行改型 ,从而实现了贴装设备的自动化。实践证明研制开发倒装芯片技术的自动组装技术可使生产率、材料和工艺设备取得明显的进步     

采用单体载带技术对裸芯片进行测试老化筛选

军用ＨＩＣ大量采用裸芯片进行组装，尽管组装好的电路要老化筛选，但加在裸芯片上的应力远远不够，为了研制高可靠的ＨＩＣ，对裸芯片的老化筛选技术作了研究。在综合国外技术的基础上，提出了裸芯片的老化筛选方法     

浅析贴片设备

由于表面组装技术不断地朝着小型化的方向发展，特别是在细间距、小直径的凸点和使用的焊剂的诸多因素的推动下，促使设备供应商根据倒装芯片技术的需求而研制新一代的贴装机。本主要介绍了设备的制造厂家根据倒装芯片 的特点，采用柔性（软件）方法和视觉系统等方案对现有的设备进行改型，从而实现了贴装设备的自动化。实践证明研制开发倒装芯片技术的自动组装技术可使生产率、材料和工艺设备取得了明显的进步。     

HIC中芯片的老化筛选技术

军用ＨＩＣ电路大量采用裸芯片进行组装。尽管组装好的电路要老化筛选，但加在单个裸芯片上的应力远远不够。为了研制高可靠的ＨＩＣ电路，本文对裸芯片的老化筛选技术作了研究。在综合国外技术的基础上，提出了裸芯片的老化筛选方法。     

CIS生产中的SMT与COB技术

表面贴装技术 (SMT)和板载芯片技术 (COB)在当今电子产品组装中起着越来越重要的作用。从工艺方案的确定至具体的工艺实施 ,介绍了表面贴装技术与板载芯片技术相结合的混装工艺在CIS生产中的应用。     

表面组装技术的发展趋势

分析了表面组装工艺和表面组装设备的发展趋势,指出了表面组装工艺的芯片级组装技术、多芯片模块技术和三维立体组装技术等三大发展趋势.同时给出了贴装机、印刷机、回流焊机、波峰焊机、清洗设备和检测设备的发展趋势.     

Chip on paper technology utilizing anisotropically conductive adhesive for smart label applications

Smart labels are a new generation of low cost transponders consisting of a transponder chip and a flexible type of antenna. Applying a flip chip assembly technology yields a new generation of low cost radio frequency identification (RFID) system that is a paper-thin smart label. Anisotropically conductive adhesive (ACA) is utilized to attach a flip chip onto a paper substrate to form the BiStatix RFID tag. Unlike bar codes, which are passive tags, smart labels can dynamically transmit and receive information to help identify, track and route packages remotely. The concept of flipping or inverting a silicon chip to be mounted on a paper substrate offers distinct advantages and enables achieving the cost and performance goals of this new product technology.Significant process development and reliability assessment was required to develop this smart label application. This paper discusses the process development and reliability assessment that was completed to achieve a low cost flip chip on paper assembly process. The various characteristics of ACA made it an enabling technology for this smart label application. A bare (unbumped) flip chip––without a dielectric layer and conductive polymer bumps––was aligned and placed on the paper substrate with compressive force. A thin layer of anisotropically conductive adhesive was used to attach the IC chip to the conductive ink antenna on the paper substrate. The conductive adhesive underfills and cures in only seconds. Advantages of this environmentally preferred process include the elimination of additional curing processes and reduced equipment requirements as well as the reduction of total IC packaging thickness.     

Development of process modeling methodology for flip chip on flex interconnections with non-conductive adhesives

This paper presents a comprehensive methodology to model the assembly process of flip chip on flex interconnections with non-conductive adhesives (NCAs). The methodology combines experimental techniques for material characterization, finite element modeling, and model validation. A non-conductive adhesive has been characterized using several techniques. A unique experimental technique has been developed to measure the cure shrinkage. A 2D axisymmetric finite element model is used for analysis of flip chip on flex package with the non-conductive adhesive (NCA), which takes into account assembly force, cure shrinkage, adhesive modulus buildup, removal of assembly force, and cooling down to room temperature. The relationship between the bump contact resistance and the bump pressure has been established through the development of a dedicated experimental setup, which uses a micro-force tester combined with a digital multimeter and a nano-voltmeter. The process modeling has been validated by comparing the predicted bump contact resistance value and the measured bump contact resistance value after assembly process. The approach developed in this paper can be used to provide guidelines with respect to adhesive material properties, assembly process parameters, and good reliability performances.     

86 Gbit/s SiGe receiver module with high sensitivity for 160/spl times/86 Gbit/s DWDM system

A 86 Gbit/s SiGe receiver chip with an on-chip phase-locked loop and a preamplifier is presented. The chip is mounted and measured in a module assembly with RF-connectors. At the intended system data rate of 86 Gbit/s bit-error-free operation at a high input sensitivity of 50 mV/sub pp/ is demonstrated. With an external clock, high-speed capability is proven by error-free operation up to 100 Gbit/s     

Study of the electrical performance of chip-on-board (COB) devices

When a bare die is flipped directly onto the printed circuit board (PCB) during chip-on-board assembly, it becomes exposed to a number of factors, which could influence its electrical performance. Although the mechanical integrity of flip-chip devices has been thoroughly studied, there is very little evidence of detailed investigations of the electrical performance of these devices. The present paper aims to bridge this gap by studying the electrical parameters of flip chip devices and analysing the changes occurring following assembly. A dedicated test chip comprised of passive and active semiconductor devices was designed for the study. Two different types of tacky flux and underfill materials were used in the flip chip assembly process. The flip chip structures were then subjected to various environmental stress techniques for accelerating ageing. Electrical parameters of the devices such as threshold voltage, I-V characteristics, off-state leakage current, current gain, and resistance were measured at various stages of the programme. A slight change in device parameters was observed immediately after assembly. Further change in some device parameters was observed after environmental stressing. The paper investigates the mechanisms that could be responsible for the changes, such as mechanical stresses introduced during the flip chip process or ionic contamination inherent to the assembly process.     

Heat dissipation from silicon chips in a vertical plate,elevated pressure cold wall system

The heat dissipation effects of elevated pressure and cold gas temperature on vertically configured module mounted and free hanging chips were examined. It was found that with both types of chips, the thermal resistance (temperature rise x area/power) varies linearly with pressure in a log-log plot. A free hanging chip exhibits a (-1/3) power dependency on pressure while the module mounted chip exhibits a (-1/5) power dependency on pressure. The thermal resistance of the module mounted chip also appears to exhibit a dependency on gas temperature, but not on the difference in temperature between the chip and cold gas. The thermal resistance of the module mounted chip is some 5x lower than that of the free hanging chip, demonstrating that the module acts to a degree as a thermal expander. The efficiency is less than 20% based on the fact that the module area is some 30x greater than the chip area. For the module mounted chip, and a combination of a liquid nitrogen gas temperature and 1500 psi ambient atmosphere pressure, > 30 W/chip (0.180 in. × 0.180 in.) (0.46 cm × 0.46 cm), can be dissipated with a temperature rise to 85°C. This translates to a heat dissipation capability of more than 900 W/in².     

Development of chip-on-flex using SBB flip-chip technology

A bare LSI chip mounted onto a flexible substrate is called chip-on-flex (COF). Companies and universities are desperately developing COF. In this paper, the development of COF using stud bump bonding (SBB) flip-chip technology will be introduced.So far, SBB technology has been adopted when ceramic or glass-epoxy is used as a substrate material for chip size packages (CSPs) and multi-chip modules (MCMs). Recently there is a great demand for developing SBB technology toward a flexible substrate.SBB technology needs to keep a flexible substrate flat during the assembly process. A flexible substrate was adhered to a flat carrier using a thermal release sheet in order to keep it flat. Since this thermal release sheet loses its adhesive strength by applying heat beyond 160°C, it is easy to peel off accomplished specimens from the flat carrier after assembling.SBB specimens were prepared using liquid crystal polymer (LCP) and polyimide (PI) as a flexible substrate. Reliability tests, such as pressure cooker test (PCT), thermal shock test (TST) and reflow soldering after moisture storage test, were carried out for these specimens. In PCT, both LCP and PI specimens passed as a result of using proper underfill for each substrate. In TST, both specimens also passed using the underfill selected in PCT. In reflow soldering after moisture storage test, LCP specimens passed, on the other hand PI specimens needed to be baked after moisture storage in order to pass the reflow.     

Fabrication and characterization of SPR chips with the modified bovine serum albumin

A facile surface plasmon resonance (SPR) chip is developed for small molecule determination and analysis. The SPR chip was prepared based on a self assembling principle, in which the modified bovine serum albumin (BSA) was directly self-assembled onto the bare gold surface. The surface morphology of the chip with the modified BSA was investigated by atomic force microscopy (AFM) and its optical properties were characterized. The surface binding capacity of the bare facile SPR chip with a uniform morphology is 8 times of that of the bare control SPR chip. Based on the experiments of immune reaction between cortisol antibody and cortisol derivative, the sensitivity of the facile SPR chip with the modified BSA is much higher than that of the control SPR chip with the un-modified BSA. The facile SPR chip has been successfully used to detect small molecules. The lowest detection limit is 5 ng/mL with a linear range of 5—100 ng/mL for cortisol analysis. The novel facile SPR chip can also be applied to detect other small molecules.