共查询到18条相似文献,搜索用时 46 毫秒
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观察了ULSI中大马士革结构的Cu互连线的晶粒生长和晶体学取向.分析了线宽及退火对Cu互连线显微结构及电徙动的影响.Cu互连线的晶粒尺寸随着线宽的变窄而减小.与平坦Cu膜相比,Cu互连线形成微小的晶粒和较弱的 (111) 织构.300℃、30min退火促使Cu互连线的晶粒长大、(111) 织构发展,从而提高了Cu互连线抗电徙动的能力.结果表明,Cu的扩散涉及晶界扩散与界面扩散,而对于较窄线宽的Cu互连线,界面扩散成为Cu互连线电徙动失效的主要扩散途径. 相似文献
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本文根据工业上使用的铜大马士革互连线尺寸建立了三维有限元模型,模拟计算了铜大马士革互连线中对应力诱导形成空洞很关键的静水应力分布,对比分析了不同低k介质、阻挡层材料和互连线深宽比对静水应力的影响。研究结果表明,静水应力受k介质、阻挡层材料和互连线深宽比影响很大,静水应力在铜大马士革互连线中分布不均匀且最大应力出现在互连线表面。 相似文献
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AFM加工的Ti纳米氧化钛线的直线度分析 总被引:1,自引:0,他引:1
为了与微电子加工工艺相结合,基于Ti氧化线的纳米电子和光电器件需要加工μm级长的Ti氧化线。Ti氧化线的直线度决定了加工的纳米器件的形状,从而影响纳米器件的工作特性。在偏置电压8 V、扫描速度0.1μm/s的条件下,在7μm×7μm的范围内从左到右每隔1μm加工了6条5μm长的Ti纳米氧化线,研究了针尖磨损和压电陶瓷扫描器等因素对加工的Ti氧化线的直线度的影响,原子力显微镜(AFM)扫描范围的中间位置加工的Ti氧化线的高度和宽度的一致性与直线度最好。 相似文献
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扫描探针显微镜(SPM)作为一种广泛应用的表面表征工具,不仅可以表征三维形貌,还能定量地研究表面的粗糙度、孔径大小和分布及颗粒尺寸,在许多学科均可发挥作用.以纳米材料为主要研究对象,综述了国外最新的几种扫描探针显微表征技术,包括扫描隧道显微镜(STM)、原子力显微镜(AFM)和近场扫描光学显微镜(SNOM)等方法,展示了这几种技术在纳米材料的结构和性能方面的应用. 相似文献
6.
在集成电路中,全局互连线的设计是关键.分析了互连线RC和RLC模型的不同特性;针对互连线与CMOS器件级联的电路进行分析.分析了集成电路中互连线和CMOS的模型对性能的影响,并给出了基于HSPICE软件的仿真结果.仿真结果表明,不同互连线和CMOS模型对系统传输特性有一定影响. 相似文献
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有机/无机光电探测器的AFM和XPS分析 总被引:7,自引:3,他引:4
采用真空蒸发沉积,在室温下制备了PTCDA/p—Si有机/无机异质结样品。对其表面用原子力显微镜(AFM)研究表明,PTCDA薄膜具有岛状形态结构。经X光电子能谱(XPS)分析表明,在PTCDA分子中,C原子有两种束缚能态,其结合能力分别为285.3eV和288.7eV;O原子与C原子相邻,一些O原子通过双键与C原子相结合,另外的O原子则通过单键与2个C原子相结合。经Ar^ 束溅射研究界面电子状态表明,随溅射时间增加,C1s和O1s峰逐渐减弱,而Si 2p和Si 2s峰渐渐增强。C1s和Si 2p谱峰随着溅射时间的增加而逐渐向低束缚能力方向移动。由于荷电效应和碳硅氧烷(C—Si—O)及SiO2的存在,Ols谱峰随溅射时间的增加先向高束缚能方向移动,然后向低束缚能方向移动。 相似文献
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Jae-Young Cho Hyo-Jong Lee Hyoungbae Kim Jerzy A. Szpunar 《Journal of Electronic Materials》2005,34(5):506-514
Influence of annealing on the textural and microstructural transformation of Cu interconnects having various line widths is
investigated. Two types of annealing steps have been considered here: room temperature over 6 months and 200°C for 10 min.
The texture was determined by x-ray diffraction (XRD) of various cross-sectional profiles after electropolishing, and the
surface, microstructure, and grain boundary character distribution (GBCD) of Cu interconnects were characterized using electron
backscattered diffraction (EBSD) techniques. In order to analyze a relationship between the stress distribution and textural
evolution in the samples, microstresses were calculated with decreasing line widths at 200°C using finite element modeling
(FEM). In this investigation, it was found that the inhomogeneity of stress distribution in Cu interconnects is an important
factor, which is necessary for understanding textural transformation after annealing. A new interpretation of textural evolution
in damascene interconnects lines after annealing is suggested, based on the state of stress and the growth mechanisms of Cu
electrodeposits. 相似文献
11.
Jung-Kyu Jung Nong-Moon Hwang Young-Joon Park Young-Chang Joo 《Journal of Electronic Materials》2005,34(5):559-563
Microstructure in the damascene interconnects evolves with the overburden layer, an excessive metal layer over trenches. We
present the results of three-dimensional simulation, which show the effects of overburden thickness on microstructure evolution
in a trench. When the thickness of the overburden is less than half of the trench depth, for a trench with the aspect ratio
of unity, the microstructure in the trench tends to evolve into a bamboo structure. This effect is discussed in terms of grain
sizes in the trench and those in the overburden. The thinner overburden layer would have smaller grains, of which growth is
limited by its thickness. Such small-sized grains in the overburden are not likely to grow into the trench, which hardly make
grain boundaries in the trench. Meanwhile, the grains from the trench are able to continue growth inside the trench, resulting
in a bamboo structure. Overburden thickness affects the reliability and the electrical performance of the damascene copper
interconnects. Optimization of overburden thickness is required to minimize these effects. 相似文献
12.
Seiichi Kondo Kouichi Fukaya Tadakazu Miyazaki Daisuke Abe Taro Enomoto 《Microelectronic Engineering》2007,84(11):2615-2619
Both chemical and mechanical damages to porous SiOC film should be minimized in the Cu-CMP (chemical mechanical polishing) process for the 32-45 nm node Cu interconnect process. This paper first discusses chemical damage that occurs during direct CMP on a porous SiOC film. We found that the k-value increase after direct CMP was caused by the surfactants added to the cleaning chemicals to suppress watermark generation on the hydrophobic SiOC film surface. The surfactants assisted water molecule diffusion into the pores by improving the wettability of the film surface. N2 annealing after direct CMP removed moisture inside the pores and restored the k-value increase. Second, the paper discusses low-pressure electro-CMP (e-CMP) technology that we developed to reduce mechanical stress on the porous SiOC film. A high removal rate and good planarization performance were obtained by optimizing the cathode area of the electro-cell and carbon material of the e-CMP pad. 相似文献
13.
Mechanical stress in damascene copper/low-k interconnects has been studied by means of micro-rotating sensors embedded in chips and directly integrated in CMOS process flow. A new hinge sensor design has been elaborated and a new analytical model of the mechanical equilibrium of sensors is validated. These sensors allow the study of the average residual stress as a function of the line width in a range from few hundred nanometers to several microns. It was found that the residual stress increases from 290 to 850 MPa in, respectively, 2 and 0.25 μm wide lines. This trend shows a yield stress increase with the line width reduction. Copper grains microstructure change between large and narrow lines is probably one of the reasons for yield stress and so residual stress increase. This microstructure change has been observed by means of Transmission Electron Microscopy (TEM) observations. 相似文献
14.
Stefan Brandstetter Vincent Carreau Sylvain Maîtrejean Marc Legros 《Microelectronic Engineering》2010,87(3):383-386
The evolution of the grain structure through annealing of narrow damascene Cu interconnects is important for any further design of highly integrated circuits. Here we present a comprehensive transmission electron microscopy study of damascene lines between 80 nm and 3000 nm wide. Experimental results clearly indicate that morphology evolutions through annealing are strongly influenced by the line width. If the lines are wider than 250 nm a strong connection between the grain structure within the lines and the overburden copper is present at least after sufficient annealing. Once the lines are as small as 80 nm the grain structure within the lines are only weakly connected to the overburden copper grown above. 相似文献
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The anisotropic spread of the central peak in a (111) pole figure by x-ray diffraction (XRD) was observed for damascene Cu
lines of 0.18–2 μm in width and 0.5 μm in depth. The spread originates from the existence of slightly tilted (111) grains
because of inclined sidewalls. The tilted (111) orientation is favorable only for polygranular clusters whose sidewall energies
can be minimized simultaneously. Consequently, bamboo grains have an exact 〈111〉 orientation, while the polygranular clusters
have a tilted 〈111〉 orientation. Using this concept, the volume fraction of the bamboo grains and polygranular clusters in
the damascene Cu lines were quantified using the XRD pole plots. 相似文献
17.
This study is devoted to thermomechanical response and modeling of copper thin films and interconnects. The constitutive behavior
of encapsulated copper film is first studied by fitting the experimentally measured stress-temperature curves during thermal
cycling. Significant strain hardening is found to exist. Within the continuum plasticity framework, the measured stress-temperature
response can only be described with a kinematic hardening model. The constitutive model is subsequently used for numerical
thermomechanical modeling of Cu interconnect structures using the finite element method. The numerical analysis uses the generalized
plane strain model for simulating long metal lines embedded within the dielectric above a silicon substrate. Various combinations
of oxide and polymer-based low-k dielectric schemes, with and without thin barrier layers surrounding the Cu line, are considered.
Attention is devoted to the thermal stress and strain fields and their dependency on material properties, geometry, and modeling
details. Salient features are compared with those in traditional aluminum interconnects. Practical implications in the reliability
issues for modern copper/low-k dielectric interconnect systems are discussed. 相似文献
18.
Nanotwin formation and its physical properties and effect on reliability of copper interconnects 总被引:1,自引:0,他引:1
Di Xu Vinay Sriram Jenn-Ming Yang Gery R. Stafford Inka Zienert Petra Hofmann 《Microelectronic Engineering》2008,85(10):2155-2158
Ultra-fine grained copper with a large amount of nano-scale twin boundaries has high mechanical strength and maintains normal electrical conductivity. The combination of these properties may lead to promising applications in future Si microelectronic technology, especially as interconnect material for air-gap and free-standing copper technologies. Based on first principles calculations of total energy and in-situ stress measurements, high stress followed by stress relaxation during the Cu film deposition seems to have contributed to nanotwin formation. Nanoindentation studies have shown a larger hardness for copper with a higher nanotwin density. The effect of Cu nanotwin boundaries on grain growth was investigated by scanning electron microscopy (SEM), electron backscatter diffraction (EBSD) and transmission electron microscopy (TEM). The presence of a high density of nanotwin boundaries may improve the reliability of Cu interconnects. 相似文献