基于遗传编程的HFC-ADM算法在滤波器进化设计中的应用

该文在电路进化设计中使用遗传编程和键合图结合的进化设计方法,并且引入了分等级公平竞争(HFC)模型,采用自适应阈值控制不同等级之间的迁移,并结合动态的参数与拓扑空间进化设计了一个模拟滤波器。实验结果表明该算法不仅扩大了搜索空间,还有较强的持续进化能力,进一步证明了该方法的可行性和有效性。     

基于基因表达式的演化硬件进化和优化算法

电路进化设计是可进化硬件研究的重要内容．针对电路进化设计做了如下工作：(1)融合了数据挖掘、基因表达式编程与传统电路进化技术,提出两阶段电路进化方法．该方法包括基于表达式树遗传编程进化算法的电路进化阶段和基于挖掘频繁数字电路算法的电路优化阶段。(2)给出了详尽的实验．实验表明6次多项式函数发现的平均进化代数为442代、乘法器电路的平均进化代数为2292代．比笛卡尔遗传编程和NEHF(Novel Evolvable Hardware Framework)快6倍以上．用MFDC对乘法器电路进化结果进行挖掘后,得到了比传统电路更有效的乘法器电路。     

基于20-sim软件的非线性电路仿真

利用20-sim软件的功能,可以对非线性电路进行直接面向方程的仿真分析,也可以在现有非线性电路的基础上,转换成相应的键合图模型,利用键合图理论进行仿真分析.为了对这两种仿真分析方法进行对比分析,选取杜芬方程作为研究对象,提出了运算放大器的键合图模型,分别用图形化的方法与键合图方法进行了仿真,并对两种方法进行了结论性的比较.     

基于键合图的电力电子电路建模与仿真

随着DC-DC变换器的实际应用领域的不断扩大,人们对变换器系统的稳定性提出了更高的要求,因此,精确而有效的建模和仿真对于变换器的发展有着重大的意义。本文以电力电子Buck电路为例,提出混合键合图模型和键合图平均模型两种模型,这两种模型都是在键合图建模理论的基础上,根据电路中开关控制方式的不同而得到的。首先经过分析得到Buck电路的两种键合图模型,并在GME(Generic Modeling Environment)软件中搭建模型,然后通过该软件将它转换为Matlab框图模型并仿真,最后将仿真结果与实际电路模型的输出波形进行对比分析,验证了两种模型的可行性和正确性。     

金丝键合短尾问题分析及解决

金丝键合通常由金丝球超声键合完成。短尾是金丝球键合过程中一个典型的失效模式,详细分析了金丝球键合过程中第二点键合的四个关键步骤,分析了第二点键合形貌形成过程,分别研究了键合第二点各个区域与键合劈刀的位置关系,在此基础上详细分析了造成第二点键合金丝短尾的主要因素和机理,提出劈刀上升前后两种主要的短尾模式,得出键合参数是影响键合质量和键合强度的关键因素,给出了优化改进措施,提出通过降低超声功率和压力,或者通过优化原材料、劈刀,以便使用较低的工艺参数就可以完成键合,解决第二点键合短尾问题。     

基于FPTA的动态可重构模拟电路研究

阐述了基于FPTA的模拟可进化电路的设计方法,分析了FPTA的结构,介绍了进化设计所使用的遗传算法,分析了使用PSpice软件建立的仿真模型,并通过VB程序实现算法并对演化过程进行控制.以4位数模转换电路(DAC)为例,通过对4个FPTA细胞组成的电路结构进行进化实验,结果表明4个FPTA细胞完全能够进化得到4位DAC.     

基于遗传编程的智能建模方法及应用

遗传编程是基于自然进化理论的一种全局最优智能搜索技术.基于遗传编程的智能建模方法可以建立复杂系统的数学模型,与其它建模方法相比,该方法具有同时辨识系统的结构和参数,并且得出的辨识结果是显示的等优点.提出了一种新的多目标遗传编程算法,将进化的目标设定为偏差的平方和、表达式的复杂程度和最大动态偏差的综合最小.应用该方法建立火电厂机炉协调控制系统模型,仿真结果说明该算法是有效的.     

EPROM编程器介绍

该EPROM编程器是在计算机的控制下,实现了程序写入、读取、检验、拷贝和编辑修改等功能,也可以按字节、按段进行读写等功能。设计中,采用逻辑阵列技术,在一个测试插座上分别可对二十一种芯片进行编程;采用升压变换技术,将计算机的5V和12V电压变换为适用于各种EPROM的编程电压和工作电压。从而研制成不用外接电源,写入速度高、容量大、类型多的EPROM编程器,为单片机应用开发提供了有效编程手段,如稍做修改,可设计成超大容量EPROM编程器。其基本电路也可为其它电路设计所借鉴。本文介绍读编程器的基本电路结构及其工作原理。     

用图像识别的方法检测集成电路的键合点

１引言（ａ）例１（ｂ）例２图１键合区与键合点在大规模集成电路（ＶＬＳＩ）的制造工艺中,键合区及键合点的检验是保证可靠性的一个重要环节,因为每一个键合点的好坏,直接影响整体集成电路（ＩＣ）芯片的可靠性．图１是两例放大了一百倍的ＩＣ键合区显微图像．图中中...     

基于函数级FPGA原型的硬件内部进化

电路进化设计是现阶段可进化硬件（EHW）研究的重点内容，针对制约进化设计能力的主要“瓶颈”，该文提出并讨论了一种简洁高效的内部进化方法，包括基于函数变换的染色体高效编码方案，与之配套的函数级FPGA原型和进化实验平台以及在线评估与遗传数自适应方法等，交通灯控制器，4位可级联比较器等相对复杂且具应用价值的电路的成功进化，证明该方法适用于组合，时序电路的进化设计，并可显著地减少运算量，提高进化设计的速度和规模。     

A circuit representation technique for automated circuit design

We present a method of automatically generating circuit designs using evolutionary search and a set of circuit constructing primitives arranged in a linear sequence. This representation has the desirable property that virtually all sets of circuit-constructing primitives result in valid circuit graphs. While this representation excludes certain circuit topologies, it is capable of generating a rich set of them including many of the useful topologies seen in hand-designed circuits. Our system allows circuit size (number of devices), circuit topology, and device values to he evolved. Using a parallel genetic algorithm and circuit simulation software, we present experimental results as applied to three analog filter and two amplifier design tasks. In all tasks, our system is able to generate circuits that achieve the target specifications. Although the evolved circuits exist as software models, detailed examinations of each suggest that they are electrically well behaved and thus suitable for physical implementation. The modest computational requirements suggest that the ability to evolve complex analog circuit representations in software is becoming more approachable on a single engineering workstation     

基于理想模型和遗传算法的模拟电路自动化设计研究

受模拟电路人工设计启发,以 MOSFET 电路为例提出一种模拟电路的自动化设计方法。首先以 MOSFET 的理想模型为基础,利用遗传算法(GA)产生电路拓扑并优化其参数;然后用实际元件替换其理想模型,通过少量调整即可得到最终电路。GA 在电路拓扑生成和参数优化方面具有优势,理想模型可有效缩小算法的搜索空间,因而所提方法在最优电路拓扑生成和加快电路设计速度两方面具有更为明显的优势。通过对三次方运算电路的设计,证实了所提方法的有效性。     

Automated synthesis of analog electrical circuits by means ofgenetic programming

Analog circuit synthesis entails the creation of both the topology and the sizing (numerical values) of all of the circuit's components. This paper presents a single uniform approach using genetic programming for the automatic synthesis of both the topology and sizing of a suite of eight different prototypical analog circuits, including a low-pass filter, a crossover filter, a source identification circuit, an amplifier, a computational circuit, a time-optimal controller circuit, a temperature-sensing circuit, and a voltage reference circuit. The problem-specific information required for each of the eight problems is minimal and consists of the number of inputs and outputs of the desired circuit, the types of available components, and a fitness measure that restates the high-level statement of the circuit's desired behavior as a measurable mathematical quantity. The eight genetically evolved circuits constitute an instance of an evolutionary computation technique producing results on a task that is usually thought of as requiring human intelligence     

Applying Genetic Parallel Programming to Synthesize Combinational Logic Circuits

Experimental results show that parallel programs can be evolved more easily than sequential programs in genetic parallel programming (GPP). GPP is a novel genetic programming paradigm which evolves parallel program solutions. With the rapid development of lookup-table-based (LUT-based) field programmable gate arrays (FPGAs), traditional circuit design and optimization techniques cannot fully exploit the LUTs in LUT-based FPGAs. Based on the GPP paradigm, we have developed a combinational logic circuit learning system, called GPP logic circuit synthesizer (GPPLCS), in which a multilogic-unit processor is used to evaluate LUT circuits. To show the effectiveness of the GPPLCS, we have performed a series of experiments to evolve combinational logic circuits with two- and four-input LUTs. In this paper, we present eleven multi-output Boolean problems and their evolved circuits. The results show that the GPPLCS can evolve more compact four-input LUT circuits than the well-known LUT-based FPGA synthesis algorithms.     

Controllable decoding for automated analog circuit structure design

The decoding scheme is a major problem in automated analog circuit topology synthesis since decoding schemes bias synthesized circuit structures. However, the proper decoding scheme varies depending on the method to realize a given function. In this paper, a controllable decoding scheme is proposed in which the method to realize a function is controlled by a set of prototype circuits. Thus, the system can generate different types of analog circuits in a unified method. The prototype circuits are designed by a human and suggested to the system as hints of configurations of new analog circuits to be synthesized by the system. In the synthesis process, the information on circuit connections is stored as sub-circuits extracted from the prototype circuits. A genetic algorithm is then used to search for an optimum combination of the sub-circuits that achieves the desired electronic specifications. The combinations of sub-circuits are generated with a proposed technique where the terminals of the sub-circuits are shared. The capabilities of the proposed method are demonstrated through synthesis examples of a cubing circuit synthesis as a current-mode design and a logic circuit synthesis as a voltage-mode.The authors would like to thank the reviewers for their valuable comments. The authors would like to express special thank to Dr. Andrew M. Abo for English corrections.     

Routine high-return human-competitive automated problem-solving by means of genetic programming

Genetic programming is a systematic method for getting computers to automatically solve problems. Genetic programming starts from a high-level statement of what needs to be done and automatically creates a computer program to solve the problem by means of a simulated evolutionary process. The paper demonstrates that genetic programming (1) now routinely delivers high-return human-competitive machine intelligence; (2) is an automated invention machine; (3) can automatically create a general solution to a problem in the form of a parameterized topology and (4) has delivered a progression of qualitatively more substantial results in synchrony with five approximately order-of-magnitude increases in the expenditure of computer time. These points are illustrated by a group of recent results involving the automatic synthesis of the topology and sizing of analog electrical circuits, the automatic synthesis of placement and routing of circuits, and the automatic synthesis of controllers as well as references to work involving the automatic synthesis of antennas, networks of chemical reactions (metabolic pathways), genetic networks, mathematical algorithms, and protein classifiers.     

Analog Genetic Encoding for the Evolution of Circuits and Networks

This paper describes a new kind of genetic representation called analog genetic encoding (AGE). The representation is aimed at the evolutionary synthesis and reverse engineering of circuits and networks such as analog electronic circuits, neural networks, and genetic regulatory networks. AGE permits the simultaneous evolution of the topology and sizing of the networks. The establishment of the links between the devices that form the network is based on an implicit definition of the interaction between different parts of the genome. This reduces the amount of information that must be carried by the genome, relatively to a direct encoding of the links. The application of AGE is illustrated with examples of analog electronic circuit and neural network synthesis. The performance of the representation and the quality of the results obtained with AGE are compared with those produced by genetic programming.     

Evolving priority scheduling heuristics with genetic programming

This paper investigates the use of genetic programming in automated synthesis of scheduling heuristics for an arbitrary performance measure. Genetic programming is used to evolve the priority function, which determines the priority values of certain system elements (jobs, machines). The priority function is used within an appropriate meta-algorithm for a given environment, which forms the priority scheduling heuristic. The evolved solutions are compared with existing scheduling heuristics and found to perform similarly to or better than existing algorithms. We intend to show that this approach is particularly useful for combinations of scheduling environments and performance measures for which no adequate scheduling algorithms exist.