AES和SMS4密码算法的高效可重构实现

可重构密码芯片提高了密码芯片的安全性和灵活性,具有良好的应用前景,但其处理速度较ASIC实现的专用密码芯片却有很大程度的下降。在此分析AES和SMS4密码算法的可重构性,利用流水线、并行处理和可重构技术,提出了一种可重构体系结构。基于该体系结构实现的AES和SMS4算法较其他同类设计相比,在资源规模相当的情况下,处理速度有了较大的提高。     

面向对称密码领域的可重构阵列设计

通过研究密码系统的特点,提出一种面向对称密码领域的可重构阵列结构.该阵列普遍适用于分组密码和流密码系统,灵活性高.通过配置信息的更新,可以快速动态切换加密功能,切换时间小于20 ns.该结构包含几个16×16的比特阵列和8×8的字节阵列,AES算法实现分组密码的加密速率为640 Mb/s～2.56 Gb/s,DES算法为1.6 Gb/s～3.2 Gb/s,SMS4算法为318 Mb/s～1.6 Gb/s,流密码Geffe的加密速率为400 Mb/s.与文献[1]～[3]相比,SMS4算法的性能有接近2倍的提升.     

AES算法Rijndael的原理、实现和攻击

分组密码Rijndael算法是美国21世纪高级加密标准AES,用于保护联邦政府敏感非机密信息,任何组织、机构和个人可自愿使用。这里详细介绍了它的设计原理、实现方法和目前存在的攻击方法,并指出破译分析的方法原则。     

基于流水线技术的可重构体系结构的研究与设计

目前,FPGA动态可重构技术大部分基于常规的SRAM FPGA平台,其主要的应用还停留在静态系统重构.真正意义上的动态重构系统由于其功能的连续性会受到重构时隙的影响,还处于研究阶段.重构时隙是实现动态重构系统的瓶颈问题.利用流水线技术和可重构技术,提出了一种动态可重构体系结构;采用AES算法对其进行仿真验证.结果表明,该结构有效地解决了动态重构系统中的重构时隙问题,可很好地应用到高速可重构体系结构设计中.     

DES加密算法的高速FPGA实现

DES(数据加密标准)算法是一种应用广泛的分组密码算法.文中在分析算法机理的基础上,对如何用FPGA(现场可编程门阵列)高速实现算法进行了分析和讨论,详细阐述了子密钥生成、S盒设计、流水线设计及子密钥延迟控制的方法,采用Verilog硬件描述语言对算法进行了FPGA仿真,并对算法的性能进行了分析.     

一种可重构的高速流水线乘法器

本文针对在语音、视频等信号处理中出现的变速率信号处理,提出了一种新型的高速高效可重构流水线乘法器电路,并在0.25μm工艺条件下对电路进行了仿真.该电路通过控制流水级数处理变速信号,可有效地节约电路资源约34%,同时可保证频率达1.8GHz的高运算速度.     

密钥可配置的高速3DES芯片设计

介绍了一种密钥可配置的高速(100 MHz)3DES算法的RTL设计及FPGA验证。分析了DES/3DES算法的实现流程;采用流水线结构及并行结构技术,解决了3DES加密算法硬件处理速度问题;并在高时钟频率作用下,实现了关键路径时序不收敛问题。同时,采用基于ROM的密钥可配置的方式,将由真随机数发生器(TRNG)等产生的安全密钥存放在ROM的地址空间内,ROM的部分地址在芯片封装前被固定,为不同客户提供不同安全密钥的初始地址。这不但增强了3DES算法的安全性,而且还实现了密钥的可配置,使其具有更好的商业用途。本设计采用Verilog HDL实现,并在FPGA平台上对数据进行加解密运算,论证了整个设计的正确性。     

一种高速低功耗可重构流水线乘法器

文章针对在语音、视频等多媒体信号处理中出现的可变速率信号，设计了一种新型的高速低功耗可重构流水线乘法器电路，该电路可通过改变流水级数使运算频率与待处理的信号频率相匹配，明显地降低了功耗、提高了效率。并在0．25μm CMOS工艺条件下对该电路性能进行了仿真、分析、比较。在保证最大频率为1．04GHz的高运算速度情况下，最多可节约电路功耗36％。     

一种新型高速低成本可重构FFT处理器结构

文中提出了一种基于FPGA的高速可重构FFT处理器结构.该结构采用精简控制算法[1]可针对从32点到1024点等不同点数数字信号进行FFT处理,并且在Xilinx公司Virtex2p系列FPGA上进行了综合及后仿真.结果表明该可重构结构相比Xilinx IP core而言资源占用减少16%~21%(slice),最高时钟频率提高了10%~30%,输入输出延时减少了56~116个时钟周期,运算效率明显提高,而功耗相当.可适用于低成本高速数字信号处理系统.     

A General Reconfigurable Architecture for the BLAST Algorithm

The process of DNA sequence matching and database search is one of the major problems of the bioinformatics community. Major scientific efforts to address this problem have provided algorithms and software tools for molecular biologists since the early 1970s. At the algorithmic and software level BLAST is by far the most popular tool. It has been developed and continues to be maintained and distributed by the NCBI organization. The BLAST algorithm and software is computationally very intensive and as a result several computer vendors use it as a benchmark. On the other hand no systematic approach for hardware speedup of BLAST and its variants for different query and database size has been reported to date. In this paper we present our architecture that implements the BLAST algorithm for all of its major versions, and for any size of database and query. The system has been fully designed and partially implemented with reconfigurable logic. It consists of software and hardware parts and achieves a speedup of several times up to thousands of times vs general purpose computers.

面向密码算法的异步可重构结构设计

针对FPGA和ASIC在实现密码算法时的不足之处，本文介绍了一种面向密码算法的异步可重构结构。该结构的运算功能由一个可重构单元阵列提供，数据通路由可重构单元之间的相互连接实现，异步通信采用握手信号完成。在分析握手信号传输延时对可重构结构的影响后，文章提出了一种适合该结构的单元信号传输握手控制电路。同时在单元结构中，使用改进的DSDCVS逻辑来设计其运算电路，减小了单元的面积，提高了单元的工作速度。应用实例表明，在实现密码算法时，面向密码算法的异步可重构结构表现出了比FPGA更好的性能。     

可配置的2D空域滤波操作VLSI架构研究

提出了一种可配置的支持红外自动目标识别应用中不同窗口操作的2D空域滤波类操作VLSI架构,从SoC角度考虑能够更好地满足不同的图像处理应用．该架构与已报道的对于该类操作的其他结构解决方案进行比较,新结构具有较高的处理速率．新结构在SIMC0．18μmCMOS工艺下实现,其时钟频率为135Mhz,功耗为52mW,面积约为128．2KGates,峰值处理性能达到6．6GOPs．     

Reconfigurable Filter Coprocessor Architecture for DSP Applications

Digital Signal Processing (DSP) is widely used in high-performance media processing and communication systems. In majority of these applications, critical DSP functions are realized as embedded cores to meet the low-power budget and high computational complexity. Usually these cores are ASICs that cannot be easily retargeted for other similar applications that share certain commonalities. This stretches the design cycle that affects time-to-market constraints. In this paper, we present a reconfigurable high-performance low-power filter coprocessor architecture for DSP applications. The coprocessor architecture, apart from having the performance and power advantage of its ASIC counterpart, can be reconfigured to support a wide variety of filtering computations. Since filtering computations abound in DSP applications, the implementation of this coprocessor architecture can serve as an important embedded hardware IP.     

AES协处理器IP核的设计与实现

用Verilog语言设计了一种AES加密解密协处理器,并利用Xilinx公司的ISE8．2i软件和Spartan-3系列的FPGA对其进行验证和优化。本设计使用了少量的资源达到了比较高的数据吞吐量,形成可重用的AES加密解密协处理器的IP核。     

Domain Specific Reconfigurable Processing Core Architecture for Digital Filtering Applications

This paper presents a reconfigurable processing core architecture targeted for digital filtering applications. The architecture can be configured to execute linear phase FIR filter, DLMS adaptive FIR filter, (I)FFT, and 2D-(I)DCT with high performance and low energy consumption by reducing heavy routing resources used extensively in other reconfigurable architectures. The pipeline depth of the multipliers in the processing core is locally controlled so that power consumption is reduced by minimizing unnecessary register switching is saved. We have shown that the proposed processing core consumes less energy and has better or comparable performance than that of the existing reconfigurable architectures proposed in academia and industry, that have been tailored for these applications. The circuit is designed in 0.35-m CMOS processing technology with 3.3 V supply voltage.Sangjin Hong received the B.S. and M.S. degrees in EECS from the University of California, Berkeley and his Ph.D in EECS from the University of Michigan, Ann Arbor. He is currently with the department of Electrical and Computer Engineering at Stony Brook University - State University of New York. Before joining SUNY, he has worked at Ford Aerospace Corp. Computer Systems Division as a systems engineer. He also worked at Samsung Electronics in Korea as a technical consultant. His current research interests are in the areas of low power reconfigurable SoC design and optimization for DSP and wireless communication systems. He has served as a member of technical committee and track chair for numerous IEEE technical conferences.Shu-Shin Chin was born in Kaohsiung, Taiwan, ROC, in 1974. He received his M.S. and Ph.D degrees in electrical and computer engineering from Stony Brook University—State University of New Yorkin 1999 and 2004, respectively. His research interests include low-power digital circuits, and coarse-grained reconfigurable architectures for high-performance DSP systems.     

高效可配置浮点FFT处理器设计

为了克服高精度浮点FFT处理器具有较大资源开销的设计瓶颈,采用基于单口存储器的FIFO构建共享蝶形结构的R2/22SDF流水可配置结构.采用适合浮点设计的基2/22算法实现流水结构,不仅有利于可配置电路的实现,还能够有效减少复数乘法次数,提高复数乘法器的计算效率.采用双倍数据位宽的单口存储器实现FIFO存储器,有效避免了双口存储器面积和功耗较大的问题.改进的蝶形共享结构实现两级蝶形的合并,解决了单路径延迟反馈流水线结构蝶形单元利用率低的问题.与传统流水线结构FFT处理器设计相比,有效降低了浮点设计中的资源开销,提高了计算单元的利用效率.     

可重构基础网络体系研究与探索

随着网络规模的急剧扩大和新业务的不断涌现,现有互联网在业务适应、传输能力、安全可管可控等方面的弊端日益凸显.为此,业界关于新型互联网体系结构的研究正蓬勃兴起.在此背景下,利用可重构技术在灵活性、可扩展性、适应性等方面的优势探索网络发展新的思路和途径.研究表明,该项目成果为解决网络发展面临的根本问题提供了有效解决途径,并且在国内外相关领域产生了重要影响.