Highly Stretchable,High‐Mobility,Free‐Standing All‐Organic Transistors Modulated by Solid‐State Elastomer Electrolytes

Highly stretchable, high‐mobility, and free‐standing coplanar‐type all‐organic transistors based on deformable solid‐state elastomer electrolytes are demonstrated using ionic thermoplastic polyurethane (i‐TPU), thereby showing high reliability under mechanical stimuli as well as low‐voltage operation. Unlike conventional ionic dielectrics, the i‐TPU electrolyte prepared herein has remarkable characteristics, i.e., a large specific capacitance of 5.5 µF cm^?2, despite the low weight ratio (20 wt%) of the ionic liquid, high transparency, and even stretchability. These i‐TPU‐based organic transistors exhibit a mobility as high as 7.9 cm² V^?1 s^?1, high bendability (R_c, radius of curvature: 7.2 mm), and good stretchability (60% tensile strain). Moreover, they are suitable for low‐voltage operation (V_DS = ?1.0 V, V_GS = ?2.5 V). In addition, the electrical characteristics such as mobility, on‐current, and threshold voltage are maintained even in the concave and convex bending state (bending tensile strain of ≈3.4%), respectively. Finally, free‐standing, fully stretchable, and semi‐transparent coplanar‐type all‐organic transistors can be fabricated by introducing a poly(3,4‐ethylenedioxythiophene):polystyrene sulfonic acid layer as source/drain and gate electrodes, thus achieving low‐voltage operation (V_DS = ?1.5 V, V_GS = ?2.5 V) and an even higher mobility of up to 17.8 cm² V^?1 s^?1. Moreover, these devices withstand stretching up to 80% tensile strain.     

Donor–Acceptor Poly(3‐hexylthiophene)‐block‐Pendent Poly(isoindigo) with Dual Roles of Charge Transporting and Storage Layer for High‐Performance Transistor‐Type Memory Applications

Field‐effect transistor memories usually require one additional charge storage layer between the gate contact and organic semiconductor channel. To avoid such complication, new donor–acceptor rod–coil diblock copolymers (P3HT₄₄‐b‐Piso_n) of poly(3‐hexylthiophene) (P3HT)‐block‐poly(pendent isoindigo) (Piso) are designed, which exhibit high performance transistor memory characteristics without additional charge storage layer. The P3HT and Piso blocks are acted as the charge transporting and storage elements, respectively. The prepared P3HT₄₄‐b‐Piso_n can be self‐assembled into fibrillar‐like nanostructures after the thermal annealing process, confirmed by atomic force microscopy and grazing‐incidence X‐ray diffraction. The lowest‐unoccupied molecular orbital levels of the studied polymers are significantly lowered as the block length of Piso increases, leading to a stronger electron affinity as well as charge storage capability. The field‐effect transistors (FETs) fabricated from P3HT₄₄‐b‐Piso_n possess p‐type mobilities up to 4.56 × 10^?2 cm² V^?1 s^?1, similar to that of the regioregular P3HT. More interestingly, the FET memory devices fabricated from P3HT₄₄‐b‐Piso_n exhibit a memory window ranging from 26 to 79 V by manipulating the block length of Piso, and showed stable long‐term data endurance. The results suggest that the FET characteristics and data storage capability can be effectively tuned simultaneously through donor/acceptor ratio and thin film morphology in the block copolymer system.     

Printed,Flexible, Organic Nano‐Floating‐Gate Memory: Effects of Metal Nanoparticles and Blocking Dielectrics on Memory Characteristics

The effects of using a blocking dielectric layer and metal nanoparticles (NPs) as charge‐trapping sites on the characteristics of organic nano‐floating‐gate memory (NFGM) devices are investigated. High‐performance NFGM devices are fabricated using the n‐type polymer semiconductor, poly{[N,N′‐bis(2‐octyldodecyl)‐naphthalene‐1,4,5,8‐bis(dicarboximide)‐2,6‐diyl]‐alt‐5,5′‐(2,2′‐bithiophene)} (P(NDI2OD‐T2)), and various metal NPs. These NPs are embedded within bilayers of various polymer dielectrics (polystyrene (PS)/poly(4‐vinyl phenol) (PVP) and PS/poly(methyl methacrylate) (PMMA)). The P(NDI2OD‐T2) organic field‐effect transistor (OFET)‐based NFGM devices exhibit high electron mobilities (0.4–0.5 cm² V^?1 s^?1) and reliable non‐volatile memory characteristics, which include a wide memory window (≈52 V), a high on/off‐current ratio (I_on/I_off ≈ 10⁵), and a long extrapolated retention time (>10⁷ s), depending on the choice of the blocking dielectric (PVP or PMMA) and the metal (Au, Ag, Cu, or Al) NPs. The best memory characteristics are achieved in the ones fabricated using PMMA and Au or Ag NPs. The NFGM devices with PMMA and spatially well‐distributed Cu NPs show quasi‐permanent retention characteristics. An inkjet‐printed flexible P(NDI2OD‐T2) 256‐bit transistor memory array (16 × 16 transistors) with Au‐NPs on a polyethylene naphthalate substrate is also fabricated. These memory devices in array exhibit a high I_on/I_off (≈10^{4 ± 0.85}), wide memory window (≈43.5 V ± 8.3 V), and a high degree of reliability.     

Self‐Assembled,Millimeter‐Sized TIPS‐Pentacene Spherulites Grown on Partially Crosslinked Polymer Gate Dielectric

Here, a highly crystalline and self‐assembled 6,13‐bis(triisopropylsilylethynyl) pentacene (TIPS‐Pentacene) thin films formed by simple spin‐coating for the fabrication of high‐performance solution‐processed organic field‐effect transistors (OFETs) are reported. Rather than using semiconducting organic small‐molecule–insulating polymer blends for an active layer of an organic transistor, TIPS‐Pentacene organic semiconductor is separately self‐assembled on partially crosslinked poly‐4‐vinylphenol:poly(melamine‐co‐formaldehyde) (PVP:PMF) gate dielectric, which results in a vertically segregated semiconductor‐dielectric film with millimeter‐sized spherulite‐crystalline morphology of TIPS‐Pentacene. The structural and electrical properties of TIPS‐Pentacene/PVP:PMF films have been studied using a combination of polarized optical microscopy, atomic force microscopy, 2D‐grazing incidence wide‐angle X‐ray scattering, and secondary ion mass spectrometry. It is finally demonstrated a high‐performance OFETs with a maximum hole mobility of 3.40 cm² V^?1 s^?1 which is, to the best of our knowledge, one of the highest mobility values for TIPS‐Pentacene OFETs fabricated using a conventional solution process. It is expected that this new deposition method would be applicable to other small molecular semiconductor–curable polymer gate dielectric systems for high‐performance organic electronic applications.     

Nanoparticle-dispersed high-k organic–inorganic hybrid dielectrics for organic thin-film transistors

We fabricated solution-processable thin gate dielectrics for organic thin-film transistors (OTFTs) using an organosiloxane-based organic–inorganic hybrid material. The electrical characteristics of the hybrid dielectrics were controlled by adjusting the zirconium alkoxide concentration. Microstructural observation and chemical analysis allow us to determine the influence of microstructure and composition on the electrical properties of the hybrid dielectrics. Our hybrid material is composed of three phases: ZrO₂, ZrSiO₄, and organosiloxane. OTFTs based on the hybrid dielectrics exhibited better electrical performance compared to transistors based on poly(4-vinylphenol) (PVP). Using a dielectric with a higher dielectric constant and fewer hydroxyl groups enabled us to fabricate a transistor with a lower off-current, higher on/off current ratio, and lower threshold voltage.     

Controllable Shifts in Threshold Voltage of Top‐Gate Polymer Field‐Effect Transistors for Applications in Organic Nano Floating Gate Memory

Organic field‐effect transistor (FET) memory is an emerging technology with the potential to realize light‐weight, low‐cost, flexible charge storage media. Here, solution‐processed poly[9,9‐dioctylfluorenyl‐2,7‐diyl]‐co‐(bithiophene)] (F8T2) nano floating gate memory (NFGM) with a top‐gate/bottom‐contact device configuration is reported. A reversible shift in the threshold voltage (V_Th) and reliable memory characteristics was achieved by the incorporation of thin Au nanoparticles (NPs) as charge storage sites for negative charges (electrons) at the interface between polystyrene and cross‐linked poly(4‐vinylphenol). The F8T2 NFGM showed relatively high field‐effect mobility (µ_FET) (0.02 cm² V^?1 s^?1) for an amorphous semiconducting polymer with a large memory window (ca. 30 V), a high on/off ratio (more than 10⁴) during writing and erasing with an operation voltage of 80 V of gate bias in a relatively short timescale (less than 1 s), and a retention time of a few hours. This top‐gated polymer NFGM could be used as an organic transistor memory element for organic flash memory.     

Fully Transparent Non‐volatile Memory Thin‐Film Transistors Using an Organic Ferroelectric and Oxide Semiconductor Below 200 °C

A fully transparent non‐volatile memory thin‐film transistor (T‐MTFT) is demonstrated. The gate stack is composed of organic ferroelectric poly(vinylidene fluoride‐trifluoroethylene) [P(VDF‐TrFE)] and oxide semiconducting Al‐Zn‐Sn‐O (AZTO) layers, in which thin Al₂O₃ is introduced between two layers. All the fabrication processes are performed below 200 °C on the glass substrate. The transmittance of the fabricated device was more than 90% at the wavelength of 550 nm. The memory window obtained in the T‐MTFT was 7.5 V with a gate voltage sweep of ?10 to 10 V, and it was still 1.8 V even with a lower voltage sweep of ?6 to 6 V. The field‐effect mobility, subthreshold swing, on/off ratio, and gate leakage currents were obtained to be 32.2 cm² V^?1 s^?1, 0.45 V decade^?1, 10⁸, and 10^?13 A, respectively. All these characteristics correspond to the best performances among all types of non‐volatile memory transistors reported so far, although the programming speed and retention time should be more improved.     

Solution‐Processed Small‐Molecule Bulk Heterojunction Ambipolar Transistors

Solution‐processed small‐molecule bulk heterojunction (BHJ) ambipolar organic thin‐film transistors are fabricated based on a combination of [2‐phenylbenzo[d,d']thieno[3,2‐b;4,5‐b']dithiophene (P‐BTDT) : 2‐(4‐n‐octylphenyl)benzo[d,d ']thieno[3,2‐b;4,5‐b']dithiophene (OP‐BTDT)] and C₆₀. Treating high electrical performance vacuum‐deposited P‐BTDT organic semiconductors with a newly developed solution‐processed organic semiconductor material, OP‐BTDT, in an optimized ratio yields a solution‐processed p‐channel organic semiconductor blend with carrier mobility as high as 0.65 cm² V^?1 s^?1. An optimized blending of P‐BTDT:OP‐BTDT with the n‐channel semiconductor, C₆₀, results in a BHJ ambipolar transistor with balanced carrier mobilities for holes and electrons of 0.03 and 0.02 cm² V^?1 s^?1, respectively. Furthermore, a complementary‐like inverter composed of two ambipolar thin‐film transistors is demonstrated, which achieves a gain of 115.     

Nonvolatile Ferroelectric P(VDF‐TrFE) Memory Transistors Based on Inkjet‐Printed Organic Semiconductor

Nonvolatile ferroelectric poly(vinylidene fluoride‐co‐trifluoroethylene) memory based on an organic thin‐film transistor with inkjet‐printed dodecyl‐substituted thienylenevinylene‐thiophene copolymer (PC12TV12T) as the active layer is developed. The memory window is 4.5 V with a gate voltage sweep of ?12.5 V to 12.5 V. The field effect mobility, on/off ratio, and gate leakage current are 0.1 cm²/Vs, 10⁵, and 10^?10 A, respectively. Although the retention behaviors should be improved and optimized, the obtained characteristics are very promising for future flexible electronics.     

Physicochemically Stable Polymer‐Coupled Oxide Dielectrics for Multipurpose Organic Electronic Applications

A chemically coupled polymer layer is introduced onto inorganic oxide dielectrics from a dilute chlorosilane‐terminated polystyrene (PS) solution. As a result of this surface modification, hydrophilic‐oxide dielectrics gain hydrophobic, physicochemically stable properties. On such PS‐coupled SiO₂ or AlO_x dielectrics, various vacuum‐ and solution‐processable organic semiconductors can develop highly ordered crystalline structures that provide higher field‐effect mobilities (μ_FETs) than other surface‐modified systems, and negligible hysteresis in organic field‐effect transistors (OFETs). In particular, the use of PS‐coupled AlO_x nanodielectrics enables a solution‐processable triethylsilylethynyl anthradithiophene OFET to operate with μ_FET ～ 1.26 cm² V^?1 s^?1 at a gate voltage below –1 V. In addition, a complementary metal‐oxide semiconductor‐like organic inverter with a high voltage gain of approximately 32 was successfully fabricated on a PS‐coupled SiO₂ dielectric.     

On the Relation between Morphology and FET Mobility of Poly(3‐alkylthiophene)s at the Polymer/SiO2 and Polymer/Air Interface

The influence of the interface of the dielectric SiO₂ on the performance of bottom‐contact, bottom‐gate poly(3‐alkylthiophene) (P3AT) field‐effect transistors (FETs) is investigated. In particular, the operation of transistors where the active polythiophene layer is directly spin‐coated from chlorobenzene (CB) onto the bare SiO₂ dielectric is compared to those where the active layer is first spin‐coated then laminated via a wet transfer process such that the film/air interface of this film contacts the SiO₂ surface. While an apparent alkyl side‐chain length dependent mobility is observed for films directly spin‐coated onto the SiO₂ dielectric (with mobilities of ≈10^?3 cm² V^?1 s^?1 or less) for laminated films mobilities of 0.14 ± 0.03 cm² V^?1 s^?1 independent of alkyl chain length are recorded. Surface‐sensitive near edge X‐ray absorption fine structure (NEXAFS) spectroscopy measurements indicate a strong out‐of‐plane orientation of the polymer backbone at the original air/film interface while much lower average tilt angles of the polymer backbone are observed at the SiO₂/film interface. A comparison with NEXAFS on crystalline P3AT nanofibers, as well as molecular mechanics and electronic structure calculations on ideal P3AT crystals suggest a close to crystalline polymer organization at the P3AT/air interface of films from CB. These results emphasize the negative influence of wrongly oriented polymer on charge carrier mobility and highlight the potential of the polymer/air interface in achieving excellent “out‐of‐plane” orientation and high FET mobilities.     

Ultrathin,Organic, Semiconductor/Polymer Blends by Scanning Corona‐Discharge Coating for High‐Performance Organic Thin‐Film Transistors

A new thin‐film coating process, scanning corona‐discharge coating (SCDC), to fabricate ultrathin tri‐isopropylsilylethynyl pentacene (TIPS‐PEN)/amorphous‐polymer blend layers suitable for high‐performance, bottom‐gate, organic thin‐film transistors (OTFTs) is described. The method is based on utilizing the electrodynamic flow of gas molecules that are corona‐discharged at a sharp metallic tip under a high voltage and subsequently directed towards a bottom electrode. With the static movement of the bottom electrode, on which a blend solution of TIPS‐PEN and an amorphous polymer is deposited, SCDC provides an efficient route to produce uniform blend films with thicknesses of less than one hundred nanometers, in which the TIPS‐PEN and the amorphous polymer are vertically phase‐separated into a bilayered structure with a single‐crystalline nature of the TIPS‐PEN. A bottom‐gate field‐effect transistor with a blend layer of TIPS‐PEN/polystyrene (PS) (90/10 wt%) operated at ambient conditions, for example, indeed exhibits a highly reliable device performance with a field‐effect mobility of approximately 0.23 cm² V^?1 s^?1: two orders of magnitude greater than that of a spin‐coated blend film. SCDC also turns out to be applicable to other amorphous polymers, such as poly(α‐methyl styrene) and poly(methyl methacrylate) and, readily combined with the conventional transfer‐printing technique, gives rise to micropatterned arrays of TIPS‐PEN/polymer films.     

Novel organic-perovskite hybrid structure forward photo field effect transistor

To enhance photosensitive performances for an organic thin film transistor, we fabricated a hybrid structured transistor with C8BTBT film as organic active layer, onto which, a CH₃NH₃PbI₃ layer was formed through the vacuum deposition. The phototransistor showed the best photo responsivity as high as 33 A/W, much higher than most other organic based thin film transistors, in addition to keeping fast response time and well gate tunable ability. The working mechanism were further investigated with the temperature dependence measurement. The organic-perovskite hybrid transistor may open up a path way for the optimization of organic photo sensitive transistors.     

Acrylate-based nanocomposite zirconium-dispersed polymer dielectric for flexible oxide thin-film transistors with a curvature radius of 2 mm

Novel hybrid dielectric film is synthesized at a low temperature of 150 °C using a solution process. Zirconium acrylate (ZrA) and poly(methyl methacrylate) (PMMA) comprise the inorganic and organic components, respectively. The acrylate-based molecular structure of both ingredients allows the facile formation of hybrid ZrA/PMMA dielectric film with neither additional coupling agent nor ultraviolet photon irradiation. The high quality of the hybrid ZrA/PMMA dielectric film is confirmed by its high dielectric constant of 5.5 and low leakage current density of 1.7 × 10⁻⁸ A/cm² at the electric field of 1 MV/cm. The indium gallium tin oxide (IGTO) transistors with the optimal ZrA/PMMA gate insulator layer are fabricated on the polyimide substrate at the maximum high temperature of 150 °C. They exhibit hysteresis-free high performance with high carrier mobility of 24.3 cm²V⁻¹s⁻¹, gate swing of 0.61 V/decade and I_ON/OFF ratio of 4 × 10⁶. Owing to the intrinsic deformability of hybrid dielectric film, these transistors maintained electrical performance after 100 cycles of mechanical bending to the extremely small radius of curvature of 2 mm.     

Artificial Synapse Based on Oxygen Vacancy Migration in Ferroelectric-Like C-Axis-Aligned Crystalline InGaSnO Semiconductor Thin-Film Transistors for Highly Integrated Neuromorphic Electronics

Artificial synapses are a key component of neuromorphic computing systems. To achieve high-performance neuromorphic computing ability, a huge number of artificial synapses should be integrated because the human brain has a huge number of synapses (≈10¹⁵). In this study, a coplanar synaptic, thin-film transistor (TFT) made of c-axis-aligned crystalline indium gallium tin oxide (CAAC–IGTO) is developed. The electrical characteristics of the biological synapses such as inhibitory postsynaptic current (IPSC), paired-pulse depression (PPD), short-term plasticity (STP), and long-term plasticity at V_DS = 0.1 V, are demonstrated. The measured synaptic behavior can be explained by the migration of positively charged oxygen vacancies (V_o⁺/V_o⁺⁺) in the CAAC–IGTO layer. The mechanism of implementing synaptic behavior is completely new, compared to previous reports using electrolytes or ferroelectric gate insulators. The advantage of this device is to use conventional gate insulators such as SiO₂ for synaptic behavior. Previous studies use chitosan, Ta₂O₃, SiO₂ nanoparticles , Gd₂O₃, and HfZrO_x for gate insulators, which cannot be used for high integration of synaptic devices. The metal–oxide TFTs, widely used in the display industry, can be applied to the synaptic transistors. Therefore, CAAC–IGTO synaptic TFT can be a good candidate for application as an artificial synapse for highly integrated neuromorphic chips.     

Water‐Induced Scandium Oxide Dielectric for Low‐Operating Voltage n‐ and p‐Type Metal‐Oxide Thin‐Film Transistors

Solution‐processed metal‐oxide thin films based on high dielectric constant (k) materials have been extensively studied for use in low‐cost and high‐performance thin‐film transistors (TFTs). Here, scandium oxide (ScO_x) is fabricated as a TFT dielectric with excellent electrical properties using a novel water‐inducement method. The thin films are annealed at various temperatures and characterized by using X‐ray diffraction, atomic‐force microscopy, X‐ray photoelectron spectroscopy, optical spectroscopy, and a series of electrical measurements. The optimized ScO_x thin film exhibits a low‐leakage current density of 0.2 nA cm^?2 at 2 MV cm^?1, a large areal capacitance of 460 nF cm^?2 at 20 Hz and a permittivity of 12.1. To verify the possible applications of ScO_x thin films as the gate dielectric in complementary metal oxide semiconductor (CMOS) electronics, they were integrated in both n‐type InZnO (IZO) and p‐type CuO TFTs for testing. The water‐induced full oxide IZO/ScO_x TFTs exhibit an excellent performance, including a high electron mobility of 27.7 cm² V^?1 s^?1, a large current ratio (I_on/I_off) of 2.7 × 10⁷ and high stability. Moreover, as far as we know it is the first time that solution‐processed p‐type oxide TFTs based on a high‐k dielectric are achieved. The as‐fabricated p‐type CuO/ScO_x TFTs exhibit a large I_on/I_off of around 10⁵ and a hole mobility of 0.8 cm² V^?1 at an operating voltage of 3 V. To the best of our knowledge, these electrical parameters are among the highest performances for solution‐processed p‐type TFTs, which represents a great step towards the achievement of low‐cost, all‐oxide, and low‐power consumption CMOS logics.     

Solution‐Deposited Zinc Oxide and Zinc Oxide/Pentacene Bilayer Transistors: High Mobility n‐Channel,Ambipolar, and Nonvolatile Devices

A solution processed n‐channel zinc oxide (ZnO) field effect transistor (FET) was fabricated by simple dip coating and subsequent heat treatment of a zinc acetate film. The field effect mobility of electrons depends on ZnO grain size, controlled by changing the number of coatings and zinc acetate solution concentration. The highest electron mobility achieved by this method is 7.2 cm² V^?1 s^?1 with On/Off ratio of 70. This electron mobility is higher than for the most recently reported solution processed ZnO transistor. We also fabricated bilayer transistors where the first layer is ZnO, and the second layer is pentacene, a p‐channel organic which is deposited by thermal evaporation. By changing the ZnO grain size (or thickness) this type of bilayer transistor shows p‐channel, ambipolar and n‐channel behavior. For the ambipolar transistor, well balanced electron and hole mobilities are 7.6 × 10^?3 and 6.3 × 10^?3 cm² V^?1 s^?1 respectively. When the ZnO layer is very thin, the transistor shows p‐channel behavior with very high reversible hysteresis. The nonvolatile tuning function of this transistor was investigated.     

Low‐Temperature‐Processed Printed Metal Oxide Transistors Based on Pure Aqueous Inks

Additive patterning of transparent conducting metal oxides at low temperatures is a critical step in realizing low‐cost transparent electronics for display technology and photovoltaics. In this work, inkjet‐printed metal oxide transistors based on pure aqueous chemistries are presented. These inks readily convert to functional thin films at lower processing temperatures (T ≤ 250 °C) relative to organic solvent‐based oxide inks, facilitating the fabrication of high‐performance transistors with both inkjet‐printed transparent electrodes of aluminum‐doped cadmium oxide (ACO) and semiconductor (InO_x ). The intrinsic fluid properties of these water‐based solutions enable the printing of fine features with coffee‐ring free line profiles and smoother line edges than those formed from organic solvent‐based inks. The influence of low‐temperature annealing on the optical, electrical, and crystallographic properties of the ACO electrodes is investigated, as well as the role of aluminum doping in improving these properties. Finally, the all‐aqueous‐printed thin film transistors (TFTs) with inkjet‐patterned semiconductor (InO_x ) and source/drain (ACO) layers are characterized, which show ideal low contact resistance (R _c < 160 Ω cm) and competitive transistor performance (µ _lin up to 19 cm² V^?1 s^?1, Subthreshold Slope (SS) ≤150 mV dec^?1) with only low‐temperature processing (T ≤ 250 °C).     

Single‐Crystalline p‐Type Zn3As2 Nanowires for Field‐Effect Transistors and Visible‐Light Photodetectors on Rigid and Flexible Substrates

Zn₃As₂ is an important p‐type semiconductor with the merit of high effective mobility. The synthesis of single‐crystalline Zn₃As₂ nanowires (NWs) via a simple chemical vapor deposition method is reported. High‐performance single Zn₃As₂ NW field‐effect transistors (FETs) on rigid SiO₂/Si substrates and visible‐light photodetectors on rigid and flexible substrates are fabricated and studied. As‐fabricated single‐NW FETs exhibit typical p‐type transistor characteristics with the features of high mobility (305.5 cm² V^?1 s^?1) and a high I_on/I_off ratio (10⁵). Single‐NW photodetectors on SiO₂/Si substrate show good sensitivity to visible light. Using the contact printing process, large‐scale ordered Zn₃As₂ NW arrays are successfully assembled on SiO₂/Si substrate to prepare NW thin‐film transistors and photodetectors. The NW‐array photodetectors on rigid SiO₂/Si substrate and flexible PET substrate exhibit enhanced optoelectronic performance compared with the single‐NW devices. The results reveal that the p‐type Zn₃As₂ NWs have important applications in future electronic and optoelectronic devices.     

Implementation of Low‐Power Electronic Devices Using Solution‐Processed Tantalum Pentoxide Dielectric

The development of solution‐processed field effect transistors (FETs) based on organic and hybrid materials over the past two decades has demonstrated the incredible potential in these technologies. However, solution processed FETs generally require impracticably high voltages to switch on and off, which precludes their application in low‐power devices and prevent their integration with standard logic circuitry. Here, a universal and environmentally benign solution‐processing method for the preparation of Ta₂O₅, HfO₂ and ZrO₂ amorphous dielectric thin films is demonstrated. High mobility CdS FETs are fabricated on such high‐κ dielectric substrates entirely via solution‐processing. The highest mobility, 2.97 cm² V^?1 s^?1 is achieved in the device with Ta₂O₅ dielectric with a low threshold voltage of 1.00 V, which is higher than the mobility of the reference CdS FET with SiO₂ dielectric with an order of magnitude decrease in threshold voltage as well. Because these FETs can be operated at less than 5 V, they may potentially be integrated with existing logic and display circuitry without significant signal amplification. This report demonstrates high‐mobility FETs using solution‐processed Ta₂O₅ dielectrics with drastically reduced power consumption; ≈95% reduction compared to that of the device with a conventional SiO₂ gate dielectric.