Numerical simulation and comparison of Si BJTs andSi1-xGex HBTs

Using the Monte Carlo method for the solution of the Boltzmann transport equation, the authors analyze the low-field carrier mobilities of strained layer and bulk Si and Si_1-xGe_x alloys. Strained alloy layers exhibit higher low-field mobility compared with bulk Si at doping levels >10¹⁸ cm^-3 and for a Ge mole fraction x⩽0.2, while the unstrained alloy bulk low-field mobility is always lower than that of Si for any doping level or mole fraction. These mobilities are then used in a two-dimensional drift-diffusion equation solver to simulate the performance of Si BJTs (bipolar junction transistors) and Si_1-xGe_x HBTs (heterojunction bipolar transistors). The substitution of a Si_0.8 Ge_0.2 layer for the base region leads to a significant improvement in current gain, turn-on voltage, and high-frequency performance. Maximum unity current gain frequency f_T increases two times over that of an Si BJT if the bulk alloy mobility is used for the alloy base layer; it increases three times if strained-layer mobility is used. Maximum frequency of oscillation also improves, but not as dramatically as f_T     

High performance Si/Si1-xGex resonanttunneling diodes

Resonant tunneling diodes (RTDs) with strained i-Si_0.4Ge_0.6 potential barriers and a strained i-Si quantum well, all on a relaxed Si_0.8Ge_0.2 virtual substrate were successfully grown by ultra high vacuum compatible chemical vapor deposition and fabricated using standard Si processing methods. A large peak to valley current ratio of 2.9 and a peak current density of 4.3 kA/cm² at room temperature were recorded from pulsed and continuous dc current-voltage measurements, the highest reported values to date for Si/Si_1-xGe_x RTDs. These dc figures of merit and material system render such structures suitable and highly compatible with present high speed and low power Si/Si_1-xGe_x heterojunction field effect transistor based integrated circuits     

The scaled performance of Si/Si1-xGexresonant tunneling diodes

Small area resonant tunneling diodes (RTDs) with strained Si_0.4Ge_0.6 potential barriers and a strained Si quantum well grown on a relaxed Si_0.8Ge_0.2 virtual substrate were fabricated and characterized. A room temperature peak current density (J_P) of 282 kA/cm² with a peak to valley current ratio (PVCR) of 2.43 were recorded for a 5×5 μm ² sample, the highest values reported to date for Si/Si_1-xGe_x RTDs. Scaling of the device size demonstrated a decrease in J_P proportional to an increase in the lateral area of the tunnel junctions, whereas the PVCR remained approximately constant. This observation suggests that the dc behavior of such Si/Si_1-xGe_x RTD design is presently limited by thermal effects     

Si/Si1-x-yGexCy/Si heterojunctionbipolar transistors

We report the first Si/Si_1-x-yGe_xC_y /Si n-p-n heterojunction bipolar transistors and the first electrical bandgap measurements of strained Si_1-x-yGe_x C_y on Si (100) substrates. The carbon compositions were measured by the shift between the Si_1-x-yGe_xC_y and Si_1-xGe_x X-ray diffraction peaks. The temperature dependence of the HBT collector current demonstrates that carbon causes a shift in bandgap of +26 meV/%C for germanium fractions of x=0.2 and x=0.25. These results show that carbon reduces the strain in Si_1-x Ge_x at a faster rate than it increases the bandgap (compared to reducing x in Si_1-xGe_x), so that a Si _1-x-yGe_xC_y film will have less strain than a Si_1-xGe_x film with the same bandgap     

Electrical determination of bandgap narrowing in bipolartransistors with epitaxial Si, epitaxial Si1-xGex,and ion implanted bases

The apparent bandgap narrowing in bipolar transistors with epitaxial Si, epitaxial SiGe and ion implanted bases is measured from the temperature dependence of the collector current density J_c(T). A graph of InJ_c(T)/J_o(T) as a function of reciprocal temperature is plotted, and the apparent bandgap narrowing obtained from the slope. For epitaxial base transistors, in which the boron base profiles are abrupt, a linear J_c(T)/J _o(T) characteristic is obtained, which allows the unambiguous determination of the apparent bandgap narrowing. The measured values for epitaxial Si bases are in good agreement with the theoretical model of Klaassen over a range of base doping concentrations. For Si_0.88 Ge_0.12 and Si_0.87Ge_0.13 epitaxial base heterojunction bipolar transistors (HBT's), values of bandgap narrowing of 119 and 121 meV are obtained due to the presence of the Ge, which can be compared with theoretical values of 111 and 118 meV. For the implanted base transistor, the J_c(T)/J_o(T) characteristic is not linear, and its slope is larger at high temperatures than at low. This behaviour is explained by the presence of a tail on the ion implanted profile, which dominates the Gummel number of the transistor at low temperatures     

Si/Si1-xGex heterojunction bipolartransistors produced by limited reaction processing

Si/Si_1-xGe_x heterojunction transistors (HBTs) fabricated by a chemical vapor deposition (CVD) technique are reported. A rapid thermal CVD limited-reaction processing (LRP) technique was used for the in situ growth of all three device layers, including a 20-mm Si_1-xGe_x layer in the base. The highest current gains observed (β=400) were for a Si/Si_1-x Ge_x HBT with a base doping of 7×10¹⁸ cm^-3 near the junction and a shallow arsenic implant to form ohmic contacts and increase current gain. Ideal base currents were observed for over six decades of current and the collector current remained ideal for nearly nine current decades starting at 1 pA. The bandgap difference between a p-type Si layer doped to 5×10¹⁷ cm^-3 and the Si_1-xGe_x(x=0.31) base measured 0.27 eV. This value was deduced from the measurements of the temperature dependence of the base current and is in good agreement with published calculations for strained Si_1-xGe_x layers on Si     

Fabrication of thin film transistors using a Si/Si1-xGex/Si triple layer film on a SiO2 substrate

A novel approach that can reduce the thermal budget in the fabrication of thin film transistors (TFTs) using a Si/Si_0.7Ge_0.3/Si triple film as an active layer was proposed. The crystallization behavior of the triple film was described and device characteristics of Si/Si_0.7Ge_0.3 /Si TFTs were compared with those of Si TFTs and of SiGe TFTs. The triple film was completely crystallized only after a 25-h anneal at 550°C. N-channel polycrystalline Si/Si_0.7Ge_0.3/Si TFTs had a field-effect mobility of 57.9 cm²/Vs and an I_on/I_off ratio of 5.7×10⁶. This technique provides not only a shorter time processing capability than Si TFT's technology but also superior device characteristics compared to SiGe TFTs     

Laser Annealing of Amorphous Germanium on Silicon–Germanium Source/Drain for Strain and Performance Enhancement in pMOSFETs

We report the first demonstration of a novel germanium-enrichment process for forming a silicon-germanium (SiGe) source/drain (S/D) stressor with a high Ge content. The process involves laser-induced local melting and intermixing of a Ge layer with an underlying Si_0.8Ge_0.2 S/D region, leading to a graded SiGe S/D stressor with a significant increase in the peak Ge content. Various laser fluences were investigated for the laser annealing process. The process is then successfully integrated in a device fabrication flow, forming strained silicon-on-insulator p-channel field-effect transistors (p-FETs) with a high Ge content in SiGe S/D. A drive current enhancement of ~ 12% was achieved with this process, as compared to a strained p-FET with Si_0.8Ge_0.2 S/D p-FETs. The I _Dsat enhancement, primarily attributed to strain-induced mobility improvement, is found to increase with decreasing gate lengths.     

DC and RF performance of 0.25 μm p-type SiGe MODFET

The DC and RF performance of a 0.25 μm gate-length p-type SiGe modulation-doped field-effect transistor (MODFET) is reported. The hole channel consists of compressively strained Si_0.3Ge_0.7 layer grown on a relaxed Si_0.7Ge_0.3 buffer on a Si substrate. The combination of high-hole mobility, low-gate leakage current, and improved ohmic contact metallization results in an enhancement of the DC and RF performance. A maximum extrinsic transconductance (g(m_ext)) of 230 mS/mm was measured. A unity current gain cut-off frequency (fT) of 24 GHz and a maximum frequency of oscillation (f_max) of 37 GHz were obtained for these devices     

16 Gbit/s multiplexer IC using double mesa Si/SiGe heterojunction bipolar transistors

A double mesa Si/SiGe heterojunction bipolar transistor (HBT) was developed for application in integrated circuits. The HBT is characterised by an emitter base heterojunction and consequently by a high base doping concentration. By using these transistors an integrated digital circuit, a multiplexer, was implemented. The measured bit rate of this first Si/SiGe HBT circuit was 16 Gbit/s.<>     

Design of Si/SiGe heterojunction complementarymetal-oxide-semiconductor transistors

An optimized Si/SiGe heterostructure for complementary metal-oxide semiconductor (CMOS) transistor operation is presented. Unlike previous proposals, the design is planar and avoids inversion of the Si layer at the oxide interface. The design consists of a relaxed Si_0.7Ge _0.3 buffer, a strained Si quantum well (the electron channel), and a strained S_1-xGe_x (0.7>x>0.5) quantum well (the hole channel). The channel charge distribution is predicted using a 1-D analytical model and quantum mechanical solutions. Transport is modeled using 2-D drift-diffusion and hydrodynamic numerical simulations. An almost symmetric performance of p- and n-transistors with good short-channel behavior is predicted. Simulated ring oscillators show a 4- to 6-fold reduction in power-delay product compared to bulk Si CMOS at the 0.2-μm channel length generation     

0.3 dB minimum noise figure at 2.5 GHz of 0.13 μm Si/Si0.58Ge0.42 n-MODFETs

RF and microwave noise performances of strained Si/Si_0.58 Ge_0.42 n-MODFETs are presented for the first time. The 0.13 μm gate devices have de-embedded f_T=49 GHz, f_max =70 GHz and a record intrinsic g_m=700 mS/mm. A de-embedded minimum noise figure NF_min=0.3 dB with a 41 Ω noise resistance R_n and a 19 dB associated gain G_ass are obtained at 2.5 GHz, while NF_min=2.0 dB with G_ass=10 dB at 18 GHz. The noise parameters measured up to 18 GHz and from 10 to 180 mA/mm with high gain and low power dissipation show the potential of SiGe MODFETs for mobile communications     

Fabrication and analysis of deep submicron strained-Si n-MOSFET's

Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si_0.8Ge_0.2 heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 μm) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects     

High Mobility Strained Ge pMOSFETs With High-κ/Metal Gate

Compressively strained Ge long channel ring-type pMOSFETs with high-kappa Si/SiO₂/HfO₂/TiN gate stacks are fabricated on Si_0.2Ge_0.8 virtual substrates. Effective oxide thickness is approximately 1.4 nm with low gate leakage current. A peak hole mobility of 640 cm²/ Vldrs and up to a four times enhancement over the Si/SiO₂ universal curve are observed. Parasitic conduction within the Si-cap layers degrades the mobility at large vertical fields, although up to a 2.5 times enhancement over universal remains at a field of 0.9 MV/cm.     

A deep submicron Si1-xGex/Si vertical PMOSFETfabricated by Ge ion implantation

We report a deep submicron vertical PMOS transistor using strained Si_1-xGe_x channel formed by Ge ion implantation and solid phase epitaxy. These vertical structure Si_1-xGe_x /Si transistors can be fabricated with channel lengths below 0.2 μm without using any sophisticated lithographic techniques and with a regular MOS process. The enhancement of hole mobility in a direction normal to the growth plane of strained Si_1-xGe_x over that of bulk Si has been experimentally demonstrated for the first time using this vertical MOSFET. The drain current of these vertical MOS devices has been found to be enhanced by as much as 100% over control Si devices. The presence of the built-in electric field due to a graded SiGe channel has also been found to be effective in further enhancement of the drive current in implanted-channel MOSFET's     

Strain-Engineered Si/SiGe Resonant Interband Tunneling Diodes Grown on $hbox{Si}_{0.8}hbox{Ge}_{0.2}$ Virtual Substrates With Strained Si Cladding Layers

Strain-engineered Si-based resonant interband tunneling diodes grown on commercially available Si_0.8Ge_0.2 virtual substrates were developed that address issues of P dopant diffusion and electron confinement. Strain-induced band offsets were effectively utilized to improve tunnel diode performance versus the control device, particularly the peak-to-valley current ratio (PVCR). By growing tensilely strained Si layers cladding the P delta-doping plane, the quantum well formed by the P delta-doping plane is deepened, which concurrently increases the optimal annealing temperature from 800 to 835 and facilitates an increase in the PVCR up to 1.8times from 1.6 to 2.8 at room temperature, which is significantly better than previous results on strained substrates.     

Thickness Dependence of Hole Mobility in Ultrathin SiGe-Channel p-MOSFETs

A fundamental understanding of the mechanisms responsible for the dependence of hole mobility on SiGe channel layer thickness is presented for channel thicknesses down to 1.8 nm. This understanding is critical to the design of strained SiGe p-MOSFETs, as lattice mismatch limits the thickness of SiGe that can be grown on Si and as Ge outdiffusion during processing reduces the Ge fraction. Temperature-dependent measurements are used to extract the phonon-limited mobility as a function of SiGe channel thickness for strained Si_0.57Ge_0.43 heterostructures on bulk Si. The hole mobility is shown to degrade significantly for channel thickness below 4 nm due to a combination of phonon and interface scattering. Due to the finite nature of the quantum-well barrier, SiGe film thickness fluctuation scattering is not significant in this structure for channel thickness greater than 2.8 nm.     

A super self-aligned selectively grown SiGe base (SSSB) bipolartransistor fabricated by cold-wall type UHV/CVD technology

A novel selective epitaxial growth (SEG) technology for fabricating the intrinsic SiGe-base layer of a double poly-Si self-aligned bipolar transistor has been developed. Selectively grown Si and SiGe-alloy layers were obtained by using Si₂H₆+GeH₄+Cl₂+B₂ H₆ gas system using cold-wall ultra-high vacuum (UHV)/CVD. We have optimized the growth conditions so that Si or SiGe grows selectively against Si₃N₄ both on single crystalline Si and on poly-Si of a structure consisting of a poly-Si layer overhanging the single crystalline Si substrate. The selective growth is maintained until the growth from the bottom Si and the top poly-Si coalesce. This selective growth permits a novel emitter-base self-aligned transistor which we call a super self-aligned selectively grown SiGe base (SSSB) HBT     

Novel SOI p-channel MOSFETs with higher strain in si channel usingdouble SiGe heterostructures

We have studied p-channel advanced SOI MOSFETs using double SiGe heterostructures fabricated by the combination of SIMOX and high-quality strained-Si/SiGe regrowth technologies, in order to introduce higher strain in Si channel. It was revealed that this double SiGe structure of second Si_0.82Ge_0.18Si_0.93Ge_0.07 allows the second SiGe layer to relax by about 70%, because of the elastic energy balance between the second and the first-SiGe layers. As a result, the strain of Si layer on this double SiGe structure becomes higher than that of the single SiGe structure. Strained SOI p-MOSFETs using the double layer SiGe structure exhibited higher hole mobility than that of strained-SOI MOSFETs with single Si_0.9Ge_0.1 structure. The hole mobility enhancement of 30% and 45% was achieved in the strained-SOI MOSFETs with double SiGe structures, compared to that of the universal curve and the control-SOI MOSFETs, respectively     

SiGe/SiHBT异质界面与pn结界面的相对位移的影响

从模拟和实验两方面研究了SiGe/Si HBT发射结中pn结界面和SiGe/Si界面的相对位置对器件的电流增益和频率特性的影响.发现两界面偏离时器件性能会变差.尤其是当pn结位于SiGe/Si界面之前仅几十?就足以产生相当高的电子寄生势垒,严重恶化器件的性能.据此分析了基区B杂质的偏析和外扩对器件的影响以及SiGe/Si隔离层的作用.