Optimal superior-order curvature-corrected voltage reference based on the weight difference of gate-source voltages

A new curvature-correction technique for improving the temperature behavior of a CMOS voltage reference will be presented. The reducing of the temperature coefficient for the reference voltage will be realized compensating the nonlinear temperature dependence of the gate-source voltage for a MOS transistor working in weak inversion with the difference between two gate-source voltages. These MOS transistors are biased at drain currents with different temperature dependencies (PTAT and PTAT ^α, respectively), α parameter being selected to the optimal value for the implementing technology. The PTAT voltage generator will be designed using an original Offset Voltage Follower block, with the advantage of a reduced silicon occupied area as a result of replacing classical resistors by MOS active devices. SPICE simulation reports TC = 1.95 ppm/K for an extended temperature range, 273 K < T < 363 K, without considering the parameters spread. The circuit is compatible with low-power low-voltage designed, having a maximal power consumption of 0.4 μW for a minimal supply voltage of 1.1 V.     

Low-voltage,low-power Vt independent voltage reference for bio-implants

Biomedical electronics trends focus mainly on portability, miniaturization, connectivity, humanization, security and reliability. In this scenario, digital, low-cost CMOS technology plays a key role, especially in implementing complex systems into small devices with no batteries that can even be implanted in humans. Due to patient safety, the implanted devices are faced with challenges: device operation temperature and the RF power link must be kept extremely low.By using proper topologies, the whole system can be designed to operate in low-voltage and low-power modes to maintain low temperature and avoid tissue thermal hazards. In this paper, a voltage reference is proposed which can operate at as low as 500 mV with power consumption less than 100 nW. Furthermore, the proposed topology, based on composite transistors operating in weak inversion, shows a good rejection to threshold voltage V_t, which is an inherent CMOS dispersion parameter. Simulation results using the process corners show that the V_t dependence can be reduced to less than ±2% (3σ) at the body temperature and the PSRR can be as large as 65 dB for higher frequencies. One of the key features of the circuit is its simple design.     

A new curvature-corrected bandgap reference

A bandgap-voltage reference implemented with a new accurate circuit configuration for compensating the thermal nonlinearity of the base-emitter voltage is described. With this device, a temperature coefficient of 0.5 ppm//spl deg/C over the temperature range -25 to +85/spl deg/C has been achieved. The minimum required supply voltage amounts to only 5.5 V.     

A curvature-corrected low-voltage bandgap reference

A curvature-corrected bandgap reference that can function at supply voltages as low as 1 V, at a supply current of only 100 μA, is presented. After trimming, this bandgap reference has a temperature coefficient (TC) of ±4 p.p.m./°C. The reference voltage is about 200 mV and it can easily be adjusted to higher values. The temperature range of this circuit is from 0 to 125°C. This bandgap reference is realized using a standard bipolar process with base-diffused resistors     

Low-voltage low-power LVDS drivers

Two low-voltage low-power LVDS drivers used for high-speed point-to-point links are discussed. While the previously reported LVDS drivers cannot operate with low-voltage supplies, the proposed double current sources (DCS) LVDS driver and the switchable current sources (SCS) LVDS driver are suitable for low-voltage applications. Although static current consumption is greater than the minimum amount required by the signal swing, the DCS LVDS driver is simple and fast. The SCS LVDS driver, by dynamically switching the current sources, draws minimum static current and reduces the power consumption by 60% compared to previously reported realizations. Both drivers were fabricated in a standard 0.35-/spl mu/m CMOS process; they are compliant with LVDS standards and can operate at data rates up to gigabits-per-second.     

A low-voltage low-power voltage reference based on subthreshold MOSFETs

In this work, a new low-voltage low-power CMOS voltage reference independent of temperature is presented. It is based on subthreshold MOSFETs and on compensating a PTAT-based variable with the gate-source voltage of a subthreshold MOSFET. The circuit, designed with a standard 1.2-/spl mu/m CMOS technology, exhibits an average voltage of about 295 mV with an average temperature coefficient of 119 ppm//spl deg/C in the range -25 to +125/spl deg/C. A brief study of gate-source voltage behavior with respect to temperature in subthreshold MOSFETs is also reported.     

A low-voltage low-power CMOS voltage reference based on subthreshold MOSFETs

This paper describes a CMOS voltage reference using only resistors and transistors working in weak inversion,without the need for any bipolar transistors.The voltage reference is designed and fabricated by a 0.18μm CMOS process.The experimental results show that the proposed voltage reference has a temperature coefficient of 370 ppm/℃at a 0.8 V supply voltage over the temperature range of-35 to 85℃and a 0.1%variation in supply voltage from 0.8 to 3 V.Furthermore,the supply current is only 1.5μA at 0.8 V supply voltage.     

Low-voltage low-power multifunction current-controlled conveyor

In this study, low-voltage low-power multifunction current-controlled conveyor (CCCII) is introduced. Multifunction current conveyors are able to achieve various CCCII structures with a small modification in the circuit. The proposed circuit required ±0.5 V as a power supply, a simple circuit structure and low power consumption. The power consumption is only 4.8 µW. Low-voltage operation is achieved by using changeable threshold voltage and PMOS level-shifter current mirror. This circuit is able to operate as CCCII± with both positive and negative intrinsic resistance, which have a wide tunable range with a small modification in the circuit connections.     

Low-voltage low-power opamp based amplifiers

Amplifiers operating under low-voltage and low-power conditions are strongly limited in dynamic range and bandwidth. The maximum dynamic range is limited by the supply power and the thermal noise power in resistors. To obtain the maximum, input and output stages should be able to process signals from rail to rail. Several rail-to-rail input stages and rail-to-rail output stages biased in current-efficient class-AB mode are presented. Also, the bandwidth is limited by the low-power constraint. To reach the maximum bandwidth at sufficient DC gain, the effectivity of several frequency compensation structures is compared, such as Parallel, Miller, and Nested Miller Compensation. Finally, it is shown that the Multipath Nested Miller Compensation combines a very high bandwidth with high gain, while being insensitive to process parameters.     

一种工作在亚阈值区的低电压低功耗基准电压电路

本文提出了一种不使用三极管而只使用工作在亚阈值区的晶体管和电阻的电压基准。使用0.18um工艺进行流片以及测试的结果表明：本文所设计的电压基准可在0.8V的低电压下工作,在温度从-35˚C到85˚C的范围内,温度系数为370ppm/˚C;电源电压从0.8V到3V的条件下,电压偏差小于0.1%。而且在电源电压为0.8V的条件下,整个芯片的功耗只有1.5uA。     

多管组合曲率补偿低压带隙基准源

A new bandgap reference(BGR) curvature compensation technology is proposed,which is a kind of multiple transistor combination.On the basis of the existing first-order bandgap reference technology,a compensation current circuit consisting of a sink current branch and a source current branch is added.The BGR was designed and simulated by using Semiconductor Manufacturing International Corporation(SMIC) 0.18μm CMOS process.The simulation results showed that when the power supply voltage was 1 V,the temperature coefficient of the BGR was 2.08 ppm/℃with the temperature range from—40 to 125℃,the power supply rejection ratio (PSRR) was—64.77 dB and the linear regulation was 0.44 mV/V with the supply power changing from 0.85 to 1.8 V.     

Low-voltage low-power controllable preamplifier for electretmicrophones

A low-voltage low-power analog controllable preamplifier for electret microphones is discussed. It has been designed for a single supply voltage of 1.0 V, whereas its average power consumption amounts to some tens of microwatts. A DC current controls its gain directly into decibels. The design meets specifications concerning accuracy, bandwidth, and noise properties suitable for most applications in portable telephone equipment, portable transceivers, and hearing aids. Much attention has been paid to the dynamic range of the input signal, noise, and offset properties. The circuit has been realized in a semicustom IC process. Simulation and measurement data of the most important properties are presented     

Low-voltage low-power fully-integratable automatic gain controls

This paper discusses the design of low-voltage low-power fully-integratable automatic gain controls. Four different AGCs are presented, all consisting of three elementary building blocks: a controlled amplifier, a comparator and a voltage follower. Their design is treated separately. As an example, the final section describes an automatic gain control for hearing instruments, realized in a bipolar process.     

Low-voltage, low-power BiCMOS digital circuits

A new BiCMOS buffer circuit, for low-voltage, low-power environment, is presented. The circuit is based on the deep submicron technology and utilizes the parasitic bipolar transistors associated with the CMOS structure. The analysis, simulations and SPICE results confirm the functionality of the circuit and its speed and voltage swing superiority, compared with conventional BiCMOS circuits at low supply voltages     

Low-voltage low-power high-Q CMOS RF bandpass filter

Based on the gyrator-C inductor topology, a second-order bandpass filter can be realised by adding a series capacitor to the input port of the gyrator. high-Q second-, fourth- and sixth-order fully differential RF bandpass filters operating in the 2.4 GHz Industrial, Scientific and Medical (ISM) frequency band under a 2 V single power supply voltage with low-power dissipation are demonstrated     

Low-voltage low-power CMOS RF low noise amplifier

In this paper, a 1 V, 2 GHz CMOS low-noise amplifier (LNA) was developed intended for use in the front-end receiver. The circuit is simulated in standard $0.25\mathrm{\mu }\mathrm{m}$ CMOS MOSIS. The LNA gain is 25.675 dB, noise figure (NF) is 4 dB, reverse isolation $(S_{12})$ is $-134.3\mathrm{dB}$, input return loss $(S_{11})$ is $-14.6\mathrm{dB}$, output return loss $(S_{22})$ is $-13.34\mathrm{dB}$, and the power consumption is 5.13 mA from a single 1 V power supply. One of the features of the proposed design is using a three-component cascode limitation, one of it is a transistor, to reduce the supply voltage.     

Low-voltage,low-power current monitor for deep-submicron testing

An on-chip low-power circuit for both quiescent current I _ddq and transient current I _ddt monitoring is presented. The current monitor performs faster and is significantly smaller than those reported previously. The monitor is designed for low-voltage digital CMOS circuits (1.5V). The same design can be used in the testing of analogue and mixed signal circuits. The effect on the circuit under test performance is negligible. Testing speeds of up to 25MHz can be achieved (including the 4-bit A/D converter, 100MHz without the converter). The monitor has been implemented in 0.5μm and 0.35μm CMOS technology and tested successfully on parallel chains of inverters as circuit under test. Two types of fault (an open fault and a short fault) have been observed. Simulation and experimental results are included and analysed.     

Low-voltage low-power improved linearity CMOS active resistor circuits

A tutorial of CMOS active resistor circuits will be presented in this paper. The main advantages of the proposed implementations are the improved linearity, the small area consumption and the improved frequency response. In order to improve their linearity, improved performances linearization techniques will be proposed, with additional care for compensating the errors introduced by second-order effects. Design techniques for minimizing the silicon area consumption will be further presented and FGMOS (Floating Gate MOS) transistors will be used for this purpose. The frequency response of the circuits is very good as a result of biasing all MOS transistors in the saturation region and of a current-mode operation of an important part of their blocks. Additionally, small changing in each design allows to obtain negative controllable equivalent resistance circuits. The circuits are implemented in CMOS technology, SPICE simulations confirming the theoretical estimated results, showing small values of the linearity error (under 0.15% for the best design) for an extended input range and for a supply voltage equal with ±3 V. The proposed circuits respond to low-voltage low-power requirements, their design being adapted to the continuous degradation of the model quality associated with the evolution toward latest nanotechnologies.