A 10-b 300-MHz interpolated-parallel A/D converter

A monolithic 10-b A/D converter that realized a maximum conversion frequency of 300 MHz is described. Through the development of the interpolated-parallel scheme, the severe requirement for the transistor V_be matching can be alleviated drastically, which improves differential nonlinearity (DNL) significantly to within ±0.4 LSB. Furthermore, an extremely small input capacitance of 8 pF can be attained, which translates into better dynamic performance such as SNR of 56 dB and THD of -59 dB for an input frequency of 10 MHz. Additionally, the folded differential logic circuit has been developed to reduce the number of elements, power dissipation, and die area drastically. Consequently, the A/D converter has been implemented as a 9.0-mm×4.2-mm chip integrating 36 K elements, which consumes 4.0 W using a 1.0-μm-rule, 25-GHz f_t, double-polysilicon self-aligned bipolar technology     

A 10-b 15-MHz CMOS recycling two-step A/D converter

A two-step recycling technique is applied to implement a 10-b CMOS analog-to-digital (A/D) converter with a video conversion rate of 15 Msample/s. In a prototype digitally corrected converter, one capacitor-array multiplying digital-to-analog converter (MDAC) is used repeatedly as a sample-and-hold (S/H) amplifier, a DAC, and a residue amplifier so that the proposed converter may obtain linearity with the capacitor-array matching. An experimental fully differential A/D converter implemented using a double-poly 1-μm CMOS technology consumes 250 mW with a 5-V single supply, and its active die area, including all digital logic and output buffers, is 1.75 mm² (2700 mil²). Because the conversion accuracy of the proposed architecture relies on a capacitor-array MDAC linearity, high-resolution CMOS A/D conversions are feasible at high frequencies if sophisticated circuit techniques are further developed. For high-speed two-phase versions, the system can be easily modified to use multiplexing and/or pipelining techniques with a separate S/H amplifier and/or two separate flash converters     

A 10-b, 75-MHz two-stage pipelined bipolar A/D converter

A 4-b flash first quantizer is cascaded with an efficient 7-b second quantizer to attain 10-b resolution after error correction. As the second quantizer itself embodies analog subranging through folding and interpolation, its complexity is comparable with that of the first quantizer. An input track and hold preceding the first quantizer acquires dynamic signals with low distortion, and a second track and hold delays the analog residue signal to pipeline the operation of the two quantizers. This collection of components, accompanied by all necessary digital circuits for encoding and error correction is fabricated on an all-NPN 4-GHz f_T bipolar IC measuring 4×4 mm, which dissipates 800 mW from ±5-V supplies. At a 75-MEPi conversion rate, the untrimmed ADC exhibits 59 db S/(N+D) with a 6-MHz full-scale input, which diminishes by only 3 dB when the input frequency rises to 50 MHz     

A 12-b, 10-MHz, 250-mW CMOS A/D converter

A 12-b, 10-MHz, 250-mW, four-stage analog-to-digital converter (ADC) was implemented using a 0.8-μm p-well CMOS technology. The ADC based on a digitally calibrated multiplying digital-to-analog converter (MDAC) selectively employs a binary-weighted capacitor array in the front-end stage and a unit-capacitor array in the remaining back-end stages to obtain 12 b level linearity while maintaining high yield. All the analog and digital circuit functional blocks are fully integrated on a single chip, which occupies a die area of 15 mm² (4.2 mm×3.6 mm). Measured differential nonlinearity (DNL) and integral nonlinearity (INL) of the prototype are less than ±0.8 LSB and ±1.8 LSB, respectively     

A 10-b 50-MHz CMOS D/A converter with 75-Ω buffer

A 10-b 50-MHz digital-to-analog (D/A) converter for video applications that is based on a dual-ladder resistor string is presented. This approach allows the linearity requirements to be met without the need for selection or trimming. The D/A decoding scheme reduces the glitch energy, and signal-dependent switch signals reduce high-frequency distortion. The output buffer allows driving 1 V_pp to 75 Ω. The chip consumes 65 mW at maximum clock frequency and a full-swing output signal. The device is processed in a standard 1.6-μm CMOS process with a single 5-V supply voltage. The double-ladder architecture allows the requirements for small cell area and high linearity to be separated. Compensation techniques have been applied to reduce the second- and third-order distortion components; at 5-MHz signal frequency the total harmonic distortion is -53 dB     

A 10-b 40-MHz 0.8-μm CMOS current-output D/A converter

A 10-b binary-weighted D/A digital-to-analog converter based on current division is presented. The effective resolution bandwidth is 5 MHz at a maximum clock frequency of 40 MHz. The circuit is integrated in a 0.8-μm double-metal CMOS technology and the chip area is 0.4 mm². This particular converter was realized by constructing the bit currents through a careful combination of unit current sources and by limiting the driving voltage on the gates of the current switches     

A 10-b 125-MHz CMOS digital-to-analog converter (DAC) withthreshold-voltage compensated current sources

This paper describes a 10-b high-speed COMS DAC fabricated by 0.8-μm double-poly double-metal CMOS technology. In the DAC, a new current source called the threshold-voltage compensated current source is used in the two-stage current array to reduce the linearity error caused by inevitable current variations of the current sources. In the two-stage weighted current array, only 32 master and 32 slave unit current sources are required. Thus silicon area and stray capacitance can be reduced significantly. Experimental results show that a conversion rate of 125 MHz is achievable with differential and integral linearity errors of 0.21 LSB and 0.23 LSB, respectively. The power consumption is 150 mW for a single 5-V power supply. The rise/fall time is 3 ns and the full-scale settling time to ±1/2 LSB is within 8 ns. The chip area is 1.8 mm×1.0 mm     

A low glitch 14-b 100-MHz D/A converter

A low glitch 14-b 100-MHz current output digital-to-analog converter (DAC) is described. In addition to segmentation of the four most significant bits (MSB's) into 15 equally weighted current sources, a proportional-to-absolute-temperature (PTAT) switching voltage is applied to the current steering devices to minimize glitch over temperature. A bidirectional thin-film trim network and high β n-p-n devices reduce the amount of laser trimming required to achieve 14-b accuracy, resulting in less post-trim degradation of DAC linearity over temperature and the life of the chip. The converter has been fabricated in a 4-GHz/1.4-μm BiCMOS technology and exhibits a measured glitch energy of 0.5 pV·s (singlet). Settling time to within ±0.012% of the final value is ⩽20 ns for both rising and falling edges of a full scale step. Spurious free dynamic range (SFDR) for the described converter is 87 dBc at an update rate (f_CLK) of 10 MHz and an output frequency (f_OUT) of 2.03 MHz. The converter operates from +5 V and -5.2 V supplies and consumes 650 mW independent of conversion rate. The chip size is 4.09×4.09 mm including bond pads and electrostatic discharge (ESD) protection devices     

A complete monolithic 10-b D/A converter

A monolithic 10-b plus sign D/A converter has been developed that incorporates all necessary circuit functions including voltage reference and internally compensated high-speed output op amp in a single 82/spl times/148 mil chip. A unique logic switch and current source configuration achieves 0.05 percent nonlinearity with /spl plusmn/10 V compliance current output option as well as true or complementary binary coding. The design constraints and area requirements for scaling of current source emitter areas are reduced by using a new active current-splitting technique. The circuit features a 1.5 /spl mu/s settling time voltage output and sign-magnitude coding.     

A 10-b 150-MSample/s 1.8-V 123-mW CMOS A/D converter with 400-MHz input bandwidth

This work describes a 10-b 150-MSample/s 4-b-per-stage single-channel CMOS pipelined ADC incorporating improved gate-bootstrapping techniques for a wideband SHA and temperature- and supply-insensitive CMOS references. The proposed ADC is designed and fabricated in a 0.18-/spl mu/m one-poly six-metal CMOS technology. The measured differential and integral nonlinearities are within 0.69 LSB and 1.50 LSB, respectively. The prototype ADC shows a peak signal-to-noise-and-distortion ratio (SNDR) of 52 dB at 150 MSample/s. The ADC maintains the SNDR over 52 dB and 43 dB, respectively, for input frequencies up to the Nyquist frequency and 400 MHz at 140 MSample/s. The active die area is 2.2 mm/sup 2/ and the chip consumes 123 mW at 150 MSample/s.     

A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC

This paper describes a circuit design and experimental results of a video-rate 10-b analog-to-digital converter (ADC) suitable for portable audio-visual equipment. Two new circuit techniques, termed pipelined capacitive interpolation and error averaging circuits with capacitor networks, are developed. As a result, very low power dissipation of 30 mW at a low power-supply voltage of 2.5 V is attained at the conversion frequency of 20 MHz. Also, a good DNL of less than ±0.5 LSB and an acceptable signal-to-noise and distortion ratio of 55 dB are obtained for the input frequencies of 1 kHz and 1 MHz, respectively. The ADC is fabricated in 0.8-μm CMOS technology and occupies an area of 2.6×2.5 mm²     

A 10-b 20-Msample/s analog-to-digital converter

A 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9-μm CMOS technology is described. The converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-and-distortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies a 8.7 mm² and dissipates 240 mW     

A monolithic 10-b digital-to-analog converter using ion implantation

The design and fabrication of a self-contained 10-b monolithic digital-to-analog converter is described. To overcome the limitations of standard bipolar processing and to achieve a circuit with reasonably low process sensitivities, a new process incorporating ion implantation is used. The circuit has been designed in a manner to fully utilize the characteristics of this process with the objective of high performance along with simple wafer processing. System consideration as well as the design of each component block are discussed.     

A low glitch 10-bit 75-MHz CMOS video D/A converter

A low glitch 10-bit 75-MHz CMOS current-output video digital-to-analog Converter (DAC) for high-definition television (HDTV) applications is described. In order to achieve monotonicity and low glitch, a special segmented antisymmetric switching sequence and an innovative asymmetrical switching buffer have been used. The video DAC has been fabricated by using 0.8 μm single-poly double-metal CMOS technology. Experimental results indicated that the conversion rate is above 75 MHz, and nearly 50% of samples have differential and integral linearity errors less than 0.24 LSB and 0.6 LSB, respectively. The glitch has been reduced to be less than 3.9 pV·s and the settling time within ±0.1% of the final value is less than 13 ns. The video DAC is operated by a single 5 V power supply and dissipates 1.70 mW at 75 MHz conversion rate (140 mW in the DAC portion). The chip size of video DAC is 1.75 mm×1.2 mm (1.75 mm×0.7 mm for the DAC portion)     

A 10-b 40-Msample/s BiCMOS A/D converter

A fully-differential, 10-b, 40-Msample/s pipelined analog-to-digital converter (ADC) has been developed and tested. The converter exhibits a signal-to-(noise+distortion) ratio (SNDR) of 57.1 dB and consumes <400 mW of power from a single 5 V supply. The converter can digitize not only a fully-differential but also a single-ended input signal over a wide input range with little variation in converter performance. In addition, a full-power bandwidth (FPBW) of >250 MHz is made possible with the open-loop sampling scheme     

A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/Dconversion

The authors examine the application of oversampling techniques to analog-to-digital conversion at rates exceeding 1 MHz. A cascaded multibit sigma-delta (ΣΔ) modulator that substantially reduces the oversampling ratio required for 12-b conversion while avoiding stringent component matching requirements is introduced. Issues concerning the design and implementation of the modulator are presented. At a sampling rate of 50 MHz and an oversampling ratio of 24, an implementation of the modulator in a 1-μm CMOS technology achieves a dynamic range of 74 dB at a Nyquist conversion rate of 2.1 MHz. The experimental modulator is a fully differential circuit that operates from a single 5-V power supply and does not require calibration or component trimming     

A 200-MHz 64-b dual-issue CMOS microprocessor

A 400-MIPS/200-MFLOPS (peak) custom 64-b VLSI CPU is described. The chip is fabricated in a 0.75-μm CMOS technology utilizing three levels of metalization and optimized for 3.3-V operation. The die size is 16.8 mm×13.9 mm and contains 1.68 M transistors. The chip includes separate 8-kbyte instruction and data caches and a fully pipelined floating-point unit (FPU) that can handle both IEEE and VAX standard floating-point data types. It is designed to execute two instructions per cycle among scoreboarded integer, floating-point, address, and branch execution units. Power dissipation is 30 W at 200-MHz operation     

A 10-b, 100-MS/s CMOS A/D converter

A new architecture for a CMOS A/D converter overcomes many of the known problems in the parallel operation of multiple pipelined stages. The input signal is sampled in one channel, and after quantization to 4 b, the residue is distributed into many channels. A prototype implemented in 1-μm CMOS achieves 60 dB signal-to-noise plus distortion ratio (SNDR) at low conversion rates, with a resolution bandwidth of greater than 20 MHz. The SNDR drops by 3 dB at a 95 MHz conversion rate, and the bandwidth remains the same     

An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributedtrack-and-hold preprocessing

An analog-to-digital converter incorporating a distributed track-and-hold preprocessing combined with folding and interpolation techniques has been designed in CMOS technology. The presented extension of the well known folding concept has resulted in a 75 MHz maximum full-scale input signal frequency. A signal-to-noise ratio of 44 dB is obtained for this frequency. The 8-b A/D converter achieves a clock frequency of 80 MHz with a power dissipation of 80 mW from a 3.3 V supply voltage. The active chip area is 0.3 mm² in 0.5-μm standard digital CMOS technology     

A 433-MHz 64-b quad-issue RISC microprocessor

A quad-issue custom VLSI microprocessor is described. This microprocessor implements the Alpha architecture and achieves an estimated performance of 13.3 SPECint9S and 18.4 SPECfp95 at 433 MHz. The 9.6 million transistor die measures 14.4 mm×14.5 mm, and is fabricated in a 0.35-μm, four-metal layer CMOS process. This chip dissipates less than 25 W at 433 MHz using a 2.0 V internal power supply. The design was leveraged from a prior 300-MHz, 3.3-V, 0.50-μm CMOS design. It includes several significant architectural enhancements and required circuit solutions for operation at 2.0 V. The chip will operate at nominal internal power supply voltages up to 2.5 V allowing improved performance at the cost of increased power consumption. At 2.5 V, the chip operates at 500 MHz and delivers 15.4 SPECint95 (est) and 21.1 SPECfp95 (est). This paper describes the chip implementation details and the strategy for efficiently migrating the existing design to the 0.35-μm technology