一种适用于中频接收机的具有75dB动态范围的100MHz带通$Sigma Delta$调制器

本文介绍了一款适用于中频接收机的四阶开关电容带通$Sigma Delta$调制器,采样频率为100MHz。为优化谐振器的性能,文中提出了考虑运算放大器非理想特性后谐振器的传输函数。本文设计的调制器采用0.13-um标准CMOS工艺,在25MHz附近200KHz信号带宽内测得的SNDR和DR分别为68dB和75dB。调制器工作在1.2V电源电压下,总功耗为8.2mW。     

一种高阶1 bit插入式∑-△调制器的设计

介绍了插入式∑-△ A/DC调制器的设计过程,并给出了调制器行为级SIMULINK模型,通过对调制器系统级仿真可以确定调制器的信噪比、增益因子等参数,为其电路设计提供依据.设计了一个4阶调制器,仿真结果显示在128的过采样比、输入信号相对幅度-6 dB的条件下,可获得110 dB的信噪比,达到18 bit的分辨率.     

A Sub-1V Fourth-Order Bandpass Delta-Sigma Modulator

A sub-1V fourth-order bandpass delta-sigma modulator is presented in this paper. Using the switched opamp technique enables the modulator to operate at only 0.8 V supply voltage without using voltage multipliers or bootstrapping switches. A two-path structure is applied to relax the settling requirement. Implemented in a 0.25-m one-poly, five-metal standard CMOS process, the prototype modulator exhibits a signal-to-noise-plus-distortion ratio (SNDR) of 58.2 db and a dynamic range (DR) of 64 db in a 60 KHz signal bandwidth centered at 1.25 MHz while consuming 2.5 mW and occupying an active area of 2.11 mm².     

Domino Free 4-Path Time-Interleaved Second Order Sigma-Delta Modulator

A domino free 4-path time-interleaved second order sigma-delta modulator is proposed. This time-interleaved scheme uses only one integrator channel along with incomplete integrator output terms to completely eliminate the quantizer domino which is a key limit for the practical circuit implementation of conventional multi-path time-interleaved sigma-delta modulators. In addition, the single integrator channel leads to considerable hardware reduction as well as path mismatch insensitivity, since only one global feedback path is required. As a result, the switched capacitor implementation of the 4-path time-interleaved second order sigma-delta modulator is enabled with the conventional 2-phase clocking scheme by using only 5 op-amps.Kye-Shin Lee received the B.S. degree in electrical engineering from Korea University, Seoul, Korea, in 1992 and the M.S. degree in electrical engineering from Texas A&M University, College Station, in 2002. He is currently working toward the Ph.D. degree in electrical engineering at the University of Texas at Dallas.He was with LG Semicon Co. (now Hynix Semicon Inc.), Seoul, Korea from 1994 to 1999, where he was involved in mixed signal circuit design and testing of BW/Color CCD chipsets including timing/sync. signal generator, camera signal processor, USB camera interface, and sigma-delta CODECs for audio and voice band applications. His research has been focused on switched-capacitor circuits, sigma-delta modulators, and pipeline ADCs.Yunyoung Choi received the B.S. degree from Kwangwoon University, Seoul, Korea, in 1999 and the M.S. degree in electrical engineering from Texas A&M University, College Station, in 2002. He is currently working toward the Ph.D. degree in electrical engineering at the University of Texas at Dallas. He worked for Texas Instruments, Dallas, from May to December 2003 at the Wireless Business Unit. His research interest includes sigma-delta A/D and D/A converters for audio systems and RF applications.Franco Maloberti received the Laurea Degree in physics (summa cum laude) from the University of Parma, Parma, Italy, in 1968 and the Dr. Honoris Causa degree in electronics from the Instituto Nacional de Astrofisica, Optica y Electronica (Inaoe), Puebla, Mexico, in 1996.In 1993, he was a Visiting Professor at ETH-PEL, Zurich, Switzerland. He was Professor of Microelectronics and Head of the Micro Integrated Systems Group, University of Pavia, Pavia, Italy, and the TI/J.Kilby Analog Engineering Chair Professor at Texas A&M University, College Station. He is currently with the University of Pavia and an adjunct Professor at the University of Texas at Dallas. His professional expertise is in the design, analysis, and characterization of integrated circuits and analog digital applications, mainly in the area of switched-capacitor circuits, data converters, interfaces for telecommunication and sensor systems, and CAD for analog and mixed A/D design. He has written more than 250 published papers, three books, and holds 15 patents.Dr. Maloberti was a 1992 recipient of the XII Pedriali Prize for his technical and scientific contributions to national industrial production. He was co-recipient of the 1996 Institution of Electrical Engineers (U.K.) Fleming Premium for the paper “CMOS triode transistor transconductance for high-frequency continuous time filters.” He has been responsible at both technical and management levels for many research programs including ten ESPRIT projects and has served the European Commission as ESPRIT Projects’ Evaluator and Reviewer and as a European Union expert in many Initiatives. He served the Academy of Finland on the assessment of electronic research in Academic institutions and on the research programs’ evaluator. He was Vice-President, Region 8, of the Editor of IEEE Circuits and Systems (CAS) Society from 1995 to 1997 and an Associate Editor of the IEEE Transcations on Circuits and Systems II. He received the 1999 IEEE CAS Society Meritorious Service Award, the 2000 CAS Society Golden Jubilee Medal, and the IEEE Millennium Medal. He is the President of IEEE Sensors Council and a member of the Board of Governors of the IEEE CAS Society. He is also the member of the Italian Electrotechnical and Electronic Society (AEI) and the Editorial Board of Analog Integrated Circuits and Signal Processing.     

A Triple-Mode Sigma-Delta Modulator for Multi-Standard Wireless Radio Receivers

A 1.8 V sigma-delta modulator with a 4 bit quantizer has been designed for GSM/WCDMA/WLAN receivers in a 0.18 um CMOS process. The modulator makes use of low-distortion sigma-delta modulator architecture and Pseudo-Data-Weighted-Averaging technique to attain high linearity over a wide bandwidth. Power dissipation is minimized by optimizing the architecture and by a careful design of analog circuitry. In GSM mode, the modulator achieves 96/104 dB peak SNR/SFDR over 100 kHz bandwidth and dissipates 18 mW at a sampling frequency of 32 MHz. The modulator achieves 92/68 dB peak SFDR and 77/54 dB peak SNR over a 2 MHz/10 MHz bandwidth and dissipates 23/39 mW at a sampling frequency of 64 MHz/160 MHz in WCDMA/WLAN. Ana Rusu received degrees of diploma engineer in electronics and telecommunications engineering from Technical University of Iasi, Romania, in 1983 and Ph.D. in electronics engineering from Technical University of Cluj-Napoca, Romania, in 1998. During 1983–1986 she was with Research Institute for Electronics Iasi, as researcher engineer. From 1986 to 1988 she was with Territorial Computer Centre, Piatra-Neamt, Romania, as a programmer in software engineering. Since 1988 she has been with the Technical University of Cluj-Napoca, Electronics and Telecommunications Faculty. In 1999 she was appointed as an associate professor. She has been in visiting researcher positions in University of Bradford, England, and Institute National Politechnique of Grenoble, France, in 1997 and 2001, respectively. Since September 2001, she has been with the Royal Institute of Technology (KTH), Stockholm, Sweden, where she is a senior researcher in radio and mixed-signal systems group. Her research interests include data conversion techniques for wireless communications and the design of low-voltage low-power analog and mixed-signal ICs. Ana Rusu has authored or coauthored five books (published in Romanian language) and more than 40 papers in international conference proceedings and journals. Alexey Borodenkov received his B.Sc. degree in computer science and engineering from St. Petersburg Electrotechnical University, Russia in 2002 and M.Sc. degree in electrical engineering from Royal Institute of Technology (KTH), Stockholm, Sweden in 2004. In October 2004 he joined Samsung Electronics Co. Ltd., Gyeunggi-Do, Korea, where he is involved in the design of multi-standard transceivers for wireless communications. His current research interests include integrated-circuit development of frequency synthesizers and data converters. Mohammed Ismail received the B.S. and M.S. degrees in electronics and telecommunications engineering from Cairo University, Egypt, in 1974 and 1978 and the Ph.D. in electrical engineering from the University of Manitoba, Canada, in 1983. He is a Professor with the Department of Electrical Engineering, The Ohio State University, Columbus. Since April 2003, he is also a Professor with the Department of Microelectronics and Information Technology, Royal Institute of Technology (KTH) Stockholm, Sweden. He has over 20 years experience of R&D in the fields of analog, RF and mixed signal integrated circuits. He has held several positions in both industry and academia and has served as a corporate consultant to nearly 30 companies in the US, Europe and the Far East. His current interest lies in research involving digitally programmable/configurable fully integrated radios with focus on low voltage/low power first-pass solutions for 3G and 4G wireless handhelds. He publishes intensively in this area and has been awarded 11 patents. He has co edited and coauthored several books. He co-founded ANACAD-Egypt (now part of Mentor Graphics, Inc.) and Spirea AB, Stockholm (now Firstpass Semiconductors AB), a developer of CMOS radio and mixed signal IPs for handheld wireless applications. Dr. Ismail has been the recipient of several awards including the US National Science Foundation Presidential Young Investigator Award, the US Semiconductor Research Corp Inventor Recognition Awards in 1992 and 1993, and a Fulbright/Nokia fellowship Award in 1995. He is the founder of the International Journal of Analog Integrated Circuits and Signal Processing, Springer and serves as the Journal's Editor-In-Chief. He has served as Associate Editor for many IEEE Transactions, was on the Board of Governors of the IEEE Circuits and Systems Society and is the Founding Editor of “The Chip” a Column in The IEEE Circuits and Devices Magazine. He is a Fellow of IEEE. Hannu Tenhunen received degrees of diploma engineer in electrical engineering and computer sciences from Helsinki University of Tehnology, Helsinki, Finland, in 1982 and Ph.D. in Microelectronics from Cornell University, Ithaca, NY, U.S.A., in 1986. During 1978–1982 he was with Electron Physics Laboratory, Helsinki University of Technology, and from 1983 to 1985 at Cornell University as a Fullbright scholar. From September 1985 he has been with Tampere University of Technology, Signal Processing Laboratory, Tampere, Finland, as an associate professor. He was also a coordinator of National Microelectronics Program of Finland during 1987–1991. Since January 1992, he has been with Royal Institute of Technology (KTH) Stockholm, Sweden, where he is a professor of electronic system design. His current research interests are VLSI circuits and systems for wireless and broadband communication, and related design methodologies and prototyping techniques. He has made over 400 presentations and publications on IC technologies and VLSI systems worldwide, and has over 16 patents pending or granted.     

宽阻带三模谐振器微带带通滤波器设计

介绍了一种新颖的微带三模谐振器,由该谐振器构成的微带滤波器具有较宽的通带以及较好的带外抑制.对传统的单模微带环形谐振器结构进行优化,使谐振器在通带内具有三个谐振点,并且在通带边缘有四个对称衰减极点.引入的阶梯阻抗谐振单元使得微带三模谐振器具有良好的带外抑制.依据传输线原理对宽阻带三模谐振器进行了分析,并完成了中心频率为1090 MHz的宽阻带带通滤波器设计和加工,其实际测试结果与软件仿真结果具有良好的一致性.     

屏蔽壳结构高Q值混合谐振器集成带通滤波器

提出了一种基于混合谐振器的新型二阶带通滤波器,该混合谐振器由微带线和一个短路的铜柱线组 成,这可以利用射频收发系统的结构件空间,并方便与平面微带电路集成,以提高滤波器的品质因数,它的无载Q 值 为455,高于传统的微带谐振器。而且,通过源负载耦合和混合电磁耦合的方法,在通带两边分别有一个可调的传输 零点,提高滤波器带外抑制特性。实验结果表明,测试结果与仿真数据吻合良好。     

Comments on “Bandpass Sigma-Delta Modulator Employing SAW Resonator as Loop Filter”

Some corrections needed in the theoretical analysis of the surface acoustic wave resonator loop filter for a bandpass sigma-delta modulator, as presented by Yu and Xu, are pointed out. A simple idea is also proposed for perfect cancellation of anti-resonance without substantially affecting the resonance frequency, but with the added benefits of an enhanced factor and insertion gain, rather than insertion loss. However, a practical implementation of the idea remains an open question.     

一种带输入输出抽头的新型阶梯式阻抗微带带通滤波器

本文提出了一种利用阶梯式阻抗微带线构造微型带通滤波器的新型结构。在该结构中引入以零相位方式接入的微带抽头，与带集总电容的阶梯式阻抗微带滤波器相配合，通过在通带两侧分别产生两个传输零点，很好地改善了滤波器的带通特性。     

A 1 V Second Order Sigma-Delta Modulator

A second order switched capacitor sigma-delta modulator operating at a supplyvoltage of 1 V is presented. This low supply voltage restricts the gate overdrivevoltage available for switching transistors. The design relies on the elimination ofcritical switches by using a modified switched op amp for the integrator and novelswitched half-supply and reference voltage generators. The design has been carried outin a fully differential configuration in order to minimize errors arising from chargeinjection and clock-feedthrough effects. The converter has been implemented using aconventional 0.8 m double-poly double-metal CMOS process, having a nominalthreshold voltage of 0.75 V. Test results, showing more than 9 bits of resolutionwith an oversampling ratio of 64, are also presented.     

一种低功耗高精度Sigma-Delta调制器

提出了一种改进的三阶单环Sigma-Delta调制器,噪声传递函数采用前馈方式实现极点,降低了积分器输出信号的幅度,从而降低功耗;采用局部反馈实现零点,从而优化了输出信噪比。采用0.35μm CMOS工艺设计了该调制器,过采样率128,信号带宽24kHz,分辨率16bit,在3.3V工作电压下,模拟电路部分功耗2.7mW,数字部分功耗0.5mW。电路用开关电容技术实现,在HSPICE中通过多工艺角验证。     

一种低电压的Sigma-Delta ADC新结构

介绍了一种低电压Sigma-Delta ADC新结构,该结构采用了二阶单位增益ΣΔ调制器和一阶传统ΣΔ调制器相结合的方式,既可以从系统级降低对运放直流增益等非理想因素的要求,又可以减少加法器的个数、降低电路的复杂度。在此基础上,采用HJTC0.18μm1.8V/3.3V1P6M混合信号工艺,实现了一种1V工作电压的ΣΔ调制器,经测试动态范围可以达到69.5dB。     

一种高分辨率∑△小数分频频率合成器

提出了一种采用新型分频器的小数分频频率合成器。该频率合成器与传统的小数分频频率合成器相比具有稳定时间快、工作频率高和频率分辨率高的优点。设计基于TSMC0.25μm2.5V1P5MCMOS工艺,采用sig-ma-delta调制的方法实现。经测量得到该频率合器工作频率在2.400～2.850GHz之间,相位噪声低于-95dBc/Hz@100kHz,最小频率步进小于30Hz,开关时间小于50μs,满足多数无线通信系统的要求。     

一种新型开路环谐振带通滤波器

利用开路环终端的内部电容耦合效应,提出一种结构紧凑,具有小型化和良好的二阶和三阶谐波抑制能力的开路环谐振器窄带带通滤波器.分析了开路环终端电容内部耦合结构变化对带通滤波器谐波抑制特性的影响,并利用上述结构仿真和设计了一个中心频率为1.5 GHz的带通滤波器,模拟结果与实验结果吻合良好,验证了滤波器的设计思想.     

基于16 bit Sigma-Delta模数转换器的数字滤波器设计

介绍了基于64倍过采样sigma-delta模数转换器的多级抽取滤波器设计.通过采用低功耗的多相分解梳状滤波器结构来代替传统的CIC滤波器结构,使得梳状滤波器部分的功耗降低近5倍.通过对滤波器电路结构的优化,可节省35%的芯片面积占用量.经过仿真及FPGA验证,该滤波器的信噪比达到99 dB,可以实现16位精度模数转换器的设计要求.     

A Multistage Closed-loop Sigma-Delta modulator (MSCL)

A new family of high order Sigma Delta modulators called MSCL (Multi Stage Closed-loop) is presented in this paper. They use a global feedback to lower the sensitivity to circuit imperfections. This feedback from the output of the modulator is the sum of the output of each comparator so that no digital prefiltering is required before summing up these signals. However, easy calibration will be required to compensate for the feedback imperfections.MSCL modulators present the same insensitivity to circuit imperfections as classical multi-order one-bit converters, but reach the performance of high-order MASH (MultistAge noise SHaping) modulators. They help make high-order low-pass or band-pass modulators without limit cycles so that their quantizing noise characteristics are similar to those predicted by the linear simplified model.     

Low Distortion and Swing Suppression Sigma-Delta Modulator with Extended Dynamic Range Scheme

This work presents a new low distortion and swing suppression second order sigma-delta modulator with extended dynamic range scheme. The proposed modulator is based on the dual-quantizer architecture and can effectively extend the dynamic range by only adding two simple digital filters in the digital circuit. The techniques of low distortion and swing suppression integrator designs are also employed in the new architecture. Accordingly, this new architecture can improve the circuitry nonlinearity, and the in-band noise can be significantly suppressed to achieve a high resolution in mid or wide bandwidth applications. A second order SDM for Bluetooth application with bandwidth of 500 KHz and sampling frequency of 40 MHz was designed and implemented. The peak SNDR of the experimental SDM is 78 dB.     

用液晶作调制器的相位成像

利用液晶调制器和ＣＣＤ探头组成的荧光相位成像系统,实现了不同荧光寿命物体的荧光成像,时间分辨率达到了亚毫秒量级。并对结果进行了讨论。     

A 1.8 V 15-bit 1 mW 2nd-Order Sigma-Delta Modulator

Low-voltage low-power sigma-delta modulators provide a critical interface in portable mixed-signal electronic systems. This paper deals with the design andimplementation of a low-voltage, low-power 2nd-ordersigma-delta modulator operating from a single 1.8 V powersupply using a conventional 3.3 V, double-poly, 0.35 mCMOS process, based on fully-differentialswitched-capacitor techniques. All the circuit blocks areintegrated on one chip, and the input common-mode voltageis set at mid-rail, resulting in low power dissipation,minimum off-chip components, and high efficiency,flexibility and compatibility. The design is useful forvoice applications in personal communications systemssupplied by two nickel-cadmium or alkaline batteries. Themodulator exhibits a 15-bit dynamic range for a 7 kHzbandwidth, and a 14-bit dynamic range for a 20 kHzbandwidth at an oversampling frequency of 2.56 MHz. Thepeak SNDR reaches 62 dB. The complete 2nd-order modulatorhas a power dissipation of 0.99 mW, and occupies 0.31mm² die area excluding bonding pads.