Custom design of a VLSI PCM-FDM transmultiplexer from system specifications to circuit layout using a computer-aided design system

The computer-aided design of a VLSI PCM-FDM transmultiplexer is presented. The entire design process, from system specifications to integrated circuit layout, is carried out with the aid of specialized computer programs for the analysis, synthesis, and optimization at each design level: the filter network, the architecture, and the circuit layout. These CAD tools support a top-down custom design methodology based on bit-serial architectures and standard cells. A customized architecture is constructed which is integrated using a 5-/spl mu/m CMOS cell library. The results are compared with a fully manual design and demonstrate the power of architecture based computer-aided design methodologies for VLSI filtering. By combining both synthesis and optimization aids at each design level it is possible to achieve a high degree of automation while retaining an efficient use of silicon area, high throughput, and moderate power consumption.     

An integrated switched-capacitor signal processing design system

A CAD system integrating switched-capacitor network function synthesis, circuit synthesis, and layout is presented. The tool addresses the design of programmable gain, cosine, interpolation, and arbitrary transfer functions in addition to canonical filter structures. Amplifier design is based on numerical optimization of highly accurate analytic models derived with the aid of symbolic-mathematics-based model development aids. The physical design of the filter is created by a general-purpose switched-capacitor circuit synthesizer. The tool makes it possible to synthesize a complete switched-capacitor signal path with full handcrafted quality in a single day. Examples taken from actual IC designs illustrate the utility and accuracy of the various functions     

Intuitive analogue circuit design

This paper is concerned with ideas and methods for a teaching approach that has been developed to provide insight into and aid creativity in the process of analogue circuit design. This approach is modelled on the way the authors see circuit designers acting as cognitive agents, namely qualitatively, intuitively, abstractly and in a knowledge rich and formalism poor fashion. This can be contrasted with the formal mathematical approach, the tool employed by designers once an understanding has been reached of the design problem at hand. Although formal modelling approaches have been well researched, modelling the initial design process can throw light upon and maybe tackle the problem of the lack of an analogue design formalism of the kind seen in digital circuit design. The authors feel that there is a cognitive process at the initial stages of analogue design not present in the digital design process that must be tackled. The paper presents a formalisation of some techniques used by designers to help deal with the manipulation of complex relationships in analogue circuit design. These formalisms can be viewed as giving cognitive support to the designer to enhance creativity     

Computer-aided design of VLSI circuits

With the rapid evolution of integrated circuit (IC) technology to larger and more complex circuits, new approaches are needed for the design and verification of these very-large-scale integrated (VLSI) circuits. A large number of design methods are currently in use. However, the evolution of these computer aids has occurred in an ad hoc manner. In most cases, computer programs have been written to solve specific problems as they have exist and no truly integrated computer-aided desisn (CAD) systems exist for the design of IC's. A structured approach both to circuit desisn and to circuit verification, as well as the development of integrated design systems, is necessary to produce cost-effective error-free VLSI circuits. This paper presents a review of the CAD techniques which have been used in the design of IC's, as well as a number of design methods to which the application of computer aids has proven most successful. The successful application of design-aids to VLSI circuits requites an evolution from these techniques and design methods.     

Quantitative comparison of alternative sensory displays for mobility aids for the blind

This paper proposes a method to compare quantitatively various auditory display schemes communicating the course a blind traveler should follow to comply with information a blind mobility aid has acquired, and the optimal scheme is sought for that traveler. A computer system emulates different display devices which use amplitude modulation to indicate the error of a subject's location from the indicated course. The real-time Selspot-based TRACK system measures the location of the human subject in real time, and the error is presented to the subject via each of the emulated devices. The indicated course, human trajectory, and error are recorded in computer disk memory. The performance of the human in each task is evaluated by calculation of a transfer function of the human with each display and then using this transfer function as the criterion for comparison. The feasibility of designing the display schemes of blind mobility aids using this procedure is demonstrated. Thus, an optimal choice for the specific blind person can be made via this system before committing a particular mobility aid design to the lengthy development process.     

CAD tools for ASIC design

Computer aids have been used for both the design and verification of electronic systems for many years. The recent explosion in the complexity of electronic systems that the advent of Very Large Scale Integration (VLSI) has allowed, has made the use of sophisticated computer-aided design tools indispensable. Computer aids will soon also provide key proprietary advantages as semiconductor and system design houses vie for the promising Application-Specific IC (ASIC) market of the next decade. This paper focusses on the techniques critical to both custom and ASIC design, the directions of present research and development for these areas, and future trends. In particular, recent developments in tools for the automated design of combinational logic are reviewed. These techniques include both algorithmic and rule-based approaches.     

Development of an object-oriented knowledge-based system for powerelectronic circuit design

A knowledge-based (expert) system (KBS) approach to power electronic circuit design is presented. The system, a power electronics and control tool, designated PECT, is written using Smalltalk-80, which integrates the artificial intelligence techniques of production rules for high-level knowledge representation. PECT embraces elements of power circuitry design and contains such features as selection of the circuit configuration, control facility, and power device best suited to a given application. It is interfaced with HSPICE, the commercial version of a general-purpose circuit simulation package, and a semiconductor power device library. Data retrieved from this library is converted into an object-oriented representation database. Analytical hierarchy process reasoning is performed on this data to aid the device selection process. System architecture as well as target design realization process are detailed. The criteria of development and the factors and requirements in building the PECT are also included. An example simulation is given representing a buck-boost converter using a gate turn-off thyristor (GTO) switch model     

The automatic synthesis of digital systems

The purpose of a digital synthesis aid is to allow a digital system architect to describe the behavior of a system to be built and to then aid him in the logic design of that system. This paper will overview several different approaches to the development of synthesis aids. The importance of key features of synthesis aids, such as the automatic generation of multilevel system representations, will also be discussed.     

Significance of Configuration and Subassemblies in Sequential Procedural Instructions and Role of Text-Graphical Aid: An Explorative Study

The purpose of this study was to learn about readers' ability to logically comprehend sequential procedural instructions, presented as isolated graphic frames. Further, this study sought, to find out how text and graphical aids can help comprehension. The 20 participants in this study received a stack of graphic cutouts demonstrating the action in a sequential assembly process. Readers had to sequentially order the collection of unordered graphics with either supporting text describing the action or supporting graphics showing the completed action. Results showed that readers often falter when process information is not presented as part of a configuration and also falter often at points where they need to comprehend instructions demonstrating transitions between subassemblies. Further, data also showed that performance was better with outcome graphics as an aid than with text as an aid. although the difference was not statistically significant.     

Designing-in of quality through axiomatic design

Decisions made during the design stage of product and process development profoundly affect product quality and process productivity. To aid in design decision making, a theoretical framework is advanced; the axiomatic approach to design. Axiomatic design consists of: (1) domains in the design world; (2) mapping between these domains; (3) characterization of a design by a vector in each domain; (4) decomposition of the characteristic vectors into hierarchies through a process of zigzagging between the domains; and (5) the design axioms, viz, independence and information axioms. Statistical process control (SPC) and other methodologies to improve quality are valid only when they are consistent with the independence and information axioms. This paper presents several criteria that govern the design and manufacture of quality products. To be able to control the quality of products, a design must satisfy the independence axiom. Based on this axiom and some theorems, several design criteria are derived and discussed. These criteria provide the bounds for the validity of some of the SPC techniques being used. When there is more than one acceptable design of a product or process, the information axiom must be used to select the best design(s)     

Low-power multi-threshold MCML: Analysis, design, and variability

The increasing demand on low-power applications is adding pressure on circuit designers to come out with new circuit styles that can decrease power dissipation while making use of the performance improvement of the new CMOS technologies. Multi-threshold MOS current mode logic (MTMCML) appears to be a solution to this problem by making use of the high-performance of MOS current mode circuits while minimizing power dissipation with the help of multi-threshold CMOS technologies. In this work, analytical formulations, based on the BSIM3v3 model, are proposed for MTMCML performance measures with an error within 10% compared to HSPICE. The formulation helps designers to efficiently design MTMCML circuits without undergoing the time-consuming HSPICE simulations. Furthermore, it provides design guidelines and aids for designers to fully understand the different tradeoffs in MTMCML design. In addition, the analysis is extended to study the impact of technology scaling and parameter variations on MTMCML. It is shown that the worst case variation in the minimum supply voltage of MTMCML is 1.16%, thus suggesting maximal power saving.     

VLSI design using Apple MacIntosh

VLSI design has caused a revolution in microminiaturization. The design process requires construction of stick diagrams for the digital circuit to be designed. These diagrams are prepared using different colored layers. The color graphics and the color monitors make the overall system quite expensive. The object of this article is to show how an inexpensive personal computer like the Apple MacIntosh can be used for preparing VLSI stick diagrams. The Apple MacIntosh's capabilities include translation, mirroring, detail work and hatching; which are indispensible in the construction of stick diagrams. The stick diagrams for a few examples such as serial adder, half adder, adder/subtractor and generalized pipeline array cell have been worked out. It is hoped that this paper will aid in making VLSI design easier on less expensive and easily obtainable personal computers.     

An efficient column generation design method of p-cycle-based protected working capacity envelope

The protected working capacity envelope (PWCE) concept was proposed by Grover (2004) in order to simplify network operations and management in survivable wavelength division multiplexing (WDM) networks. In this paper, we focus on the design of PCWE and investigate a new design method based on column generation (CG) for designing survivable WDM networks based on p-cycle PWCE. Proposed design algorithms for PWCE and p-cycle proceed in two steps: A first step where a large (sometimes huge) number of cycles is enumerated followed by a second step where the selection of the most promising p-cycles is made with the help of combinatorial optimization tools. In this paper, we develop a new (single-step) method based on large scale optimization tools, that is, CG techniques, where the generation of cycles is dynamic and embedded within the optimization process. The key advantage of CG techniques is that no a priori cycle enumeration step is required ahead of the optimization process: The generation of the relevant cycles, only one or few at a time, is embedded in the optimization process. We conducted intensive computational experiments to compare the performances of our CG algorithms with four other algorithms in the literature. The different algorithms were compared with regard to several design metrics and running time. Results obtained in the experiments on five different network instances show that the CG-based algorithm outperforms by far all proposed algorithms in the literature, both with respect to the scalability (much smaller computing times for large network instances) and also with respect to the quality of the solutions.     

Perceptual time-frequency subtraction algorithm for noise reduction in hearing aids

Sensorineural hearing disorders are a major and universal community health problem. In many cases, hearing aids offer the only solution for people suffering from such disorders. Unfortunately existing aids do not provide any improvement in intelligibility of the signal when background noise is present. A hearing aid system should ideally simulate auditory processes including those aspects of the speech signal that are perceptually important. This work presents a new integrated approach to the design of a digital hearing aid, based on a wavelet transform, as well as a formulation of the temporal and spectral psychoacoustic model of masking. Within the model, the Perceptual Time-Frequency Subtraction (PTFS) algorithm is developed to simulate the masking phenomena and reduce noise in single-input systems. Results show that the use of the PTFS yields a significant improvement in speech quality especially in unvoiced portions. Additionally, the noise component during periods of silence has been attenuated by up to 20 dB. This new noise reduction method is expected to be applicable in a variety of applications, including digital hearing aids and portable communication systems (e.g., cellular telephones).     

The new line in IC design

If deep submicron ICs are to excel in yields and performance, the design process must focus throughout on their interconnects. A new design process grapples with the problem. Design For interconnectivity, as it is called, ensures that interconnection information is available throughout the design process, so that the circuitry may be optimized around it at every stage. The availability of this information proves the key to achieving yield and performance goals in deep submicron designs. The novel process involves predicting, at an early stage in logic design, the probable paths of interconnects and any problems likely to ensue. Later on, it tackles device layout and performance verification one small step at a time. To do this, the front-end logic designers need tools to gather the proper information without plunging into the intricacies of physical design, while the back-end physical designers need tools with which to surmount interconnect issues. Moreover, technologies are required to produce globally optimized results by linking logical and physical design tools more closely     

二维介质PBG结构的工程设计

针对介质材料中按二维菱形周期排列空气圆孔的PBG结构，采用平面波展开法结合迭代技术的理论分析程序，对结构尺寸与介质参数的不同组合进行了批量计算，根据对计算结果的分析，归纳出阻带范围与结构参数之间的函数关系，经数据拟合得出一组准确而快捷的工程设计公式，还给出了根据预期的阻带范围设计PBG结构参数的简明步骤，实例验证了该组公式的实用性。     

On the design of a series-feedback network in a transistornegative-resistance oscillator

This paper presents a review and exposition to the design of the series-feedback network commonly used in a negative-resistance transistor oscillator. An appropriate selection of the feedback network can significantly increase the negative resistance of the two-port network and is, therefore, an important design step. Three methods, the third being a CAD method, are given for the design of the series-feedback network with examples that help illustrate the procedures used in each method. Furthermore, the examples show the agreement amongst the three methods     

The design and evaluation of online help for Unix EMACS: capturingthe user in menu design

The card-sort technique and cluster analysis were used for determining an effective organization for a help menu in Unix EMACS. Similarity data were gathered for with a card-sorting task using EMACS commands, and a hierarchical cluster analysis of the data was performed. The results indicate that differences among novices, intermediates, and experts appear with computer-based concepts such as windows and buffers, but that the sorts are more similar than they are different. It is argued that cluster analysis may aid designers in determining a functional organization, but that in the domain of this study, this organization may not help users bridge the mapping from real world tasks to computer tasks     

The practical engineer [IC design, power reduction]

The need of popular portable electronics for long battery life is placing power reduction at the top of every IC design engineer's to-do list. A new breed of design automation tools is helping them scrimp on power at every step of the VLSI design process. The automation tools can be differentiated, to a first order, by the level of abstraction on which they operate. Lowest of all are the transistor level tools. These possess the best accuracy, but commensurately require the longest run times and have the smallest capacities-the size of the circuit that can be analyzed. While transistor level tools can assist with analyses earlier in the design process, they are typically used to characterize cells and modules for use at the higher abstraction levels. The next level of abstraction embraces the logic-level power analysis tools. The highest abstraction level for which power analysis tools exist today is the architectural level. This type of tool analyzes abstract design representations such as Verilog or VHDL RTL code. The use of these tools in power reduction design is outlined     

多通道数字助听器算法及低功耗VLSI设计

改进了多通道数字助听器中的听力补偿和噪声消除算法,并进行了低功耗VLSI设计.听力补偿方面,提出一种改进的多通道宽动态范围压缩(WDRC)算法;该方法降低了存储和计算开销,并抑制了对残余背景噪音的过度放大.噪声消除方面,利用语音谱和噪声谱的帧间相关性,改进了传统的多子带谱相减算法,使之在硬件实现时便于并行运算,同时不影响消噪性能.最后,综合采用多种低功耗设计方法,在SMIC的130nm工艺条件下,完成了基于上述算法的多通道数字助听器VLSI设计.后仿结果表明,该设计总功耗仅为228μW.