基于无线传感器网络能耗系统的研究

节能已经成为无线传感器网络研究的核心部分。该文研究了无线传感器网络拓扑结构的邻近节点数对网络能耗的影响,主要采用动态电压调节技术(DVS)来降低无线传感器网络中节点的能耗。动态电压调节主要通过减少门等效电容、供电电压以及降低转换因子、时钟频率来达到降低动态能耗的目的,其中,降低供电电压节能效果最佳。与其他方法相比,动态电压调节降低能耗更加明显、效率更高。通过在CC2430节点芯片上测试验证,通过改变其分频比,得出了功耗和频率的近似线性关系。     

优先级融合动态电压频率调节的云计算任务调度算法研究

为了在云计算任务调度过程中保证云设备效率的同时提高资源利用率,提出了一种基于优先级和动态电压频率调节的调度算法。首先,为调度算法定义了问题模型以规范异构服务器的性能;然后,利用优先级为任务提供可行的组合或调度;最后,利用动态电压频率调节为服务器提供适当的电压和频率供应,并且向虚拟机管理器发送分配结果。利用可扩展的模拟工具Cloud Sim进行实验评估了本文方法的能耗和调度时间,结果表明,本文方法的执行时间与MMF-DFVS方法相当,而能耗比MMF-DFVS降低了5%-25%。     

创意电子实现整合式DVFS低功率系统设计平台

创意电子（Global Unichip Corp）日前宣布,该公司已经成功地在65奈米制程平台上,验证先进的动态电压与频率调节技术（DVFS）,为其Power Magic低功率设计服务更添一项新的利器。这一款先进的动态功率降低技术,是创意电子继推出完整的漏电降低（Leakage Reduction）技术后,更进一步提供完整验证过的低功率系统设计平台,     

任务敏感的多模式视频编码系统功耗控制方法

在嵌入式多模式视频编码系统中,动态电压频率调整(Dynamic Voltage and Frequency Scaling,DVFS)技术可在一定程序上节约系统能耗,然而持续降低电压和频率可能影响处理器接口资源的传输性能,甚至导致系统无法正常工作.针对该问题,提出了一种任务敏感的功耗控制方法.通过研究多模式视频编码任务量和处理器资源之间的关系,建立一个任务敏感的资源配置模型,基于该模型设计了一个自适应功耗控制器,在系统工作过程中根据编码任务量的不同动态调节处理器工作频率和工作核数.实验表明,在满足多模式实时视频编码功能和性能要求的基础上,该文提出的方法与传统DVFS技术相比,单帧视频编码的平均功耗节省了11.4%.     

基于自适应DVFS的SoC低功耗技术研究

对便携式系统设备而言,在采用目前90 nm和130 nm工艺进行新的系统级芯片(SoC)设计中,对整个系统功耗的优化变得与性能和面积的优化同等重要.为此,简单介绍了涵盖静态功耗和动态功耗的低功耗技术,同时提供了一种能够通过使用前向预测反馈的动态电压频率调节(DVFS)系统,并对该技术的可行性进行了建模分析,验证了自适应DVFS方式的有效性,同时也给出了评估DVFS仿真的有效途径.     

基于功耗大小的DVS频率选择策略

动态电压调节技术（DynamicVoltageScaling,DVS）是一种有效的运用于实时嵌入式系统中的低功耗技术。动态电源管理（DynamicPowerManagement,DPM）是一种通过选择性关闭处于欠负载状态的模块,使系统功耗最小化的策略。实时嵌入式系统中DVS技术不仅要实现系统功耗的降低,同时也要兼顾系统的实时性。但是,单纯的DVS技术或是DPM技术都不能完全解决实时嵌入式系统中的功耗问题。文章针对已有的动态电压调节策略,分析DPM策略在动态电压调节过程中对系统总功耗的影响,从而提出基于功耗大小的DVS控制策略。     

基于钛酸锶钡变容管的可调匹配网络

采用钛酸锶钡(BST)薄膜变容管作为可调电容元件,在LaAlO3基片上采用微细加工技术制备了共面波导结构的C-L-Cπ型可调匹配网络。仿真及测试结果表明,通过在BST薄膜变容管上施加直流偏置电压对BST变容管的电容进行调节,可以在740～770 MHz频率范围内,实现该匹配网络与终端负载之间良好的阻抗匹配。其中,在760 MHz时测得的匹配网络的反射系数S11达到–45.8 dB。     

基于锯齿波信号控制的扫频信号发生电路的设计

为将示波器用于网络的幅频特性测试中，用集成函数发生器ICL8038设计成由锯齿波电压控制的扫频信号发生器，并通过实验测量给出了电路元件参数、频率调节范围和电压与频率的对应关系，该扫频发生器中心频率范围是10Hz-600kHz范围，调节电压小于0．2v／kHz。     

基于压电材料的振动能量收集器的谐振频率调节

振动能量收集器的最大输出电压发生在共振状态,因此其谐振频率应与环境振动频率一致.针对振动能量收集器与环境频率不匹配的问题,采用单自由度模型分析了悬臂梁-质量块结构的振动能量收集器谐振频率等性能,加工并测试了压电式的微型振动能量收集器样机,结果谐振频率的误差最大为6％.通过质量调节方法进一步将样机的谐振频率调节了10.5 Hz的宽度.针对50 Hz的振动环境,将谐振频率为58.7 Hz的样机调节到了50.4 Hz,输出电压提高了4倍.     

基于DVS的多核实时系统节能调度

动态电压调节是一种有效的节能技术．本文提出了多核处理器平台上的一种近似最优的动态电压调节算法．算法将电压调节问题转化为松弛时间分配问题，由任务集结构找到存在的松弛时间，针对不同类型的松弛时间，使用了并行补偿等分配方法．实验结果表明本文的算法能够有效的降低能量消耗且具有较低的时间复杂度．     

GALDS: a complete framework for designing multiclock ASICs and SoCs

A Globally Asynchronous, Locally Synchronous (GALS) system with dynamic voltage and frequency scaling can use the slowest frequency possible to accomplish a task with minimal power consumption. With the mechanism for implementing dynamic voltage scaling at each synchronous domain left up to the designer, our Globally Asynchronous, Locally Dynamic System (GALDS) provides a top-down, system-level means to maximize power reduction in an integrated circuit and facilitate system-on-a-chip (SoC) design. Our solution includes three distinct components: a novel bidirectional asynchronous FIFO to communicate between independently clocked synchronous blocks , an all-digital dynamic clock generator to quickly and glitchlessly switch between frequencies and a digitally controlled oscillator to generate the global fixed frequency clocks required by the all-digital dynamic clock generator. In addition to being capable of reducing power consumption when combined with dynamic voltage scaling, a GALDS design benefits from numerous other advantages such as simplified clock distribution, high performance operation and faster time-to-market through the modular nature of the architecture.     

A fully digital, energy-efficient, adaptive power-supply regulator

A voltage scaling technique for energy-efficient operation requires an adaptive power-supply regulator to significantly reduce dynamic power consumption in synchronous digital circuits. A digitally controlled power converter that dynamically tracks circuit performance with a ring oscillator and regulates the supply voltage to the minimum required to operate at a desired frequency is presented. This paper investigates the issues involved in designing a fully digital power converter and describes a design fabricated in a MOSIS 0.8-μm process. A variable-frequency digital controller design takes advantage of the power savings available through adaptive supply-voltage scaling and demonstrates converter efficiency greater than 90% over a dynamic range of regulated voltage levels     

传感器网络的任务双效节能调度研究

能源供应有限性是局限传感器网络的性能和存活寿命的重要因素,本文从传感器网络节点的任务调度出发,提出动态能量管理DPM和动态电压/频率调节DV/FS的双效处理器节能调度算法,即DV/FS-RM和DV/FS-EDF调度算法;在DPM动态控制空闲任务进入休眠的同时,在保证节点的实时性的前提下,通过DV/FS-RM或DV/FS-EDF算法降低处理器频率,达到更好的节能效果.实验显示,该节能任务调度算法使以电池为能源的传感器网络节点的生存期成倍地延长.     

A survey and measurement study of GPU DVFS on energy conservation

Energy efficiency has become one of the top design criteria for current computing systems. The dynamic voltage and frequency scaling (DVFS) has been widely adopted by laptop computers, servers, and mobile devices to conserve energy, while the GPU DVFS is still at a certain early age. This paper aims at exploring the impact of GPU DVFS on the application performance and power consumption, and furthermore, on energy conservation. We survey the state-of-the-art GPU DVFS characterizations, and then summarize recent research works on GPU power and performance models. We also conduct real GPU DVFS experiments on NVIDIA Fermi and Maxwell GPUs. According to our experimental results, GPU DVFS has significant potential for energy saving. The effect of scaling core voltage/frequency and memory voltage/frequency depends on not only the GPU architectures, but also the characteristic of GPU applications.     

动态电压调整多处理器实时系统任务调度

动态电压调整DVS（Dynamic Voltage Scaling）是根据处理器电压（速度）降低之后，能量消耗平方级的减少这一原理提出的。文章通过DVS机制在多处理器实时系统中进行任务调度．通过对任务调度中的静态能量管理进行分析，在此基础上提出了一种新的基于DVS的适用于多处理器实时系统中的调度算法。这种新的调度算法是通过对贪婪法调度进行研究，发现其不足．并以此为基础进行改进。结合了动态电压调整的多处理器实时系统任务调度的能量消耗比普通的任务调度能量消耗有了很大的改善。     

A 2.4-Gsample/s DVFS FFT Processor for MIMO OFDM Communication Systems

This paper presents a new dynamic voltage and frequency scaling (DVFS) FFT processor for MIMO OFDM applications. By the proposed multimode multipath-delay-feedback (MMDF) architecture, our FFT processor can process 1-8-stream 256-point FFTs or a high-speed 256-point FFT in two processing domains at minimum clock frequency for DVFS operations. A parallelized radix-2⁴ FFT algorithm is also employed to save the power consumption and hardware cost of complex multipliers. Furthermore, a novel open-loop voltage detection and scaling (OLVDS) mechanism is proposed for fast and robust voltage management. With these schemes, the proposed FFT processor can operate at adequate voltage/frequency under different configurations to support the power-aware feature. A test chip of the proposed FFT processor has been fabricated using UMC 90 nm single-poly nine-metal CMOS process with a core area of 1.88 times1.88 mm² . The SQNR performance of this FFT chip is over 35.8 dB for QPSK/16-QAM modulation. Power dissipation of 2.4 Gsample/s 256-point FFT computations is about 119.7 mW at 0.85 V. Depending on the operation mode, power can be saved by 18%-43% with voltage scaling in TT corner.     

基于嵌入式处理器的系统级低功耗管理研究

针对嵌入式系统低功耗设计问题,分析了动态功率管理DPM和动态电压/频率调节DVFS两种嵌入式功耗管理策略,并提出了系统级低功耗控制框架.讨论了基于嵌入式处理器i.MX1硬件平台实现系统级功耗控制方案,并给出了具体的设计方法.实际应用表明,该设计方案可有效降低系统能耗.     

电压调节技术用于SoC低功耗设计

针对便携设备在SOC系统设计中的功耗问题，通过电压调节和电压控制的方法来达到降低功耗的目的。可以用两种方法来实现，一种是开环电压调节(动态)，另一种是闭环(自适应)电压控制的方法。     

A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling

A single-chip H.264 and MPEG-4 audio-visual LSI for mobile applications including terrestrial digital broadcasting system (ISDB-T / DVB-H) with a module-wise, dynamic voltage/frequency scaling architecture is presented for the first time. This LSI can keep operating even during the voltage/frequency transition, so there is no performance overhead. It is realized through a dynamic deskewing system and an on-chip voltage regulator with slew rate control. By the combination with traditional low power techniques such as embedded DRAM and clock gating, it consumes only 63 mW in decoding QVGA H.264 video at 15 frames/sec and MPEG-4 AAC LC audio simultaneously.     

Adaptive fault-tolerant DVFS with dynamic online AVF prediction

Advances in silicon technology and shrinking the feature size to nanometer levels make random variations and low reliability of nano-devices the most important concern for fault-tolerant design. Design of reliable and fault-tolerant embedded processors is mostly based on developing techniques that compensate reliability shortcomings by adding hardware or software redundancy. The recently-proposed redundancy adding techniques are generally applied uniformly to all parts of a system and lead to heavy overheads and inefficiencies in terms of performance, power, and area. Efficient employment of non-uniform redundancy becomes possible when a quantitative analysis of a system behavior while encountering transient faults is provided. In this work, we present a quantitative analysis of the behavior of an embedded processor regarding transient faults and propose a new approach that accurately predicts the architecture vulnerability factor (AVF) in real-time. Another critical concern in design of new-silicon processors is power consumption issue. Dynamic voltage and frequency scaling (DVFS) is an effective method for controlling both energy consumption and performance of a system. Since rate of radiation-induced transient faults depends on operating frequency and supply voltage, DVFS techniques are recently shown to have compromising effects on electronic system reliability. Therefore, ignoring the effects of voltage scaling on fault rate could considerably degrade the system reliability. Here, by exploiting the proposed online AVF prediction methodology and based on analytic derivation, we propose a reliability-aware adaptive dynamic voltage and frequency scaling (DVFS) approach in case study of Multi-Processor System on Chip (MPSoC) with Multiple Clock Domain (MCD) pipeline architectures in which the frequency and voltage are scaled by simultaneously considering all three of power consumption, reliability, and performance. Comparing to the traditional methods of reliability-aware DVFS systems, the proposed reliability-aware DVFS method yields 50% better power saving at the same reliability level.