A CMOS operational amplifier with low impedance drive capability

A CMOS operational amplifier capable of delivering 160 mW of power to a 100 /spl Omega/ load while only dissipating 7 mW of quiescent power is described. The amplifier consists of three stages, the last of which is a transconductance output driver. The output stage is operated class B with less than 2 percent typical THD. A method of setting crossover by ratioing current mirror loads to parallel invertors is shown. Experimental results are presented showing various nominal operating characteristics.     

A 1.7-1.9 THz local oscillator source

We report on the design and performance of a /spl times/2/spl times/3/spl times/3 frequency multiplier chain to the 1.7-1.9 THz band. GaAs-based planar Schottky diodes are utilized in each stage. A W-band power amplifier, driven by a commercially available synthesizer, was used to pump the chain with 100 mW of input power. The peak measured output power at room temperature is 3 /spl mu/W at 1740 GHz. When cooled to 120 K, the chain provides more than 1.5 /spl mu/W from 1730 to 1875 GHz and produced a peak of 15 /spl mu/W at 1746 GHz.     

An integrated 200-W class-D audio amplifier

An integrated stereo class-D audio power amplifier realized in a silicon-on-insulator (SOI)-based BCD technology is presented. The amplifier is capable of delivering 2/spl times/100 W in two 4-/spl Omega/ loads at a supply voltage of 60 V. A second-order feedback loop is used to suppress supply ripple and pulse-shape errors in the switching power stage. The limiting factor in the performance of any class-D amplifiers is the quality of the switching power stage. A high-speed low-current levelshifter and a robust deadtime control arrangement are proposed that enable the realization of a robust high-quality switching power stage. Some practical issues with respect to robustness and electromagnetic compatibility are discussed.     

A 25 ns 64K static RAM

A high-performance 64K/spl times/1-bit CMOS SRAM is described. The RAM has an access time of 25 ns with active power of 350 mW and standby power of 15 mW. The access time has been obtained by using a 1.5 /spl mu/m rule CMOS process, advanced double-level A1 interconnection technology, an equalizer circuit, and a digit line sense amplifier that is the first sense amplifier directly connected to digit lines. The WRITE recovery circuit is effective in improving WRITE characteristics, and a block selecting circuit was used for low power dissipation.     

Low-power InP/GaAsSb/InP DHBT cascode transimpedance amplifier with GBP/P/sub dc/ of 7.2 GHz/mW

A low-power high gain-bandwidth monolithic cascode transimpedance amplifier using novel InP/GaAsSb/InP DHBT technology was investigated. The amplifier exhibited state-of-the-art performance of 17.3 dB gain, 12 GHz bandwidth, 55 dB/spl Omega/ transimpedance, and a corresponding gain-bandwidth of 6.7 THz/spl Omega/ while consuming only 12.2 mW DC power. It also achieved good gain-bandwidth-product per DC power figure-of-merit (GBP/P/sub dc/) of 7.2 GHz/mW     

An ultra-low power InAs/AlSb HEMT Ka-band low-noise amplifier

The first antimonide-based compound semiconductor (ABCS) MMIC, a Ka-Band low-noise amplifier using 0.25-/spl mu/m gate length InAs/AlSb metamorphic HEMTs, has been fabricated and characterized on a 75 /spl mu/m GaAs substrate. The compact 1.1 mm/sup 2/ three-stage Ka-band LNA demonstrated an average of 2.1 dB noise-figure between 34-36 GHz with an associated gain of 22 dB. The measured dc power dissipation of the ABCS LNA was an ultra-low 1.5 mW per stage, or 4.5 mW total. This is less than one-tenth the dc power dissipation of a typical equivalent InGaAs/AlGaAs/GaAs HEMT LNA. Operation with degraded gain and noise figure at 1.1 mW total dc power dissipation is also verified. These results demonstrate the outstanding potential of ABCS HEMT technology for mobile and space-based millimeter-wave applications.     

Analysis of gain improvements through a pump reflector in Er/sup 3+/-doped optical amplifiers in the presence of concentration quenching

We numerically examine the small-signal gain improvements possible when the pump light is reflected in erbium-doped amplifiers suffering from concentration quenching caused by homogeneous and inhomogeneous energy-transfer upconversion. For an unquenched amplifier, the improvement is larger for a pump power of 20 mW than it is at 100 mW. On the other hand, at a pump power of 100 mW, the reflector is found to be efficient for a quenched amplifier, with a maximum improvement of 6.5 dB. We also find that the reflector is more efficient at 1.535 /spl mu/m than it Is at 1.550 /spl mu/m, under all examined operating conditions.     

An inductance enhancement technique and its application to a shunt-peaked 2.5 Gb/s transimpedance amplifier design

This brief presents a bandwidth enhancement technique that is applicable to gigahertz-range broadband circuits. Using the inductance enhancement technique proposed in this brief, a 2.5-Gb/s transimpedance amplifier (TIA) has been implemented based on a 0.35-/spl mu/m CMOS technology. With the input noise reduction, the TIA with the proposed active inductor loads improves the overall system performances including more that 90% increase in bandwidth. Measurements show the bandwidth of 1.73 GHz, transimpedance gain of 68 dB/spl Omega/, and the averaged input referred noise current of 3.3 pA//spl radic/Hz, respectively, while dissipating 50 mW of dc power.     

A high performance 1 Mbit EPROM

A high-performance 1-Mb EPROM has been developed by utilizing advanced 1.2-/spl mu/m minimum design rule technology. The device technology used is n-channel E/D MOS. The memory cell size is 5.5/spl times/7.5 /spl mu/m and the die size is 9.4/spl times/7.2 mm. The word organization is changeable between 64K words/spl times/16 bits and 128K words/spl times/8 bits. The active power dissipation is 500 mW and the standby power dissipation is 150 mW. The access time is typically 200 ns. The programming voltage is 12-14 V and the programming pulse width is typically 1 ms/word. In order to realize such a high-density, high-speed, low power 1-Mb EPROM, 1.2-/spl mu/m minimum patterning process technology, a high-speed sense amplifier, and a high-speed decoder are used.     

High-power 1.5-/spl mu/m InGaAsP-InP slab-coupled optical waveguide amplifier

We report the first demonstration of a high-power semiconductor optical amplifier (SOA) based on the slab-coupled optical waveguide concept. This concept allows the realization of SOAs having large fundamental optical modes, low loss, and small optical confinement factor. These attributes support large output saturation power, long length for efficient heat removal, and direct butt-coupling to single-mode fibers. The 1.5-/spl mu/m InGaAsP-InP quantum-well amplifier described here has a length of 1 cm, 1/e/sup 2/ intensity widths of 4 /spl mu/m (vertical) and 8 /spl mu/m (horizontal), a fiber-to-fiber gain of 13 dB, and a fiber-coupled output saturation power of 630 mW (+28 dBm). The measured butt-coupling efficiency between the amplifier and SMF-28 is 55%. Thus, the output saturation power of the amplifier itself is approximately 1.1 W (+31 dBm).     

A 50-MS/s (35 mW) to 1-kS/s (15 /spl mu/W) power scaleable 10-bit pipelined ADC using rapid power-on opamps and minimal bias current variation

A novel rapid power-on operational amplifier and a current modulation technique are used in a 10-bit 1.5-bit/stage pipelined ADC in 0.18-/spl mu/m CMOS to realize power scalability between 1 kS/s (15 /spl mu/W) and 50 MS/s (35 mW), while maintaining an SNDR of 54-56 dB for all sampling rates. The current modulated power scaling (CMPS) technique is shown to enhance the power scaleable range of current scaling by 50 times, allowing ADC power to be varied by a factor of 2500 while only varying bias currents by a factor of 50. Furthermore, the nominal power is reduced by 20%-30% by completely powering off the rapid power-on opamps during the sampling phase in the pipeline's sample-and-holds.     

A high current drive CMOS output stage with a tunable quiescent current limiting circuit

A CMOS output stage based on a complementary common source with an original quiescent current limiting circuit is presented. The quiescent current can be varied over a wide range by means of a control current with no need to modify the transistor aspect ratios. The output stage has been coupled to a conventional complementary input stage to form a rail-to-rail buffer. A prototype with the inclusion of auxiliary pins for biasing and current monitoring purposes has been designed using the 1-/spl mu/m double-polysilicon BCD3S process of STMicroelectronics. On a single 5-V power supply, the maximum output current is 20 mA. The amplifier, biased for a total power dissipation of 1 mW, exhibits a total harmonic distortion of -58 dB at 1 kHz with 4-V peak-to-peak on a 330-/spl Omega/ load. Correct operation of the quiescent current limiting circuit has been demonstrated for a minimum supply voltage of 2.2 V.     

A high-speed 850-nm optical receiver front-end in 0.18-/spl mu/m CMOS

A high-speed optical interface circuit for 850-nm optical communication is presented. Photodetector, transimpedance amplifier (TIA), and post-amplifier are integrated in a standard 0.18-/spl mu/m 1.8-V CMOS technology. To eliminate the slow substrate carriers, a differential n-well diode topology is used. Device simulations clarify the speed advantage of the proposed diode topology compared to other topologies, but also demonstrate the speed-responsivity tradeoff. Due to the lower responsivity, a very sensitive transimpedance amplifier is needed. At 500 Mb/s, an input power of -8 dBm is sufficient to have a bit error rate of 3/spl middot/10/sup -10/. Next, the design of a broadband post-amplifier is discussed. The small-signal frequency dependent gain of the traditional and modified Cherry-Hooper stage is analyzed. To achieve broadband operation in the output buffer, so-called "f/sub T/ doublers" are used. For a differential 10 mV/sub pp/ 2/sup 31/-1 pseudo random bit sequence, a bit error rate of 5/spl middot/10/sup -12/ at 3.5 Gb/s has been measured. At lower bit-rates, the bit error rate is even lower: a 1-Gb/s 10-mV/sub pp/ input signal results in a bit error rate of 7/spl middot/10/sup -14/. The TIA consumes 17mW, while the post-amplifier circuit consumes 34 mW.     

Wideband fully differential CMOS transimpedance preamplifier

A fully differential transimpedance amplifier has been designed and implemented in 0.18 /spl mu/m standard digital CMOS technology. The parallel feedback circuit topology is adopted to broaden the bandwidth. It can operate at 10 Gbit/s with the dynamic range from 25 /spl mu/A up to 2.5 mA. The power consumption is only 88 mW under 2 V supply voltage.     

35-dB gain Tm-doped ZBLYAN fiber amplifier operating at 1.65 /spl mu/m

We demonstrate the first high gain rare-earth-doped fiber amplifier operating at 1.65 /spl mu/m. It consists of ZBLYAN fiber with a Tm/sup 3+/-doped core and Tb/sup 3+/-doped cladding, pumped by 1.22 /spl mu/m laser diodes. It is possible to achieve efficient amplification with Tm/sup 3+/ ions if their amplified spontaneous emission (ASE) in the 1.75 to 2.0 /spl mu/m wavelength region is suppressed by doping Tb/sup 3+/ ions in the cladding. A two-stage-type fiber amplifier is constructed and a signal gain of 35 dB is achieved for a pump power of 140 mW. A gain over 25 dB is realized in the 1.65 /spl mu/m to 1.67 /spl mu/m wavelength region.     

A 35-ns 128K/spl times/8 CMOS SRAM

A 128 K/spl times/8-b CMOS SRAM with TTL input/output levels and a typical address access time of 35 ns is described. A novel data transfer circuit with dual threshold level is utilized to obtain improved noise immunity. A divided-word-line architecture and an automatic power reduction function are utilized to achieve a low operational power of 10 mW at 1 MHz, and 100 mW at 10 MHz. A novel fabrication technology, including improved LOCOS and highly stable polysilicon loads, was introduced to achieve a compact memory cell which measures 6.4/spl times/11.5 /spl mu/m/SUP 2/. Typical standby current is 2 /spl mu/A. The RAM was fabricated with 1.0-/spl mu/m design rules, double-level polysilicon, and double-level aluminum CMOS technology. The chip size of the RAM is 8/spl times/13.65 mm/SUP 2/.     

Single Miller capacitor frequency compensation technique for low-power multistage amplifiers

Due to the rising demand for low-power portable battery-operated electronic devices, there is an increasing need for low-voltage low-power low-drop-out (LDO) regulators. This provides motivation for research on high-gain wide-bandwidth amplifiers driving large capacitive loads. These amplifiers serve as error amplifiers in low-voltage LDO regulators. Two low-power efficient three-stage amplifier topologies suitable for large capacitive load applications are introduced here: single Miller capacitor compensation (SMC) and single Miller capacitor feedforward compensation (SMFFC). Using a single Miller compensation capacitor in three-stage amplifiers can significantly reduce the total capacitor value, and therefore, the overall area of the amplifiers without influencing their stability. Pole-splitting and feedforward techniques are effectively combined to achieve better small-signal and large-signal performances. The 0.5-/spl mu/m CMOS amplifiers, SMC, and SMFFC driving a 25-k/spl Omega///120-pF load achieve 4.6-MHz and 9-MHz gain-bandwidth product, respectively, each dissipates less than 0.42 mW of power with a /spl plusmn/1-V power supply, and each occupies less than 0.02 mm/sup 2/ of silicon area.     

A 600-MS/s 5-bit pipeline A/D converter using digital reference calibration

The design of a 600-MS/s 5-bit analog-to-digital (A/D) converter for serial-link receivers has been investigated. The A/D converter uses a closed-loop pipeline architecture. The input capacitance is only 170 fF, making it suitable for interleaving. To maintain low power consumption and increase the sampling rate beyond the amplifier settling limit, the paper proposes a calibration technique that digitally adjusts the reference voltage of each pipeline stage. Differential input swing is 400 mV/sub p-p/ at 1.8-V supply. Measured performance includes 25.6 dB and 19 dB of SNDR for 0.3-GHz and 2.4-GHz input frequencies at 600 MS/s for the calibrated A/D converter. The suggested calibration method improves SNDR by 4.4 dB at 600 MS/s with /spl plusmn/0.35 LSB of DNL and /spl plusmn/0.15 LSB of INL. The 180 /spl times/ 1500 /spl mu/m/sup 2/ chip is fabricated in a 0.18-/spl mu/m standard CMOS technology and consumes 70 mW of power at 600 MS/s.     

A 4-terminal wide-band monolithic amplifier

A bipolar monolithic amplifier is described which achieves 18 dB gain, 725 MHz-3 dB bandwidth and 4.4 dB noise figure. The circuit is housed in a 4-lead TO-46 package, consumes 180 mW of DC power and requires no external components. Input and output impedances are matched to 50 /spl Omega/ with VSWR less than 1.5 across the band. A high-power version of the circuit consumes 1 W of DC power and gives 152 mW output power at 200 MHz.     

S-band single-stage EDFA with 25-dB gain using distributed ASE suppression

We propose a novel compact design for a single-stage S-band erbium-doped fiber amplifier, wherein distributed suppression of C-band amplified spontaneous emission is provided by optimized bend loss in a coaxial core fiber. Simulations show that /spl sim/25-dB unsaturated gain over 30-nm bandwidth (1495-1525) nm is achievable with the designed module, using a nominal pump power of 500 mW. The noise figure of the amplifier varies between 4.5 and 8 dB from 1495 to 1525 nm. By proper designing, we have also ensured that the gain ripple over the entire 30-nm bandwidth is 相似文献