Low-frequency noise sources in polysilicon emitter BJT's: influenceof hot-electron-induced degradation and post-stress recovery

The noise properties of polysilicon emitter bipolar transistors are studied. The influences of the various chemical treatments and annealing temperatures, prior and after polysilicon deposition, on the noise magnitude are shown. The impact of hot-electron-induced degradation and post-stress recovery on the base and collector current fluctuations are also investigated in order to determine the main noise sources of these devices and to gain insight into the physical mechanisms involved in these processes     

Comparison of low frequency noise and high frequency performances of double and simple polysilicon Bi-CMOS BJT

The issue of this paper concerns 0.35 μm Bi-CMOS double polysilicon bipolar transistors and 0.5 μm Bi-CMOS simple polysilicon bipolar transistors. Low-frequency noise measurements are performed. Noise spectral densities are analysed versus bias and geometry. From these noise measurements, base and emitter series resistances are extracted. A comparison of both technologies is done. Though double polysilicon transistors have a more complex structure than the simple polysilicon ones, they exhibit similar or even better performances. Indeed, DC characteristics and noise levels are equivalent for both technologies. Double polysilicon transistors exhibit a reduction of the base resistance and a significant improvement of the transition frequency f_T is obtained.     

基于Matlab的基极电流理想因子提取方法研究

采用Matlab数字分析方法,结合多晶硅发射极双极器件基极电流的构成情况,阐述了不同理想因子电流成分分离的基本原理和数学方法。利用该方法分析了多晶硅发射极双极器件在正向大电流激励下的电参数退化过程中不同理想因子基极电流的变化情况,分析了导致各电流分量变化的物理机制。该理想因子提取方法普遍适用于各类双极型器件。     

Leakage current mechanisms in SiGe HBTs fabricated using selectiveand nonselective epitaxy

SiGe heterojunction bipolar transistors (HBTs) have been fabricated using selective epitaxy for the Si collector, followed in the same growth step by nonselective epitaxy for the p⁺ SiGe base and n-Si emitter cap. DC electrical characteristics are compared with cross-section TEM images to identify the mechanisms and origins of leakage currents associated with the epitaxy in two different types of transistor. In the first type, the polysilicon emitter is smaller than the collector active area, so that the extrinsic base implant penetrates into the single-crystal Si and SiGe around the perimeter of the emitter and the polycrystalline Si and SiGe extrinsic base. In these transistors, the Gummel plots are near-ideal and there is no evidence of emitter/collector leakage. In the second type, the collector active area is smaller than the polysilicon emitter, so the extrinsic base implant only penetrates into the polysilicon extrinsic base. In these transistors, the leakage currents observed depend on the base doping level. In transistors with a low doped base, emitter/collector and emitter/base leakage is observed, whereas in transistors with a high doped base only emitter/base leakage is observed. The emitter/collector leakage is explained by punch through of the base caused by thinning of the SiGe base at the emitter perimeter. The emitter/base leakage is shown to be due to a Poole-Frenkel mechanism and is explained by penetration of the emitter/base depletion region into the p⁺ polysilicon extrinsic base at the emitter periphery. Variable collector/base reverse leakage currents are observed and a variety of mechanisms are observed, including Shockley-Read-Hall recombination, trap assisted tunneling, Poole-Frenkel and band to band tunneling. These results are explained by the presence of polysilicon grains on the sidewalls of the field oxide at the collector perimeter     

Low-frequency noise in polysilicon emitter bipolar transistors

The low-frequency noise in polysilicon emitter bipolar transistors is investigated. Transistors with various geometries and various properties of the oxide layer at the monosilicon polysilicon interface are studied. The main 1/f noise source proved to be located in the oxide layer. This source causes both 1/f noise in the base current S_Ib and 1/f noise in the emitter series resistance S_re The magnitude of the 1/f noise source depends on the properties of the oxide layer. The 1/f noise is ascribed to barrier height fluctuations of the oxide layer resulting in transparency fluctuations for both minority and majority carriers in the emitter, giving rise to S_Ib and S _re respectively. It is also shown that a low transparency of the oxide layer also reduces the contribution of mobility fluctuations to S_Ib     

Investigation of boron diffusion in polysilicon and its applicationto the design of p-n-p polysilicon emitter bipolar transistors withshallow emitter junctions

Ion implantation of boron into undoped polysilicon is utilized. The main goals are to characterize the diffusion of implanted boron from polysilicon, and to correlate the diffusion behavior with the electrical properties of shallow (<500 Å) p-n-p polysilicon emitter bipolar transistors. It is shown that diffusion and electrical activity problems are encountered with boron polysilicon emitters which are not present with arsenic. Base current and emitter resistance are measured on shallow p-n-p polysilicon emitter transistors, and it is shown that the use of a deliberately grown interfacial oxide layer can decrease the base current by a factor of 10 and increase the emitter resistance by a factor of around 2. Comparisons with identical n-p-n polysilicon emitter transistors show that the modeled interfacial oxide, tunneling parameters for n-p-n and p-n-p devices are inconsistent     

Low-frequency noise in UHV/CVD epitaxial Si and SiGe bipolartransistors

In this work a comprehensive investigation of low-frequency noise in ultrahigh vacuum/chemical vapor deposition (UHV/CVD) Si and SiGe bipolar transistors is presented. The magnitude of the noise of SiGe transistors is found to be comparable to the Si devices for the identical profile, geometry, and bias. A comparison with different technologies demonstrates that the SiGe devices have excellent noise properties compared to AlGaAs/GaAs heterojunction bipolar transistors (HBT's) and conventional Si bipolar junction transistors (BJT's). Results from different bias configurations show that the 1/f base noise source is dominant in these devices. The combination of a 1/Area dependence on geometry and near quadratic dependence on base current indicates that the 1/f noise sources are homogeneously distributed over the entire emitter area and are probably located at the polysilicon-Si interface. Generation/recombination (Gm) noise and random telegraph signal (RTS) noise was observed in selected Si and SiGe devices. The bias dependence and temperature measurements suggest that these G/R centers are located in the base-emitter space charge region. The activation energies of the G/R traps participating in these noise processes were found to be within 250 meV of the conduction and valence band edges     

多晶硅有晶体管直流特性研究

研究了砷注入多晶硅发射极晶体管的直流特性,并与采用常规平面工艺制作的晶体管性能的进行比较。结果表明多晶硅发射极晶体管具有较高的发射效率,高的电流能力,改善了ＥＢ击穿和ＣＢ击穿,电流增益依赖于淀积多晶硅前的表面处理条件。     

Random telegraph noise in SiGe HBTs: Reliability analysis close to SOA limit

In this paper, we present extensive random telegraph signal (RTS) noise characterization in SiGe heterojunction bipolar transistors. RTS noise, observed at the base, originates at the emitter periphery while at the collector side distinct RTS noise is observed at high-injection that originates from the traps in the shallow trench regions. Time constants extracted from RTS during aging tests allow understanding of trap dynamics and new defect formation within the device structure. This paper provides the first demonstration of RTS measurements during accelerated aging tests to study and understand generation of defects under bias stress in SiGe HBTs operating at the limit of their safe-operating area.     

Low frequency noise in complementary npn and pnp polysilicon emitter bipolar junction transistors

Low frequency noise characteristics of high voltage, high performance complementary polysilicon emitter bipolar transistors are described. The influence of the base biasing resistance, emitter geometry and temperature on the noise spectra are discussed. The npn transistors studied exhibited 1/f and shot noise, but the pnp transistors are characterized by significant generation–recombination noise contributions to the total noise. For both types of transistors, the measured output noise is determined primarily by the noise sources in the polysilicon–monosilicon interface. The level of the 1/f noise is proportional to the square of the base current for both npn and pnp transistors. The contribution of the 1/f noise in the collector current is also estimated. The area dependence of 1/f noise in both types of transistors as well as other npn bipolar transistors are presented.     

The influence of BF2 and F implants on the 1/f noise inSiGe HBTs with a self-aligned link base

A study is made of 1/f noise in SiGe heterojunction bipolar transistors (HBTs) fabricated using selective growth (SEG) of the Si collector and nonselective growth (NSEG) of the SiGe base and Si emitter cap. The transistors incorporate a self-aligned link base formed by BF ₂ implantation into the field oxide below the p⁺ polysilicon extrinsic base. The influence of this BF₂ implant on the 1/f noise is compared with that of a F implant into the polysilicon emitter. Increased base current noise S_IB and base current are seen in transistors annealed at 975°C, compared with transistors annealed at 950 or 900°C. At a constant collector current, both the BF₂ and F implants reduce S_IB, whereas at a constant base current, only the BF₂ implant reduces S_IB. This result indicates that the BF₂ implant decreases the intensity of the base current noise source whereas the F implant decreases the base current. The proposed explanation for the increased 1/f noise is degradation of the surface oxide by viscous flow at 975°C under the influence of stress introduced during selective Si epitaxy. The influence of the BF₂ implant on the noise is explained by the relief of the stress and hence the prevention of viscous oxide flow     

双极晶体管发射极电阻的提取方法及应用研究

以双多晶自对准互补双极器件中NPN双极晶体管为例,阐述了发射极电阻提取的基本原理和数学方法。在大电流情况下,NPN管的基极电流偏离理想电流是发射极串联电阻效应引起的。该提取方法综合考虑了辐照过程中NPN管的电流增益退化特性,分析了总剂量辐照效应对NPN管的损伤机理和模式。该提取方法适用于多晶硅发射极器件,也适用于SiGe HBT器件。     

Optimization of a 0.6 μm, single polysilicon emitter bipolar technology versus narrow emitter effects

A novel 0.6 μm, single polysilicon emitter bipolar technology has been optimized in order to reduce the consequences of narrow emitter effects (NEE) appearing at the laterals of the emitter area. The primary technological mechanisms of these effects have been studied and differentiated for this technology. They have been found to be the polysilicon over-etch into the underlying silicon, the pedestal oxidation, both of them in the area of the extrinsic base implantation, and the extrinsic base lateral diffusion. Designs of experiments techniques have been used in order to study all these technological elements and their effect on the final performance of the transistors. Common emitter current gain variation versus emitter width has been studied by means of test structures and an optimization method is proposed. Lateral diffusion of extrinsic base has been identified as main source of NEE in this technology, which reduces the transistors current gain. Pedestal oxidation has been identified as secondary source of these effects, acting in an opposite way of lateral diffusion increasing the transistors current gain. This opposed effects have been tuned in the technological optimization to minimize the NEE by means of a mutual compensation.     

DPSA双极器件中的1/f噪声特性研究

在现代高性能模拟集成电路设计中,噪声水平是影响电路性能的关键因素之一.研究了双多晶自对准高速互补双极NPN器件中发射板结构对器件直流和低频噪声性能的影响.实验结果表明,多晶硅发射极与单晶硅界面超薄氧化层以及发射极几何结构是影响多晶硅发射极双极器件噪声性能的主要因素.     

Characterisation of emitter/base leakage currents in SiGe HBTs produced using selective epitaxy

SiGe heterojunction bipolar transistors have been fabricated using selective epitaxy for the Si collector, followed in the same growth step by non-selective epitaxy for the SiGe base and Si emitter cap. E/B leakage currents are compared with cross-section TEM images to identify sources of leakage currents associated with the epitaxy. In addition, the influence of the position of the extrinsic base implant with respect to the polysilicon emitter on the leakage currents is studied. The emitter/base leakage currents are modelled using Shockley–Read–Hall recombination, trap-assisted tunnelling and Poole–Frenkel (PF) generation. The position of the extrinsic base implant is shown to have a strong influence on the leakage currents. The PF effect dominates the emitter/base leakage current in transistors in which the collector area is smaller than the polysilicon emitter. This result is explained by penetration of the emitter/base depletion region into the p⁺ polysilicon extrinsic base at the perimeter of the emitter. These leakage currents are eliminated when the collector area is increased so that the extrinsic base implant penetrates into the single-crystal silicon at the perimeter of the emitter.     

Lateral base design rules for optimized low-frequency noise of differentially grown SiGe heterojunction bipolar transistors

The low-frequency noise dependence on lateral design parameters was investigated for SiGe heterojunction bipolar transistors fabricated by differential epitaxy. The low-frequency noise was found to vary substantially as a function of the extrinsic base design. The dominant noise sources were located either at the interface between the polycrystalline and epitaxial Si/SiGe base, in the epitaxial Si/SiGe base link region, in the base–emitter depletion region, or at the thin SiO₂ interface layer between the polysilicon and monosilicon emitter. Boron was found to passivate interfacial traps, acting as low-frequency noise sources. Generation–recombination noise with a strong dependence on the lateral electrical field was observed for some of the designs.     

Trade-off between emitter resistance and current gain inpolysilicon emitter bipolar transistors with intentionally growninterfacial oxide layers

Experimental measurements of emitter resistance and current gain in polysilicon emitter bipolar transistors that have received annealing to break up an intentionally grown RCA oxide interfacial layer are presented. An anneal of 900°C for 10 min in a nitrogen ambient of the interfacial layer prior to polysilicon doping resulted in a decrease in emitter resistance by approximately a factor of 5, with an increase in base saturation current of only 25% while still maintaining a current gain of around 500. The authors believe that this is the largest trade-off in emitter resistance versus current gain demonstrated so far for polysilicon transistors with an RCA interfacial layer. These results support a theory previously proposed by the authors (1991) predicting that significant trade-offs between emitter resistance and current gain can be obtained if an intentionally grown interfacial oxide layer in polysilicon emitter bipolar transistors is annealed so as to induce only partial breakup such that most of the layer remains intact     

High-low polysilicon-emitter SiGe-base bipolar transistors

Self-aligned heterojunction bipolar transistors with a high-low emitter profile consisting of a heavily doped polysilicon contact on top of a thin epitaxial emitter cap have been fabricated. The low doping in the single-crystal emitter cap allows a very high dopant concentration in the base with low emitter-base reverse leakage and low emitter-base capacitance. The thin emitter cap is contacted by heavily doped polysilicon to reduce the emitter resistance, the base current, and the emitter charge storage. A trapezoidal germanium profile in the base ensures a small base transit time and adequate current gain despite high base doping. The performance potential of this structure was simulated and demonstrated experimentally in transistors with near-ideal characteristics, very small reverse emitter-base leakage current, and 52-GHz peak f_max, and in unloaded ECL and NTL ring oscillators with 24- and 19-ps gate delays, respectively     

Extraction of emitter and base series resistances of bipolartransistors from a single DC measurement

A new procedure for extracting the emitter and base series resistances of bipolar junction transistors is presented. The parameters are extracted from a single measurement in the forward active region on one transistor test structure with two separate base contacts, making it a simple and attractive tool for bipolar transistor characterization. The procedure comprises two methods for extracting the emitter resistance and two for extracting the base resistance. The choice of method is governed by the amount of current crowding or conductivity modulation present in the intrinsic base region. The new extraction procedure was successfully applied to transistors fabricated in an in-house double polysilicon bipolar transistor process and a commercial 0.8-μm single polysilicon BiCMOS process. We found that the simulated and measured Gummel characteristics are in excellent agreement and the extracted series resistances agree well with those obtained by means of HF measurements. By adding external resistors to the emitter and base and then extracting the series resistances, we verified that the two base contact test structure offers a simple means of separating the influence of emitter and base series resistances on the transistor characteristics     

Emitter and base transit time of polycrystalline silicon emittercontact bipolar transistors

The author formulates transit time in the neutral emitter region, τ_E, and in the neutral base region τ_B, of polycrystalline silicon emitter contact bipolar transistors. An analytical theory derived for τ_E of polysilicon emitter contact bipolar transistors and its dependence on the emitter junction depth, the polysilicon thickness, and the base width are presented. The influence of bandgap narrowing on τ_E and τ_B is analyzed. Bandgap narrowing increases τ_E , but τ_B is insensitive to it. τ_E is proportional to base width W_B and τ_B to W²_B. τ_E is not negligible compared to τ_B when W_B is less than 100 nm. Reducing emitter junction depth and polysilicon thickness is indispensable to developing shallow base bipolar transistors